CN100464396C - Method for fabricating thin film transistor - Google Patents
Method for fabricating thin film transistor Download PDFInfo
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- CN100464396C CN100464396C CNB2005101174618A CN200510117461A CN100464396C CN 100464396 C CN100464396 C CN 100464396C CN B2005101174618 A CNB2005101174618 A CN B2005101174618A CN 200510117461 A CN200510117461 A CN 200510117461A CN 100464396 C CN100464396 C CN 100464396C
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Abstract
The method for preparing thin film transistor includes steps: forming grid electrode on base plate; forming grid insulation layer on the base plate to cover the grid electrode; forming patternized semiconductor layer (PSL) on grid insulation layer and above the grid electrode; forming first and second conducting layers on the PSL; patternizing second conducting layer, and at same time, making second conducting layer on two sides above the grid electrode possess taper profile, and exposing first conducting layer; carrying out first plasma process step to form first protection layer on surface of the second conducting layer and the taper profile; removing first conducting layer not covered by the first protection layer and second conducting layer in order to form source /drain electrodes. The invention can produce source/drain electrodes with fine sizes, and can prevent influence on electrical properties of element caused by diffusing metal ions of second conducting layer to PSL.
Description
Technical field
The present invention relates to a kind of manufacture method of thin-film transistor, and be particularly related to and a kind ofly can utilize the conductivity good metal, and then make the manufacture method of thin-film transistor with the meticulous source/drain of double-level-metal layer (double-metal layer) and size.
Background technology
Along with the development of photoelectric technology, digitized video or image device have become product common in the general daily life.In these digitized videos or image device, display is important man-machine communication interface.The user can read the running of information and then control device via display.
And thin-film transistor (TFT) is the driving element that is applied in the display.Generally speaking, thin-film transistor comprises grid (gate), channel layer (channel) and source/drain elements such as (source/drain).In recent years, when carrying out the making of source/drain, behind the first deposit multilayer metal level of meeting (as chromium/aluminium/chromium metal level or molybdenum/aluminium/molybdenum layer), utilize Wet-type etching that the multiple layer metal layer is carried out Patternized technique again.But, the trend of constantly dwindling along with live width, utilize the source/drain intraconnections (interconnection) of above-mentioned material made, will be subjected to the influence of resistance capacitance time delay effect (RCdelay), and make the running speed of thin-film transistor ease up.So, if can then can solve the problem of above-mentioned resistance capacitance time delay effect with the conductivity good metal as the material that forms the source/drain intraconnections.
Because the conductivity of copper is good, so the intraconnections technology of copper conductor will be following trend.But the problem that copper itself is had is: (1) when utilizing Wet-type etching, the size of wayward copper pattern; And in dry-etching, can be difficult for copper is carried out etching.(2) copper spreads easily, and may have influence on the electrical and contaminated equipment of channel layer.Therefore, generally still can utilize copper to cooperate the multiple layer metal layer of other metal (for example molybdenum), carry out the making of source/drain.
Fig. 1 is the known generalized section of utilizing the making of the source/drain that layer metal level more than molybdenum/copper/molybdenum carry out thin-film transistor.Please refer to Fig. 1, this thin-film transistor 100 comprises substrate 110, grid 120, gate insulation layer 130, semiconductor layer 140 and source/drain 150.Wherein, semiconductor layer 140 is made up of channel layer 142 and ohmic contact layer 144, and source/drain 150 is made up of with 156 on another molybdenum layer molybdenum layer 152, copper metal layer 154.
Please continue with reference to Fig. 1, when desire forms source/drain 150, can form patterning photoresist layer 160 earlier on thin-film transistor 100, be mask with this patterning photoresist layer 160 again, carries out Wet-type etching for beneath molybdenum layer 156 and copper metal layer 154.But, because the etch-rate of copper is greater than the etch-rate of molybdenum, so when carrying out Wet-type etching, promptly can cause the phenomenon of the side direction undercutting 170 represented (side undercut) as Fig. 1, thus, very likely can cause broken string, or produce the thin-film transistor 100 that does not meet dimensions.In addition, when carrying out Wet-type etching because copper metal layer 154 is to be soaked in the middle of the etching solution, thus copper ion can be diffused near the semiconductor layer 140 along with etching solution, and have influence on thin-film transistor 100 electrically.
In addition, after finishing above-mentioned wet etch process, can carry out dry-etching again to remove the molybdenum layer 152 of grid 120 tops, and (back channel etching is BCE) with the ohmic contact layer 144 that the removes grid 120 tops channel layer 142 with part to carry on the back the passage etch process.
Fig. 2 carries out the molybdenum layer that dry-etching removes the grid top, and the generalized section of carrying on the back the passage etch process.When carrying out dry-etching,,, and make electrically being affected of semiconductor layer 140 so copper atom still may be diffused near the semiconductor layer 140 because copper metal layer 154 is still and is exposed in the middle of the etching environment.In addition, because when carrying out dry-etching with back of the body passage etch process, molybdenum layer 152, ohmic contact layer 144 and channel layer 142 be still with patterning photoresist layer 160 as mask, so will have the side 180 with the justified margin of patterning photoresist layer 160.It should be noted that both size differences are too big, thus, will be unfavorable for the meticulous source/drain of manufactured size 150 between the lateral undercut 170 of the side 180 of molybdenum layer 152 and copper metal layer 154.
Summary of the invention
In view of the foregoing, purpose of the present invention just provides a kind of manufacture method of thin-film transistor, and it is suitable for utilizing the conductivity good metal, and then making has multiple layer metal layer structure and the meticulous source/drain of size.
The present invention proposes a kind of manufacture method of thin-film transistor, and it comprises the following steps.At first, on substrate, form grid.Then, on substrate, form gate insulation layer with cover gate.Come again, forming patterned semiconductor layer on the gate insulation layer with above the grid.Then, on patterned semiconductor layer, form first conductive layer and second conductive layer in regular turn.Then, patterning second conductive layer makes second conductive layer of both sides, grid top have angled section (taper profile) simultaneously, and exposes first conductive layer.Continue it, carry out first plasma treatment process, make the surface of second conductive layer and angled section place form first protective layer.Afterwards, remove not by first conductive layer of first protective layer and the covering of second conductive layer, to form source/drain.
In one embodiment of this invention, the material of the second above-mentioned conductive layer comprises copper.
In one embodiment of this invention, the material of the first above-mentioned protective layer comprises cupric oxide or copper nitride.
In one embodiment of this invention, the material of the first above-mentioned conductive layer is that to be selected from molybdenum, molybdenum tungsten, tantalum and combination thereof one kind of.
In one embodiment of this invention, the above-mentioned employed reacting gas of first plasma treatment process is that to be selected from oxygen, nitrogen, nitrogen dioxide, ammonia and combination thereof one kind of.
In one embodiment of this invention, the method for above-mentioned patterning second conductive layer comprises the following steps.At first, form the patterning photoresist layer on substrate, its exposure is positioned at second conductive layer of grid top.Afterwards, be mask with the patterning photoresist layer, carry out wet etch process and be exposed out up to first conductive layer, and second conductive layer after etched has angled section with etching second conductive layer.
In one embodiment of this invention, above-mentioned removing is not to carry out dry etch process by the method for first conductive layer of first protective layer and the covering of second conductive layer, and the employed gas of this dry etch process is to be selected from sulphur hexafluoride (SF
6), oxygen (O
2), chlorine (Cl
2), hydrogen chloride (HCl), fluoroform (CHF
3) and make up one kind of.
In one embodiment of this invention, above-mentioned patterned semiconductor layer comprises patterning channel layer and patterning ohmic contact layer, and the patterning ohmic contact layer is positioned on the patterning channel layer.In one embodiment of this invention, the manufacture method of above-mentioned thin-film transistor also comprises carries on the back the passage etch process, with patterning ohmic contact layer and the patterning channel layer partly that removes the grid top.
In one embodiment of this invention, the above-mentioned method that forms grid on substrate comprises the following steps.On substrate, form the 3rd conductive layer and the 4th conductive layer at first, in regular turn.Then, patterning the 4th conductive layer.Continue it, carry out second plasma treatment process, make the surface of the 4th conductive layer form second protective layer.Afterwards, remove not the 3rd conductive layer that is covered by second protective layer and the 4th conductive layer, to form grid.
In one embodiment of this invention, the material of the 4th above-mentioned conductive layer comprises copper.
In one embodiment of this invention, the material of the second above-mentioned protective layer comprises cupric oxide or copper nitride.
In one embodiment of this invention, the material of the 3rd above-mentioned conductive layer is that to be selected from molybdenum, molybdenum tungsten, tantalum and combination thereof one kind of.
In one embodiment of this invention, the above-mentioned employed reacting gas of second plasma treatment process is that to be selected from oxygen, nitrogen, nitrogen dioxide, ammonia and combination thereof one kind of.
In one embodiment of this invention, the above-mentioned method that removes not the 3rd conductive layer that is covered by second protective layer and the 4th conductive layer is to carry out dry etch process, and the employed gas of this dry etch process is to be selected from sulphur hexafluoride (SF
6), oxygen (O
2), chlorine (Cl
2), hydrogen chloride (HCl), fluoroform (CHF
3) and make up one kind of.
In one embodiment of this invention, the method for above-mentioned patterning the 4th conductive layer comprises and carries out photoetching process and wet etch process.
The present invention is because of good copper and the molybdenum of employing conductivity, and making has the source/drain of double-level-metal layer.And utilize plasma treatment process that the surface of copper is handled, and make the copper metal layer on upper strata to carry out dry-etching with molybdenum layer and channel layer as mask to lower floor.Thus, the manufacture method of thin-film transistor of the present invention can prevent copper metal layer generation side direction undercutting (side undercut), and then produces the meticulous source/drain of size.And because the conductivity of copper metal layer is preferable, and then can solve resistance capacitance time delay effect, so that the running speed of thin-film transistor improves.
For above and other objects of the present invention, feature and advantage can be become apparent, preferred embodiment cited below particularly, and conjunction with figs. are described in detail below.
Description of drawings
Fig. 1 is the known generalized section of utilizing the making of the source/drain that layer metal level more than molybdenum/copper/molybdenum carry out thin-film transistor.
Fig. 2 carries out the molybdenum layer that dry-etching removes the grid top, and the generalized section of carrying on the back the passage etch process.
Fig. 3 A～Fig. 3 J is the steps flow chart generalized section of the manufacture method of a kind of thin-film transistor in the preferred embodiment of the present invention.
Fig. 4 A～Fig. 4 E is a kind of steps flow chart profile that forms the method for grid in the embodiments of the invention.
The main element description of symbols
100,500: thin-film transistor
110,300: substrate
120,310: grid
130,320: gate insulation layer
140: semiconductor layer
142: channel layer
144: ohmic contact layer
150: source/drain
152,156: the molybdenum layer
154: copper metal layer
160: the patterning photoresist layer
170: the side direction undercutting
180: the side
210,220: conductive layer
230: photoresist layer
240,370: plasma treatment process
250,380: protective layer
260,400: dry etch process
330: patterned semiconductor layer
332: the patterning channel layer
334: the patterning ohmic contact layer
340: the first conductive layers
350: the second conductive layers
352: angled section
360: the patterning photoresist layer
390: source/drain
410: back of the body passage etch process
Embodiment
Fig. 3 A～Fig. 3 J is the steps flow chart generalized section of the manufacture method of a kind of thin-film transistor in the preferred embodiment of the present invention.
At first, on substrate 300, form grid 310, as shown in Figure 3A.In one embodiment of this invention, form the method such as Fig. 4 A～represented step of Fig. 4 E of grid 310.Please earlier with reference to Fig. 4 A, form conductive layer 210 and conductive layer 220 in regular turn on substrate 300, the method that forms conductive layer 210,220 for example is sputtering method or vapour deposition method.The material of conductive layer 210 mainly is that contact impedance is low, the tack good metal, and in one embodiment, the material of conductive layer 210 is that to be selected from molybdenum, molybdenum tungsten, tantalum and combination thereof one kind of.In addition, the material of conductive layer 220 mainly is the metal of low resistance, high conductivity, and in one embodiment, the material of conductive layer 220 for example is a copper, and it also can be a silver or golden.
Then, please refer to Fig. 4 B, patterned conductive layer 220.In one embodiment of this invention, the method for patterned conductive layer 220 comprises and carries out photoetching process and wet etch process.At first, on conductive layer 220, utilize photoetching process to make photoresist layer 230, utilize photoresist layer 230 again, conductive layer 220 is carried out Wet-type etching, to obtain conductive layer 220 as the represented patterning of Fig. 4 C as mask.
Continue it, please refer to Fig. 4 C, carry out plasma treatment process 240, make the surface of conductive layer 220 form protective layer 250.In one embodiment of this invention; plasma treatment process 240 employed reacting gass are that to be selected from oxygen, nitrogen, nitrogen dioxide, ammonia and combination thereof one kind of; produce reaction with the surface that produces plasma and conductive layer 220; consequently, the material of formed protective layer 250 for example is cupric oxide or copper nitride.
Afterwards, please refer to Fig. 4 D, remove the conductive layer 210 that protected seam 250 not and conductive layer 220 are covered, to form the grid 310 represented as Fig. 4 E.In one embodiment of this invention, the method that removes the conductive layer 210 that protected seam 250 not and conductive layer 220 covered for example is to carry out dry etch process 260, and these dry etch process 260 employed gases for example are to be selected from sulphur hexafluoride (SF
6), oxygen (O
2), chlorine (Cl
2), hydrogen chloride (HCl), fluoroform (CHF
3) and make up one kind of.
Please continue B, after forming grid 310, then on substrate 300, form gate insulation layer 320 with cover gate 310 with reference to Fig. 3.In one embodiment of this invention, the method for formation gate insulation layer 320 is that (chemical vapor deposition, CVD), and the material of gate insulation layer 320 for example is silicon nitride or silica to chemical vapour deposition technique.
Come again, please refer to Fig. 3 C, forming patterned semiconductor layer 330 on the gate insulation layer 320 with above the grid 310.In one embodiment of this invention, the method that forms patterned semiconductor layer 330 for example is after depositing channel material layer (not shown) and ohmic contact material layer (not shown) in regular turn earlier, in regular turn ohmic contact material layer and channel material layer to be carried out Patternized technique again.Shown in Fig. 3 C, patterned semiconductor layer 330 for example comprises patterning channel layer 332 and patterning ohmic contact layer 334, and patterning ohmic contact layer 334 is positioned on the patterning channel layer 332.
Then, please refer to Fig. 3 D, on patterned semiconductor layer 330, form first conductive layer 340 and second conductive layer 350 in regular turn.In one embodiment of this invention, the method for formation conductive layer 340,350 is sputtering method or vapour deposition method.The material of first conductive layer 340 mainly is that contact impedance is low, the tack good metal, and in one embodiment, the material of first conductive layer 340 is that to be selected from molybdenum, molybdenum tungsten, tantalum and combination thereof one kind of.In addition, the material of second conductive layer 350 mainly is the metal of low resistance, high conductivity, and in one embodiment, the material of second conductive layer 350 for example is a copper, and it also can be a silver or golden.
Then, patterning second conductive layer 350 makes second conductive layer 350 of 310 both sides, grid top have angled section 352 (taper profile) simultaneously, and exposes first conductive layer 340, shown in Fig. 3 G.In one embodiment of this invention, the method for patterning second conductive layer 350 such as Fig. 3 E～represented step of Fig. 3 G.At first, please refer to Fig. 3 E, form patterning photoresist layer 360 on substrate 300, its exposure is positioned at second conductive layer 350 of grid 310 tops.Afterwards, please refer to Fig. 3 F, is mask with patterning photoresist layer 360, carry out wet etch process and be exposed out up to conductive layer 340 with etching second conductive layer 350, and second conductive layer 350 after etched has angled section 352.Afterwards, remove patterning photoresist layer 360, shown in Fig. 3 G.
Continue it, please refer to Fig. 3 H, carry out plasma treatment process 370, make the surface of second conductive layer 350 and angled section 352 places form protective layer 380.In one embodiment of this invention, plasma treatment process 370 employed reacting gass for example are that to be selected from oxygen, nitrogen, nitrogen dioxide, ammonia and combination thereof one kind of, and the material of formed protective layer 380 for example is cupric oxide or copper nitride.In addition, the temperature of plasma treatment process 370 for example is between room temperature (25 ℃)～380 ℃, and the power of plasma treatment process 370 is between 50W～5KW, and along with operation pressure, gas mixture ratio example, gas flow and change.
It should be noted that; the surface of second conductive layer 350 is formed the step of protective layer 380 via plasma treatment process 370; make and in follow-up technology, can directly utilize protective layer 380 as mask; and first conductive layer 340 that is positioned at second conductive layer, 350 belows is carried out dry-etching; thus; the pattern dimension of first conductive layer 340 and second conductive layer 350 will be very approaching, and can solve the too big problem of size difference between the known middle multiple layer metal layer.
Afterwards, please refer to Fig. 3 I, remove first conductive layer 340 that the protected seam 380 not and second conductive layer 350 cover, to form source/drain 390.In one embodiment of this invention, the method that removes first conductive layer 340 that the protected seam 380 not and second conductive layer 350 cover is to carry out dry etch process 400, and these dry etch process 400 employed gases for example are to be selected from sulphur hexafluoride (SF
6), oxygen (O
2), chlorine (Cl
2), hydrogen chloride (HCl), fluoroform (CHF
3) and make up one kind of.It should be noted that; because second conductive layer, 350 protected seams 380 cover; so when carrying out dry etch process 400, the material of second conductive layer 350 (as copper) just can not be released in etching process, therefore can prevent electrically being affected of patterned semiconductor layer 330.
Referring again to Fig. 3 J, in one embodiment of this invention, the manufacture method of above-mentioned thin-film transistor also comprises carries on the back passage etch process 410, with the patterning ohmic contact layer 334 and patterning channel layer 332 partly that removes grid 310 tops, so far, finish the making of thin-film transistor 500.
In sum, the manufacture method of thin-film transistor of the present invention has following advantage:
(1) is that the phenomenon of side direction undercutting (side undercut) will can not take place for the conductive layer of material with copper, and then can produces the meticulous source/drain of size.
(2) the present invention utilizes plasma treatment process, forms protective layer with the surface at the copper conductive layer.This protective layer can make copper can not be released in etching process, thus semiconductor layer electrically will can not be subjected to the influence of copper.
(3) the present invention utilizes the source/drain of the intraconnections fabrication techniques thin-film transistor of copper conductor.Because the conductivity of copper is preferable, thus the problem of known middle resistance capacitance time delay effect can be solved, and then improve the running speed of thin-film transistor.
Though the present invention discloses as above with preferred embodiment; right its is not in order to limit the present invention; any person of ordinary skill in the field; without departing from the spirit and scope of the present invention; when can doing a little change and improvement, so protection scope of the present invention is as the criterion when looking the claim person of defining.
Claims (18)
1. the manufacture method of a thin-film transistor is characterized in that comprising:
On substrate, form grid;
On this substrate, form gate insulation layer to cover this grid;
Forming patterned semiconductor layer on this gate insulation layer and above this grid;
On this patterned semiconductor layer, form first conductive layer and second conductive layer in regular turn;
This second conductive layer of patterning makes this second conductive layer of these both sides, grid top have angled section simultaneously, and exposes this first conductive layer;
Carry out first plasma treatment process, make the surface of this second conductive layer and this angled section place form first protective layer; And
Remove not by this first conductive layer of this first protective layer and the covering of this second conductive layer, to form source/drain.
2. the manufacture method of thin-film transistor according to claim 1 is characterized in that the material of this second conductive layer comprises copper.
3. the manufacture method of thin-film transistor according to claim 1 is characterized in that the material of this first protective layer comprises cupric oxide or copper nitride.
4. the manufacture method of thin-film transistor according to claim 1, the material that it is characterized in that this first conductive layer are that to be selected from molybdenum, molybdenum tungsten, tantalum and combination thereof one kind of.
5. the manufacture method of thin-film transistor according to claim 1 is characterized in that the employed reacting gas of this first plasma treatment process is that to be selected from oxygen, nitrogen, nitrogen dioxide, ammonia and combination thereof one kind of.
6. the manufacture method of thin-film transistor according to claim 1 is characterized in that the method for this second conductive layer of patterning comprises:
Form the patterning photoresist layer on this substrate, its exposure is positioned at this second conductive layer of this grid top; And
With this patterning photoresist layer is mask, carry out wet etch process and be exposed out up to this first conductive layer with this second conductive layer of etching, and this second conductive layer after etched has this angled section.
7. the manufacture method of thin-film transistor according to claim 1, the method that it is characterized in that removing not this first conductive layer that is covered by this first protective layer and this second conductive layer comprises carries out dry etch process.
8. the manufacture method of thin-film transistor according to claim 7 is characterized in that the employed gas of this dry etch process is that to be selected from sulphur hexafluoride, oxygen, chlorine, hydrogen chloride, fluoroform and combination thereof one kind of.
9. the manufacture method of thin-film transistor according to claim 1 it is characterized in that this patterned semiconductor layer comprises patterning channel layer and patterning ohmic contact layer, and this patterning ohmic contact layer is positioned on this patterning channel layer.
10. the manufacture method of thin-film transistor according to claim 9 is characterized in that also comprising and carries on the back the passage etch process, with this patterning ohmic contact layer and this patterning channel layer partly that removes this grid top.
11. the manufacture method of thin-film transistor according to claim 1 is characterized in that the method that forms this grid on this substrate comprises:
On this substrate, form the 3rd conductive layer and the 4th conductive layer in regular turn;
Patterning the 4th conductive layer;
Carry out second plasma treatment process, make the surface of the 4th conductive layer form second protective layer; And
Remove not the 3rd conductive layer that is covered by this second protective layer and the 4th conductive layer, to form this grid.
12. the manufacture method of thin-film transistor according to claim 11 is characterized in that the material of the 4th conductive layer comprises copper.
13. the manufacture method of thin-film transistor according to claim 11 is characterized in that the material of this second protective layer comprises cupric oxide or copper nitride.
14. the manufacture method of thin-film transistor according to claim 11, the material that it is characterized in that the 3rd conductive layer are that to be selected from molybdenum, molybdenum tungsten, tantalum and combination thereof one kind of.
15. the manufacture method of thin-film transistor according to claim 11 is characterized in that the employed reacting gas of this second plasma treatment process is that to be selected from oxygen, nitrogen, nitrogen dioxide, ammonia and combination thereof one kind of.
16. the manufacture method of thin-film transistor according to claim 11, the method that it is characterized in that removing not the 3rd conductive layer that is covered by this second protective layer and the 4th conductive layer comprises carries out dry etch process.
17. the manufacture method of thin-film transistor according to claim 16 is characterized in that the employed gas of this dry etch process is that to be selected from sulphur hexafluoride, oxygen, chlorine, hydrogen chloride, fluoroform and combination thereof one kind of.
18. the manufacture method of thin-film transistor according to claim 11, the method that it is characterized in that patterning the 4th conductive layer comprises carries out photoetching process and wet etch process.
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|---|---|---|---|
| CNB2005101174618A CN100464396C (en) | 2005-10-31 | 2005-10-31 | Method for fabricating thin film transistor |
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|---|---|---|---|
| CNB2005101174618A CN100464396C (en) | 2005-10-31 | 2005-10-31 | Method for fabricating thin film transistor |
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| CN100464396C true CN100464396C (en) | 2009-02-25 |
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| Publication number | Priority date | Publication date | Assignee | Title |
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| WO2010073824A1 (en) * | 2008-12-26 | 2010-07-01 | シャープ株式会社 | Substrate for display panel, and display panel comprising same |
| CN102417156B (en) * | 2011-11-15 | 2015-02-04 | 苏州含光微纳科技有限公司 | Method for etching metal molybdenum material |
| KR101544663B1 (en) * | 2012-01-26 | 2015-08-17 | 가부시키가이샤 제이올레드 | Thin film transistor array apparatus and el display apparatus using same |
| CN110112100A (en) * | 2019-04-24 | 2019-08-09 | 深圳市华星光电技术有限公司 | Preparation method, luminescent panel and the display device of luminescent panel |
| CN111244034A (en) | 2020-01-17 | 2020-06-05 | Tcl华星光电技术有限公司 | Array substrate and manufacturing method thereof |
Citations (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US5198694A (en) * | 1990-10-05 | 1993-03-30 | General Electric Company | Thin film transistor structure with improved source/drain contacts |
| US6376861B1 (en) * | 2000-02-10 | 2002-04-23 | Fujitsu Limited | Thin film transistor and method for fabricating the same |
| US20050024550A1 (en) * | 2003-07-29 | 2005-02-03 | Samsung Electronics Co., Ltd. | Thin film transistor array panel and manufacturing method thereof |
| US20050052602A1 (en) * | 2003-09-08 | 2005-03-10 | Chen-Yu Liu | Liquid crystal display panel |
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2005
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Patent Citations (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US5198694A (en) * | 1990-10-05 | 1993-03-30 | General Electric Company | Thin film transistor structure with improved source/drain contacts |
| US6376861B1 (en) * | 2000-02-10 | 2002-04-23 | Fujitsu Limited | Thin film transistor and method for fabricating the same |
| US20050024550A1 (en) * | 2003-07-29 | 2005-02-03 | Samsung Electronics Co., Ltd. | Thin film transistor array panel and manufacturing method thereof |
| US20050052602A1 (en) * | 2003-09-08 | 2005-03-10 | Chen-Yu Liu | Liquid crystal display panel |
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