CN100464282C - Method and device for controlling electric sequence of distributed system - Google Patents
Method and device for controlling electric sequence of distributed system Download PDFInfo
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- CN100464282C CN100464282C CNB200710063596XA CN200710063596A CN100464282C CN 100464282 C CN100464282 C CN 100464282C CN B200710063596X A CNB200710063596X A CN B200710063596XA CN 200710063596 A CN200710063596 A CN 200710063596A CN 100464282 C CN100464282 C CN 100464282C
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Abstract
This invention relates to one control distribution system electrical orderly method and device, wherein, the method comprises the following steps: logic slice tests system electricity to isolate system and each tank position; the logic chip sends power effective signal to effective tank and the control tank is electrified orderly; the said system then has the logic chip cancelled isolation with system and each tank to send power signal for control. This invention can automatically realize first electricity on each tank.
Description
Technical field
The present invention relates to a kind of powering method and device of distributed system, relate in particular to a kind of method and apparatus that powers in order when distributed system starts of controlling.
Background technology
In the existing distributed system, existence such as fast peripheral equipment connects (PeripheralComponent Interconnect Express, abbreviation PCIE) bus, serial peripheral equipment connect (SerialComponent Interconnect, abbreviation SPI) bus, industrial standard architectures (Industrial StandardArchitecture, be called for short ISA) multiple bus form such as bus, the slot that various buses are corresponding different.For the first time during electrifying startup, mainly there are two kinds of modes that power in system:
Allow the plug-in card on the various bus ducts position to power on simultaneously when one, starting,, send effective power supply signal just for the respective grooves position, each groove position is powered on simultaneously as long as promptly system detects the plug-in card existence;
Two, on systematic master control board, increase configuration EEPROM (Electrically Erasable Programmable Read Only Memo) (the Electrically erasable Programmable read-only Memory that powers on, be called for short EEPROM), write specific content to EEPROM, when system powers on, read the content of EEPROM, close the power supply of all groove positions, behind the master control board starting of system, open the groove position plug-in card on each bus in order, thereby each groove position plug-in card is realized sequence power-on.
In the existing various bus interface standards, stipulated the size of respective bus plug-in card power consumption, if design the power consumption of each plug-in card according to the agreement of standard, then can power on simultaneously to plug-in card, but in some cases, just with the passage of bus as exchanges data, if the power specifications of every plug-in card and standard are inconsistent, at this moment adopt first kind of mode that system is powered on and to bring harm: because the power consumption or the capacitive load on the plug-in card of various bus inserted cards are bigger in the system, simultaneously can there be bigger rush of current during electrifying startup, impulse ratio to system's power supply is bigger, power supply is produced adverse influence, need to improve the impact resistance of power supply, improve the power supply cost.
Though the existing second way has realized various bus ducts position plug-in card is powered in order, but still has defective:
The system start-up time long, after systematic master control board starts again to each bus inserted card sequence power-on, so on the basis of master control board starting, also will add the sequence power-on time of each plug-in card the start-up time of system;
2. configuration EEPROM reliability is not high, and configuration EEPROM generally adopts the twin wire universal serial bus, and (Inter Integrated Circuit is called for short I
2The C bus), if system reset when reading EEPROM, this moment, EEPROM sent " 0 ", and the read cycle does not also finish, and then can not pass through I once more
2C bus access EEPROM is because I
2The C data bus is in low level " 0 ", I thus
2The C bus is hung dead, causes the system failure normally to start;
3. the EEPROM capacity of a general configuration is bigger, and high capacity EEPROM cost is higher, and configuration EEPROM, needs earlier the content of EEPROM to be burnt in the chip, is attached on the master control borad again, and complex process has increased the production complicacy.
Summary of the invention
Defective at prior art, the invention provides a kind of method and apparatus of controlling electric sequence of distributed system, in the time of with the realization systematic master control board electrifying startup first time, the plug-in card of each bus duct position can power in order, shorten the system start-up time, reduce impact system's power supply.
To achieve these goals, the invention provides a kind of method of controlling electric sequence of distributed system, comprising:
When logic chip detects system and powers on, send to all groove position power enable invalid signals, system and each groove position are isolated;
The control chip of each groove position power enable signal of system side is after receiving the system power-on reset signal, and whether detect each groove position effective, and the interface of each effective groove position correspondence sends the power enable useful signal simultaneously on logic chip;
Logic chip sends the power enable useful signal to effective groove position, and the control flume position powers in order.
In the technique scheme, described system finish power on after, logic chip is cancelled the isolation to system and each groove position, by system the power enable signal of each groove position is controlled.
Logic chip sends the power enable useful signal to effective groove position, the process that the control flume position powers in order comprises: logic chip is connected system side sends to each effective groove position after powering on power enable useful signal successively by each groove bit position, realizes the last electric control to effective groove position.
Logic chip sends the power enable useful signal to effective groove position, the control flume position power in order can also for: whether logic chip detects each groove position effective, and directly send the power enable useful signal successively to each effective groove position according to the default delay time lag that powers on, realize last electric control to effective groove position.
To achieve these goals, the present invention also provides a kind of device of controlling electric sequence of distributed system, comprising: the detecting unit that powers on, be connected with logic control element, and when being used to detect system and powering on, power on signal is sent to logic control element; Logic control element is connected with the detecting unit that powers on, and when being used to receive described power on signal, sends to all groove position power enable invalid signals, shielding system and all groove positions; Interface to effective groove position correspondence sends the power enable useful signal simultaneously, sends the power enable useful signal to effective groove position then, and the control flume position powers in order.
Also can comprise in the said apparatus: the master switching unit, be connected with logic control element, be used for after realizing each groove position sequence power-on, finishing the sequence power-on function, the power enable signal of each groove position switches to by system directly to be controlled.
The invention provides a kind of method of controlling electric sequence of distributed system, utilize the electric sequence of external logic chip control bus groove position, the power enable signal that system sends to each groove position is connected by the power enable signal of logic chip with each groove position.When system start-up, when logic chip detects system and powers on, the power enable signal of elder generation's shielding system and all groove positions, make the power enable signal of all groove positions invalid, even system sends the power enable useful signal to effective groove position, but logic chip has been isolated system and all groove positions, send the power enable useful signal to effective groove position in chronological order then, after each groove position is powered in order, cancel isolation again to system and each groove position, by system each groove position is controlled.The device of sequence power-on when the present invention also provides a kind of control system to start, in the time of can realizing starting by this device to the sequence power-on of each bus duct position.Each bus duct position powered in order when the present invention can control distributed system automatically and starts for the first time, had shortened the system start-up time, did not need exterior arrangement EEPROM, cost is low, realizes simply, compared with prior art, the situation that system can't normally start can not occur, reliability also increases.
Below by drawings and Examples, technical scheme of the present invention is described in further detail.
Description of drawings
Fig. 1 controls method embodiment one process flow diagram of electric sequence of distributed system for the present invention;
Fig. 2 is the parsing synoptic diagram of Fig. 1 embodiment;
Fig. 3 sends the power enable useful signal for logic chip of the present invention to effective groove position, control flume position embodiment one process flow diagram that powers in order;
Fig. 4 sends the power enable useful signal for logic chip of the present invention to effective groove position, control flume position embodiment two process flow diagrams that power in order;
The method that Fig. 5 controls electric sequence of distributed system for the present invention is applied to the embodiment process flow diagram of PCIE bus;
Fig. 6 is the parsing synoptic diagram of Fig. 5 embodiment;
Fig. 7 controls device embodiment one structural representation of electric sequence of distributed system for the present invention;
Fig. 8 controls device embodiment two structural representations of electric sequence of distributed system for the present invention;
Fig. 9 controls device embodiment three structural representations of electric sequence of distributed system for the present invention;
The device that Figure 10 controls electric sequence of distributed system for the present invention is applied to the embodiment synoptic diagram of PCIE bus.
Embodiment
Mainly in order to realize systematic master control board for the first time electrifying startup the time, each bus duct potential energy powers in order, shortens the system start-up time, reduces the impact to system's power supply in the present invention.To specifically be elaborated for example to the present invention from Fig. 1 to Figure 10 below, wherein Fig. 1, Fig. 2 are the overview flow chart of the inventive method and resolve synoptic diagram; Fig. 3, Fig. 4 two kinds of different implementation embodiment process flow diagrams in the inventive method the bus duct position being powered in order; Fig. 5, Fig. 6 specifically are applied to the embodiment process flow diagram of PCIE bus for this method; Fig. 7-9 is three specific embodiment structural representations of apparatus of the present invention; Figure 10 is applied to the embodiment synoptic diagram of PCIE bus for apparatus of the present invention.
Fig. 1 controls method embodiment one process flow diagram of electric sequence of distributed system for the present invention.As shown in Figure 1, present embodiment comprises:
When logic chip detects system and powers on, system and each groove position are isolated;
Logic chip sends the power enable useful signal to effective groove position, and the control flume position powers in order.
Fig. 2 is the parsing synoptic diagram of Fig. 1 embodiment, and present embodiment only exemplifies the annexation of 2 slots and logic chip and system, if a plurality of slots are arranged, then annexation and Fig. 2 are similar.As shown in Figure 2, system's power enable (Power enable, be called for short PWREN) signal of sending to each groove position is connected by the power enable signal of logic chip with corresponding groove position plug-in card.
Contrast Fig. 2 describes Fig. 1 below: when logic chip detects system and powers on, the PWREN of shielding system and all groove positions, even system side has sent the power enable useful signal to each groove position, but logic chip can directly not send to the power enable signal that system sends the groove position (if directly send to the groove position then cause each bus slot of system to power on simultaneously, bring bigger rush of current), but isolated the power enable signal that system sends to all groove positions earlier, after each groove position sends the power enable invalid signals earlier, send power enable signal to effective groove position successively in order again, control effective groove position and power in order.
In the present embodiment, distributed system master control borad and logic chip can be worked after powering on simultaneously: after system side detects power on signal, can finish the initialization to master control borad, each bus; Finish during this period of time to starting initialization after distributed system powers on, logic chip can be realized sequence power-on with each bus duct position, thereby has saved the system start-up time.As shown in Figure 2, the PWREN1 of groove position 1 is connected indirectly by the PWREN1 that a logic chip and system side send to groove position 1, even system sends the power enable useful signal of groove position 1 immediately after powering on, logic chip is disconnected the power enable useful signal of system's transmission and the power enable signal of groove position 1, so groove position 1 still can't obtain the power enable useful signal.Logic chip is connected system side more in order successively and is sent to the signal of each groove position or directly exist the groove position of plug-in card to send the PWREN useful signal to each by logic chip after the power enable signal of shielding system and each groove position, realizes powering in order.
Method described in the present embodiment can be applicable to the start-up course of any distributed system or bus, powers in order when realizing electrifying startup.When the distributed system electrifying startup first time, each bus duct position is powered in order, shortened the start-up time of system, and avoided the rush of current that powers on simultaneously and bring, do not need exterior arrangement EEPROM, cost is low, realizes simply, compared with prior art, the situation that system can't normally start can not appear, the reliability height.
When logic chip detects system and powers in the embodiment of the invention, send to all groove position power enable invalid signals.The control chip of each groove position power enable signal of system side is after receiving system's power on signal, and whether detect each groove position effective, and the interface of each effective groove position correspondence sends the power enable useful signal simultaneously on logic chip.
In the embodiment of the invention, after logic chip is isolated system and each groove position, the control flume position powers in order can multiple implementation, as: logic chip is connected the power enable signal that system side sends to each groove position successively by each groove bit position, the power enable useful signal that each interface is received is sent to each effective groove position corresponding with interface, realizes the last electric control to effective groove position.Logic chip is provided with different powering on time delay by each groove bit position, arrives the power enable signal that default connection system during time delay of powering on sends to each groove position.For example, have 4 groove positions 0,1,2,3, be respectively 0,1,2,3 second the time delay that powers on of groove position 0,1,2,3.Logic chip postpones the power enable signal that 0,1,2,3 second connection system sends to 4 groove positions respectively after the system of detecting powers on.After the power enable signal of all groove positions was all connected, the power enable useful signal that system sends to effective groove position can send to each groove position by logic chip, and each plug-in card is realized powering in order.
Fig. 3 and Fig. 4 are other two kinds of implementations of sequence power-on, mainly are to send power enable signal by the validity that detects the groove position to the groove position.
Fig. 3 sends the power enable useful signal for logic chip of the present invention to effective groove position, control flume position embodiment one process flow diagram that powers in order.The present embodiment logic chip detects the validity of each groove position successively, and connects the power enable useful signal that system side sends to effective groove position successively according to the default delay time lag that powers on, and realizes the last electric control to effective groove position.Present embodiment also is the power enable signal that connection system successively sends to each groove position, still need detect the validity of groove position, promptly has plug-in card, and the delay time lag that powers on is set, and makes the equal at interval unanimity of power-on time of every adjacent two groove positions of connection.As shown in Figure 3, comprise in the present embodiment: judge whether current groove position is effective, be to arrive then that the connection system sends to the power enable signal of current groove position when powering on delay time lag, otherwise carry out the judgement of next groove position, be finished until all groove positions.
The delay time lag that powers on that each groove position is set in the present embodiment is same value, such as: it is 1 second that the delay time lag that powers on is set, and has 5 groove positions 0,1,2,3,4, and wherein there is plug-in card in 1,3,4 groove positions, the groove position is effective, and then the course of work of present embodiment is:
1. logic chip judges whether 0 groove position is effective, it is invalid to detect 0 groove position, directly 1 groove position is judged without time-delay, when powering in system owing to logic chip, send to all groove position power enable invalid signals earlier, so this moment, 0 groove position still was the power enable invalid signals;
2. it is effective to detect 1 groove position, and the connection system sends to the power enable useful signal of 1 groove position when postponing 1 second, carries out the judgement of 2 groove positions;
3. it is invalid to detect 2 groove positions, directly 3 groove positions is not judged so do not delay time;
4. it is effective to detect 3 groove positions, and the connection system sends to the power enable useful signal of 3 groove positions when postponing 1 second, and the rest may be inferred.
Whole electric sequence is: postpone 1 second 1 groove position after system powers on and power on, postpone 1 second 3 groove position again and power on, postpone 1 second 4 groove position again and power on, promptly the power-on time of every adjacent two groove positions of Jie Tonging is spaced apart same value.The determining step that increases in the present embodiment can further shorten start-up time, does not delay time for invalid groove position, directly skips, and reaches the purpose of quick sequence power-on.But the implementation of present embodiment needs logic chip further to detect the validity of each groove position, and for example: exist signal PRSNT to be connected with the plug-in card of each groove position, the plug-in card by current groove position exists signal to detect the validity of this groove position.For example: it is that logic low or high level judge whether this groove position exists plug-in card, whether needs this groove position is powered on that there is signal in plug-in card.
Fig. 4 sends the power enable useful signal for logic chip of the present invention to effective groove position, control flume position embodiment two process flow diagrams that power in order.Fig. 4 and Fig. 3 are similar, and identical function repeats no more, and as shown in Figure 4, detect current groove position in the present embodiment when effective, directly send to current groove position power enable useful signal by logic chip during delay interval arriving default powering on.
Fig. 4 embodiment was in isolation with system and each groove position always before effective groove position sequence power-on to each: when powering in system, system and each groove position are isolated; During sequence power-on, detect the effective of groove position by logic chip, and directly send the power enable useful signal successively to each effective groove position according to the default delay time lag that powers on, realization is to the last electric control of effective groove position, system and each groove position also are in isolation, after sequence power-on finishes, cancel isolation to system and each groove position, by system the power enable signal of each groove position is controlled.
Fig. 3 is different with the implementation of Fig. 4 embodiment, but execution result is consistent: will exist effective groove position of plug-in card to power in order, and the power-on time of every adjacent two effective groove positions is all consistent at interval.
Logic chip is by Fig. 3 and embodiment illustrated in fig. 4 or to connect the power enable signal that system side sends to each groove position successively by each groove bit position be that logic chip sends the power enable useful signal to effective groove position, the control flume position power in order 3 in different implementations, as: same distributed system, have 4 groove positions 0,1,2,3, have only on 0,3 the groove position to have plug-in card.Contrast several implementations below:
1. connect the power enable signal that system side sends to each groove position successively by each groove bit position, execution result is: powering in order needs 3 seconds, system side sends the power enable useful signal simultaneously to effective groove position when powering on, when logic chip powers in the system of detecting, send to all groove position power enable invalid signals simultaneously, and the demand working system side is issued the power enable signal of groove position 0; Back connection in the 1st second system side that powers on is issued the power enable signal of groove position 1; Back connection in the 2nd second system side that powers on is issued the power enable signal of groove position 2; Back connection in the 3rd second system side that powers on is issued the power enable signal of groove position 3;
2. detect the validity of each groove position and connect the power enable useful signal that system side sends to effective groove position by the delay time lag that powers on, execution result is: powering in order needs 1 second, connects the power enable signal that system side sends to groove position 0 when powering on; Back connection in the 1st second system side that powers on sends to the power enable signal of groove position 3;
3. detect the validity of each groove position and directly send to effective groove position power enable useful signal by logic chip by the delay time lag that powers on, execution result is: powering in order needs 1 second, and logic chip directly sends to groove position 0 power enable useful signal when powering on; The 1st second logic chip in back that power on directly sends to groove position 3 power enable useful signals.
Can find out that by top contrast utilize the validity sequence power-on, start-up time is shorter, exist in distributed system under the situation of a plurality of grooves position that this optimization meeting is more obvious, reach the purpose of quick sequence power-on.
Logic chip control flume position powers in order in the embodiment of the invention, after effective groove position sends the power enable useful signal, also comprise: system finish power on after, logic chip is cancelled the isolation to system and each groove position, by system the power enable signal of each groove position is controlled.Logic chip is finished the sequence power-on function when the system's electrifying startup first time, after the sequence power-on function is finished, can finish the sequence power-on function of logic chip, switches to by system and directly each groove position is controlled.
The method that Fig. 5 controls electric sequence of distributed system for the present invention is applied to the embodiment process flow diagram of PCIE bus.Fig. 6 is the parsing synoptic diagram of Fig. 5 embodiment.The PCIE bus is provided with a PCIE exchange chip in the existing distributed system, groove position to each PCIE plug-in card in this exchange chip is provided with a PCIE hot-swapping controller, the functions such as power supply power-on and power-off control when the PCIE plug-in card that is used for controlling each groove position inserts or extracts.For opening, there is the related register default setting of each PCIE hot-swapping controller in the PCIE exchange chip behind the electrification reset as long as detect PCIE groove position plug-in card, powers on just for during system start-up the PCIE plug-in card.Because in the PCIE standard, the plug-in card of a groove position of regulation exists signal PRSNT, manual locking sensor input (Manually operated Retention Latch SensorInput, be called for short MRL) when being logic low simultaneously, this groove position is effective, the PCIE exchange chip could send the PWREN useful signal to this groove position, and only utilized the PRSNT of each groove position in the native system, so the value of each groove position MRL and PRSNT can be set by logic chip.As shown in Figure 6, logic chip exists signal PRSNT to link to each other with the plug-in card of each groove position in the present embodiment, the MRL signal is set and imports in the PCIE exchange chip according to PRSNT.Logic chip can directly be provided with the value of MRL according to the state of PRSNT, as: PRSNT==0, then MRL==0; PRSNT==1, then MRL==1 also can directly be connected with the PRSNT of PCIE exchange chip corresponding groove position the PRSNT of each groove position with MRL, thereby trigger the PCIE exchange chip each groove position validity is detected.
Below by Fig. 6 embodiment this method embodiment is applied to the PCIE bus and realizes that sequence power-on describes: among Fig. 5 embodiment, when logic chip detects system and powers on, cut off the PCIE exchange chip and give the PWREN signal of all groove positions, send the PWREN invalid signals before connection, for all groove positions; Logic chip is still disconnected the PWREN of PCIE exchange chip and each groove position then, but in order effective groove position is powered on.The specific implementation that powers in order such as Fig. 1-Fig. 4 do not repeat them here the explanation of sequence power-on.After each groove position sequence power-on finishes, close the sequence power-on function of logic chip, the PWREN signal of each groove position switches to by the PCIE bus architecture directly to be controlled.
Fig. 5 and Fig. 6 just are applied to the PCIE bus to this method and give an example, as long as relate to system's process of electrifying startup for the first time in the distributed system, all can utilize the described method of the embodiment of the invention, system's power up is optimized, startup powers on simultaneously in order.Various buses and corresponding groove position also can utilize the described method of the embodiment of the invention that the groove position is powered in order, shorten start-up time, reduce the rush of current that powers on simultaneously and bring.
Fig. 7 controls device embodiment one synoptic diagram of electric sequence of distributed system for the present invention.As shown in Figure 7, the present embodiment device comprises: the detecting unit 1 that powers on, be connected with logic control element 2, and when being used to detect system and powering on, power on signal is sent to logic control element 2; Logic control element 2 is connected with the detecting unit 1 that powers on, when being used to receive power on signal, and shielding system and all groove positions; Send effective power supply signal to effective groove position, the control flume position powers in order.
Fig. 8 controls device embodiment two synoptic diagram of electric sequence of distributed system for the present invention.Present embodiment is to the further refinement of logic control element.As shown in Figure 8, present embodiment logic control element 2 comprises that 3 are connected control sub unit and 2 time-delay control sub unit:
The detecting unit 1 that powers on is connected control sub unit 20 ', 21 ', 22 ' and is connected with 3, when being used to detect system and powering on, power on signal is sent to 3 connection control sub unit 20 ', 21 ', 22 ';
Connect control sub unit 20 ', send to the power enable signal (PWREN0) of groove position 0 with the detecting unit 1 that powers on, system side and the power enable signal of groove position 0 is connected, connect control sub unit 20 ' in 0 groove position, do not need time-delay, so the time-delay control sub unit is not set;
Connect control sub unit 21 ', with the detecting unit 1 that powers on, time-delay control sub unit 31 ', system side sends to the power enable signal (PWREN1) of groove position 1 and the power enable signal of groove position 1 is connected;
Connect control sub unit 22 ', with the detecting unit 1 that powers on, time-delay control sub unit 32 ', system side sends to the power enable signal (PWREN2) of groove position 2 and the power enable signal of groove position 2 is connected.
After described connection control sub unit was used to receive power on signal, the shielding system side sent to the power enable useful signal of each effective groove position simultaneously after powering on, and transmitted control signal to the time-delay control sub unit; After receiving arriving signal time delay that powers on of time-delay control sub unit, the power enable useful signal that successively system side is sent to effective groove position is connected with corresponding effectively groove position;
Time-delay control sub unit 31 ', 32 ' with corresponding connection control sub unit 21 ', 22 ' connection, is used for the control signal of receive logic control module and sends arriving signal time delay that powers on when arrival powers on time delay respectively.
The transmission control sub unit of each groove position does not connect mutually among Fig. 8 embodiment, power on when arrive in time delay, in order each groove position according to each groove bit position, for example: groove position 0, after system powers on, without postponing and can the connection system giving the PWREN0 signal of 0 groove position; Groove position 1, the connection system gives the PWREN1 signal of 1 groove position after the time interval of 1 setting of back delay that powers on, and sends in the connection system before the PWREN1 signal of 1 groove position, and 1 groove position is the power enable invalid signals; Groove position 2, the connection system sends to the PWREN2 signal of 2 groove positions after the time interval of 2 settings of back delay that powers on, and sends in the connection system before the PWREN2 signal of 2 groove positions, and 2 groove positions are the power enable invalid signals, the rest may be inferred, powers in order until all groove position plug-in cards.After sequence power-on finished, system sent to the power supply signal and the corresponding groove position of each groove position and connects, by the direct control of system's realization to each groove position.This device makes the sequence power-on of groove position in the time of can realizing for the first time electrifying startup, has shortened the system start-up time, does not need exterior arrangement EEPROM, and cost is low, realizes simply, compared with prior art, the situation that system can't normally start can not occur, the reliability height.
Fig. 9 controls device embodiment three synoptic diagram of electric sequence of distributed system for the present invention.Present embodiment is to the further refinement of logic control element, and logic control element 2 comprises in the present embodiment:
3 detection sub-unit 50,51,52 link to each other with each groove position respectively, are used to detect the validity of each groove position, and testing result is sent to corresponding transmission control sub unit;
3 send control sub unit 20,21,22, are connected with last electro-detection single 1 yuan and corresponding detection sub-unit, time-delay control sub unit, and after being used to receive power on signal, with system and the isolation of corresponding groove position, control sub unit transmits control signal to delaying time; After receiving arriving signal time delay that powers on of time-delay control sub unit, directly send the power enable useful signal successively to effective groove position;
2 time-delay control sub unit 31,32, each time-delay control sub unit is connected with the transmission control sub unit respectively, is used to receive control signal and sends arriving signal time delay that powers on when arrival powers on time delay.
Also comprise master switching unit 4 in the present embodiment, send control sub unit 20,21,22 with in the logic control element 2 each and is connected, be used for after realizing each groove position sequence power-on end sequence power-on function; Switch to by system and directly the PWREN signal of each groove position is controlled.Further comprise the detection sub-unit that each groove position validity is detected in the present embodiment.The embodiment of Fig. 9, the concrete course of work and Fig. 8 are different, when powering on for the first time in the system that detects among Fig. 8 embodiment, elder generation's shielding system sends to the PWREN signal of each groove position, set different powering on time delay according to each groove bit position then, the connection system sends to the PWREN signal of each groove position when arrive in time delay, finishes in order powering on.In the present embodiment, send the power enable useful signal by the validity that detects the groove position.
When Fig. 9 embodiment powered in the system of detecting, the cut-out system sent to the PWREN signal of each groove position, during the no show of setting time delay that powers on, sent the PWREN invalid signals for each groove position, was in charge of the PWREN of each groove position.Present embodiment powers on to effective groove position in order can two kinds of working methods:
1. system powers on, and the detecting unit 1 that powers on sends power on signal to sending control sub unit 20,21,22, sends control sub unit and cuts off PWREN0, PWREN1, the PWREN2 that system is connected with each groove position.Detection sub-unit 50 detects the validity of groove position 0, the result is sent to send control sub unit 20.When 0 groove position power enable useful signal is directly given by sending control sub unit 20 effectively the time in groove position 0; After sending control sub unit 21 system being isolated with groove position 1, detection sub-unit 51 detects the validity of groove positions 1, and the result is sent to transmission control sub unit 21.After postponing the time interval of 1 setting effectively the time, groove position 1 directly sends to 1 groove position power enable useful signal by sending control sub unit 21; After sending control sub unit 22 system being isolated with groove position 2, detection sub-unit 52 detects the validity of groove positions 2, and the result is sent to transmission control sub unit 22.After postponing the time interval of 2 settings effectively the time, groove position 2 directly sends to 2 groove position power enable useful signals by sending control sub unit 22, if certain groove position is invalid, then give this groove position power enable invalid signals, the rest may be inferred, until powering on for all effective groove position plug-in cards in order.Master switching unit 4 switches after all groove position sequence power-ons finish, and cancels the isolation to system and each groove position, by system the power enable signal of each groove position is controlled.
2. system powers on, and the detecting unit 1 that powers on sends power on signal to logic control element 2, sends control sub unit 20,21,22 and respectively system and corresponding groove position is isolated.Detection sub-unit 50 detects the validity of groove position 0, the result is sent to send control sub unit 20.When groove position 0 effectively the time by sending the power enable useful signal that control sub unit 20 connection systems send to 0 groove position; After sending control sub unit 21 system being isolated with groove position 1, detection sub-unit 51 detects the validity of groove positions 1, and the result is sent to transmission control sub unit 21.After groove position 1 postpones the time interval of 1 setting effectively the time by sending the power enable useful signal that control sub unit 21 connection systems send to 1 groove position; After sending control sub unit 22 system being isolated with groove position 2, detection sub-unit 52 detects the validity of groove positions 2, and the result is sent to transmission control sub unit 22.After postponing the time interval of 2 settings effectively the time, groove position 2 sends to 2 groove position power enable useful signals by sending control sub unit 22 connection systems, if certain groove position is invalid, then give this groove position power enable invalid signals, the rest may be inferred, until powering on for all effective groove position plug-in cards in order.Master switching unit 4 switches after all groove position sequence power-ons finish, and cancels the isolation to system and each groove position, by system the power enable signal of each groove position is controlled.
The device that Figure 10 controls electric sequence of distributed system for the present invention is applied to the embodiment synoptic diagram of PCIE bus.It is among Fig. 5 and Fig. 6 method to be applied to specializing of PCIE bus that embodiment of the invention device is applied to the PCIE bus, and the identical function module repeats no more.As shown in figure 10, each groove position plug-in card can be existed signal (PRSNT) signal directly to link to each other with the MRL signal in the present embodiment device, be convenient to the validity that the PCIE exchange chip detects each groove position with the PRSNT of PCIE exchange chip corresponding groove position by detection sub-unit.Detection sub-unit can not link to each other with system side PCIE exchange chip yet in the present embodiment, exists signal (PRSNT) directly to link to each other with the PCIE exchange chip each groove position plug-in card, as shown in Figure 6, makes things convenient for system side PCIE exchange chip to detect the validity of each groove position.
Can skip this groove position in the groove position when invalid in the present embodiment does not power on to it.For instance, there is plug-in card in groove position 0, be effective groove position, it is effective that transmission control sub unit 20 detects 0 groove position by detection sub-unit 50, then sending the power enable useful signal to groove position 0 (can send by sending control sub unit 20, thereby also can send useful signal, see Fig. 9 declaratives for details) by connecting the PWREN0 that the PCIE exchange chip sends to groove position 0.To groove position 0 power on finish after, trigger groove position 1, if groove position 1 does not have plug-in card, then send control sub unit 21 and trigger groove positions 2; Transmission control sub unit 22 detects groove position 2 by detection sub-unit 52 and has plug-in card, be that groove position 2 is effective, transmit control signal to time-delay control sub unit 32, time-delay control sub unit 32 picks up counting, when arrive in time delay, to sending 22 transmission lag time of control sub unit arriving signal, and then send the PWREN2 useful signal, start next groove position, and the like, be finished until all groove positions.
Among Figure 10 embodiment owing to skipped invalid card slot position, it is not delayed time, can further shorten the sequence power-on time, be per two power-on time intervals of connecting the groove position time delay that time-delay control sub unit 31,32 is provided with, and the value of setting of each time-delay control sub unit is the same.As: the delay time lag of setting is 1 second, if there is plug-in card in 0,2,3 groove positions, then powering between the groove position 0 and 2,2 and 3 is 1 second at interval.Fig. 8 is different with the getting type of Figure 10 with Fig. 9, the transmission control sub unit of each groove position is not connected to each other among Fig. 8 and Fig. 9, just by the time-delay control sub unit each groove position is operated, the value of setting of each time-delay control sub unit is different, according to the groove bit position length of delay is set.As: the time-delay control sub unit of groove position 1 is 1 second, the counting unit of groove position 2 is 2 seconds, if 0, there is plug-in card in 2 groove positions, there is not plug-in card in groove position 1, then groove position 0 and 2 powers on and is spaced apart 2 seconds, the embodiment of sequence power-on time ratio Figure 10 is long, specifies to see for details among the method embodiment for the comparative descriptions of several implementations of sequence power-on, repeats no more.
The embodiment of the invention is at the above-mentioned deficiency of prior art, a kind of implementation method and device of sequence power-on when controlling distributed system and starting are provided, the process that starts is transformed, utilize external logic chip to control the electric sequence of each groove position, power in order finish after, switch to again by system the power enable signal of each groove position controlled.The present invention has shortened the system start-up time, does not need exterior arrangement EEPROM, and cost is low, and realization is simple and reliability is high.Because each plug-in card powers in order, has reduced the impact to system's power supply.
It should be noted last that, above embodiment is only unrestricted in order to technical scheme of the present invention to be described, although the present invention is had been described in detail with reference to preferred embodiment, those of ordinary skill in the art is to be understood that, can make amendment or be equal to replacement technical scheme of the present invention, and not break away from the spirit and scope of technical solution of the present invention.
Claims (8)
1. a method of controlling electric sequence of distributed system is characterized in that, comprising:
When logic chip detects system and powers on, send to all groove position power enable invalid signals, system and each groove position are isolated;
The control chip of each groove position power enable signal of system side is after receiving the system power-on reset signal, and whether detect each groove position effective, and the interface of each effective groove position correspondence sends the power enable useful signal simultaneously on logic chip;
Logic chip sends the power enable useful signal to effective groove position, and the control flume position powers in order.
2. according to the method for the described control electric sequence of distributed system of claim 1, it is characterized in that, described system finish power on after, logic chip is cancelled the isolation to system and each groove position, by system the power enable signal of each groove position is controlled.
3. according to the method for the described control electric sequence of distributed system of claim 1, it is characterized in that logic chip sends the power enable useful signal to effective groove position, the process that the control flume position powers in order comprises:
Logic chip is connected the power enable signal that system side sends to each groove position successively by each groove bit position, the power enable useful signal that described each interface is received is sent to each effective groove position corresponding with interface, realizes the last electric control to effective groove position.
4. according to the method for the described control electric sequence of distributed system of claim 1, it is characterized in that logic chip sends the power enable useful signal to effective groove position, the process that the control flume position powers in order comprises:
Logic chip detects the validity of each groove position successively, and connects the power enable useful signal that system side sends to effective groove position successively according to the default delay time lag that powers on, and realizes the last electric control to effective groove position.
5. according to the method for the arbitrary described control electric sequence of distributed system of claim 1-3, it is characterized in that logic chip sends the power enable useful signal to effective groove position, the process that the control flume position powers in order comprises:
Whether logic chip detects each groove position effective, and directly send the power enable useful signal successively to each effective groove position according to the default delay time lag that powers on, and realizes the last electric control to effective groove position.
6. a device of controlling electric sequence of distributed system is characterized in that, comprising:
The detecting unit that powers on is connected with logic control element, when being used to detect system and powering on, power on signal is sent to logic control element;
Logic control element is connected with the detecting unit that powers on, and when being used to receive described power on signal, sends to all groove position power enable invalid signals, shielding system and all groove positions; Interface to effective groove position correspondence sends the power enable useful signal simultaneously, sends the power enable useful signal to effective groove position then, and the control flume position powers in order.
7. according to the device of the described control electric sequence of distributed system of claim 6, it is characterized in that, also comprise:
The master switching unit is connected with logic control element, is used for finishing the sequence power-on function after realizing each groove position sequence power-on, and the power enable signal of each groove position switches to by system directly to be controlled.
8. according to the device of claim 6 or 7 described control electric sequence of distributed system, it is characterized in that described logic control element comprises:
One or more connection control sub unit, each is connected control sub unit and is connected with the detecting unit that powers on, time-delay control sub unit respectively, after being used to receive power on signal, the shielding system side sends to the power enable useful signal of each effective groove position simultaneously after powering on, transmit control signal to the time-delay control sub unit; After receiving arriving signal time delay that powers on of time-delay control sub unit, the power enable useful signal that successively system side is sent to effective groove position is connected with corresponding effectively groove position;
One or more time-delay control sub unit, each time-delay control sub unit is connected with the connection control sub unit respectively, is used to receive control signal and sends arriving signal time delay that powers on when arrival powers on time delay.
9. according to the device of claim 6 or 7 described control electric sequence of distributed system, it is characterized in that described logic control element comprises:
One or more detection sub-unit link to each other with each groove position respectively, are used to detect the validity of each groove position, and testing result is sent to corresponding transmission control sub unit;
One or more transmission control sub unit are connected with corresponding detection sub-unit, the control sub unit of delaying time with the detecting unit that powers on, and after being used to receive power on signal, system and corresponding groove position are isolated, and transmit control signal to the time-delay control sub unit; After receiving arriving signal time delay that powers on of time-delay control sub unit, directly send the power enable useful signal successively to effective groove position;
One or more time-delay control sub unit, each time-delay control sub unit is connected with the transmission control sub unit respectively, is used to receive control signal and sends arriving signal time delay that powers on when arrival powers on time delay.
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| CNB200710063596XA CN100464282C (en) | 2007-02-06 | 2007-02-06 | Method and device for controlling electric sequence of distributed system |
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| CN111736678B (en) * | 2020-06-12 | 2022-06-10 | 浪潮(北京)电子信息产业有限公司 | Chip reset circuit, method and equipment |
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