CN100463145C - Non-volatile memory and production method - Google Patents
Non-volatile memory and production method Download PDFInfo
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- CN100463145C CN100463145C CNB2005101297463A CN200510129746A CN100463145C CN 100463145 C CN100463145 C CN 100463145C CN B2005101297463 A CNB2005101297463 A CN B2005101297463A CN 200510129746 A CN200510129746 A CN 200510129746A CN 100463145 C CN100463145 C CN 100463145C
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- 238000004519 manufacturing process Methods 0.000 title claims description 35
- 230000015654 memory Effects 0.000 title description 20
- 238000003860 storage Methods 0.000 claims abstract description 88
- 238000000034 method Methods 0.000 claims abstract description 76
- 239000000758 substrate Substances 0.000 claims abstract description 72
- 239000010410 layer Substances 0.000 claims description 178
- 239000000463 material Substances 0.000 claims description 48
- 230000015572 biosynthetic process Effects 0.000 claims description 25
- VYPSYNLAJGMNEJ-UHFFFAOYSA-N Silicium dioxide Chemical compound O=[Si]=O VYPSYNLAJGMNEJ-UHFFFAOYSA-N 0.000 claims description 24
- 239000011241 protective layer Substances 0.000 claims description 23
- 239000004020 conductor Substances 0.000 claims description 22
- 230000005641 tunneling Effects 0.000 claims description 16
- 229910021420 polycrystalline silicon Inorganic materials 0.000 claims description 14
- 229910052581 Si3N4 Inorganic materials 0.000 claims description 13
- HQVNEWCFYHHQES-UHFFFAOYSA-N silicon nitride Chemical compound N12[Si]34N5[Si]62N3[Si]51N64 HQVNEWCFYHHQES-UHFFFAOYSA-N 0.000 claims description 13
- 239000000377 silicon dioxide Substances 0.000 claims description 12
- 238000005229 chemical vapour deposition Methods 0.000 claims description 11
- 239000011232 storage material Substances 0.000 claims description 10
- 230000003647 oxidation Effects 0.000 claims description 7
- 238000007254 oxidation reaction Methods 0.000 claims description 7
- 238000000926 separation method Methods 0.000 claims description 3
- 239000003989 dielectric material Substances 0.000 description 10
- 238000002955 isolation Methods 0.000 description 10
- 238000007667 floating Methods 0.000 description 8
- 229910045601 alloy Inorganic materials 0.000 description 7
- 239000000956 alloy Substances 0.000 description 7
- 229910052751 metal Inorganic materials 0.000 description 6
- 239000002184 metal Substances 0.000 description 6
- 230000000694 effects Effects 0.000 description 4
- 238000001312 dry etching Methods 0.000 description 3
- 238000005530 etching Methods 0.000 description 3
- 229910021332 silicide Inorganic materials 0.000 description 3
- FVBUAEGBCNSCDD-UHFFFAOYSA-N silicide(4-) Chemical compound [Si-4] FVBUAEGBCNSCDD-UHFFFAOYSA-N 0.000 description 3
- 238000000151 deposition Methods 0.000 description 2
- 230000008021 deposition Effects 0.000 description 2
- 238000009792 diffusion process Methods 0.000 description 2
- 238000005516 engineering process Methods 0.000 description 2
- 229910000449 hafnium oxide Inorganic materials 0.000 description 2
- WIHZLLGSGQNAGK-UHFFFAOYSA-N hafnium(4+);oxygen(2-) Chemical compound [O-2].[O-2].[Hf+4] WIHZLLGSGQNAGK-UHFFFAOYSA-N 0.000 description 2
- 238000002347 injection Methods 0.000 description 2
- 239000007924 injection Substances 0.000 description 2
- 238000005468 ion implantation Methods 0.000 description 2
- 238000003701 mechanical milling Methods 0.000 description 2
- BPUBBGLMJRNUCC-UHFFFAOYSA-N oxygen(2-);tantalum(5+) Chemical compound [O-2].[O-2].[O-2].[O-2].[O-2].[Ta+5].[Ta+5] BPUBBGLMJRNUCC-UHFFFAOYSA-N 0.000 description 2
- 239000000126 substance Substances 0.000 description 2
- 229910052801 chlorine Inorganic materials 0.000 description 1
- 125000001309 chloro group Chemical group Cl* 0.000 description 1
- 238000010276 construction Methods 0.000 description 1
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- 238000000059 patterning Methods 0.000 description 1
- 238000001259 photo etching Methods 0.000 description 1
- 239000004065 semiconductor Substances 0.000 description 1
- 229910052712 strontium Inorganic materials 0.000 description 1
- CIOAGBVUUVVLOB-UHFFFAOYSA-N strontium atom Chemical compound [Sr] CIOAGBVUUVVLOB-UHFFFAOYSA-N 0.000 description 1
- VEALVRVVWBQVSL-UHFFFAOYSA-N strontium titanate Chemical compound [Sr+2].[O-][Ti]([O-])=O VEALVRVVWBQVSL-UHFFFAOYSA-N 0.000 description 1
- 229910001936 tantalum oxide Inorganic materials 0.000 description 1
- PBCFLUZVCVVTBY-UHFFFAOYSA-N tantalum pentoxide Inorganic materials O=[Ta](=O)O[Ta](=O)=O PBCFLUZVCVVTBY-UHFFFAOYSA-N 0.000 description 1
- 210000001364 upper extremity Anatomy 0.000 description 1
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Abstract
The method includes steps: forming first doping area on the substrate provided, and there is a distance between the first doping area and surface of the substrate; next, forming groove on the substrate, and exposing the first doping are at bottom of groove; then, forming charge storage layer on two sidewalls of the groove, and top of the charge storage layer being lower than the surface of the substrate; forming grid on the groove; forming second doping area on top of the substrate on two sides of the groove.
Description
Technical field
The present invention relates to a kind of semiconductor element and manufacture method thereof, particularly relate to a kind of manufacture method of non-volatility memorizer.
Background technology
Flash memory in the non-volatility memorizer (Flash) relies on the advantage on its quick timesaving operator scheme and the cost, has become one of main flow of industry research.Typical flash element is made of floating grid (Floating Gate) and control grid (Control Gate), the control grid is set directly on the floating grid, be separated by with dielectric layer between floating grid and the control grid, and be separated by with tunnel oxide (Tunnel Oxide) between floating grid and substrate.
Because above-mentioned flash memory tends to occur the problem of over-erasure, therefore many flash memories can adopt the design of separated grid (Split Gate), with the above-mentioned control grid that is positioned on the floating grid, extend on the sidewall and substrate of floating grid.The mode of operation of this kind separate grid type flash memory utilizes source side to inject (Source-Side Injection) effect, electronics is injected floating grid with this memory of programming, and utilize the F-N tunneling effect to carry out erase operation.
Yet, along with development of integrated circuits, for element integrated level (Integrity) require highly, and the shared area of this kind memory is excessive, has not only hindered the integrated of element, also can influence whole circuit layout.
Summary of the invention
In view of this, an object of the present invention is to provide a kind of non-volatility memorizer, its shared area is little, can improve the integrated level of element, and increases the space of circuit layout.
Another object of the present invention provides a kind of manufacture method of non-volatility memorizer, can produce the littler memory cell of size with simple method.
The present invention proposes a kind of manufacture method of non-volatility memorizer, and substrate at first is provided, and forms first doped region afterwards in substrate, and first doped region and substrate surface are at a distance of a distance.Then, form at least one groove in substrate, channel bottom exposes first doped region.Form electric charge storage layer then in the groove both sides, the top of electric charge storage layer is lower than substrate surface.Then in groove, form one deck grid.Afterwards, form second doped region in groove substrate on two sides top.
According to the manufacture method of the described non-volatility memorizer of embodiments of the invention, the method for above-mentioned formation electric charge storage layer for example is prior to forming the charge storage material layer in the substrate, inserting in the groove.Remove the Partial charge storage material layer in suprabasil charge storage material layer and the groove afterwards.
Manufacture method according to the described non-volatility memorizer of embodiments of the invention, the above-mentioned step that removes the Partial charge storage material layer in the groove, also comprise the Partial charge storage material layer that removes channel bottom, form the two Charge Storage blocks that are positioned at the separation of groove two lateral walls.
According to the manufacture method of the described non-volatility memorizer of embodiments of the invention, on be set forth between the grid that form electric charge storage layer and control gate interpolar before the dielectric layer, can also form dielectric layer between this two Charge Storage block.
According to the manufacture method of the described non-volatility memorizer of embodiments of the invention, on be set forth in after the step that forms groove with the step that forms electric charge storage layer before, can also in groove, form one deck tunneling dielectric layer.
According to the manufacture method of the described non-volatility memorizer of embodiments of the invention, the formation method of above-mentioned tunneling dielectric layer comprises thermal oxidation method.
Manufacture method according to the described non-volatility memorizer of embodiments of the invention, on be set forth in after the step that forms electric charge storage layer with the step that forms the control grid before, can also form dielectric layer between one deck grid in groove, dielectric layer covers electric charge storage layer at least between these grid.
According to the manufacture method of the described non-volatility memorizer of embodiments of the invention, on be set forth in after the step that forms grid with the step that forms second doped region before, can also on grid, form layer protective layer.
According to the manufacture method of the described non-volatility memorizer of embodiments of the invention, the material of above-mentioned protective layer for example is silicon nitride or silica.The formation method of above-mentioned protective layer for example is chemical vapour deposition technique or thermal oxidation method.
According to the manufacture method of the described non-volatility memorizer of embodiments of the invention, the material of above-mentioned electric charge storage layer for example is a doped polycrystalline silicon.Above-mentioned electric charge storage layer can be an electric charge capture layer, and its material for example is a silicon nitride.The material of above-mentioned grid for example is a doped polycrystalline silicon.
According to the manufacture method of the described non-volatility memorizer of embodiments of the invention, the formation method of above-mentioned grid for example is prior to forming one deck conductor layer in the substrate, filling up groove and cover substrate.Then remove the segment conductor layer.
The present invention proposes a kind of non-volatility memorizer, is made of substrate, electric charge storage layer, grid, first doped region and second doped region.Has at least one groove in the substrate.Electric charge storage layer is arranged at the groove both sides, and the top of electric charge storage layer is lower than substrate surface.Grid is arranged in the groove.First doped region is arranged in the substrate of channel bottom, and second doped region then is arranged in the substrate on two sides of groove top.
According to the described non-volatility memorizer of embodiments of the invention, above-mentioned electric charge storage layer is the U type.
According to the described non-volatility memorizer of embodiments of the invention, above-mentioned electric charge storage layer is divided into two Charge Storage blocks, and two Charge Storage blocks are separated from one another, is arranged in the relative two side of groove.
According to the described non-volatility memorizer of embodiments of the invention, can also be to be provided with one deck tunneling dielectric layer between above-mentioned electric charge storage layer and the groove.
According to the described non-volatility memorizer of embodiments of the invention, can also be to be provided with dielectric layer between one deck grid between above-mentioned grid and the electric charge storage layer.
According to the described non-volatility memorizer of embodiments of the invention, also comprise one dielectric layer in above-mentioned two electric charge storage layers, the surface of this dielectric layer is lower than the top of electric charge storage layer.
According to the described non-volatility memorizer of embodiments of the invention, also comprise layer protective layer in the above-mentioned groove, be arranged on the grid.
According to the described non-volatility memorizer of embodiments of the invention, the material of above-mentioned protective layer for example is silica or silicon nitride.
According to the described non-volatility memorizer of embodiments of the invention, the material of above-mentioned electric charge storage layer for example is a doped polycrystalline silicon.Above-mentioned electric charge storage layer can be one deck electric charge capture layer, and its material for example is a silicon nitride.The material of above-mentioned grid for example is a doped polycrystalline silicon.
According to the described non-volatility memorizer of embodiments of the invention, above-mentioned grid more can extend between two electric charge storage layers.
The present invention is because of adopting the structure of plough groove type memory, electric charge storage layer and grid erectly is arranged among the groove, so can significantly reduces the shared area of each memory cell, not only improves the integrated level of element, more can increase the space of circuit layout.
For above and other objects of the present invention, feature and advantage can be become apparent, following conjunction with figs. and preferred embodiment are to illustrate in greater detail the present invention.
Description of drawings
Figure 1A to Fig. 1 E illustrates the manufacturing process profile of a kind of non-volatility memorizer of one embodiment of the invention.
Fig. 2 illustrates the top view of Fig. 1 E.
Fig. 3 illustrates the section of structure of a kind of non-volatility memorizer of one embodiment of the invention.
The simple symbol explanation
100,200: substrate
105,155,205,255: doped region
107,207: groove
110,210: tunneling dielectric layer
120,220: electric charge storage layer
130,230: dielectric layer
135,235: dielectric layer between grid
140,240: grid
150,250: protective layer
Embodiment
Figure 1A to Fig. 1 E illustrates the manufacturing process profile of a kind of non-volatility memorizer of one embodiment of the invention.Fig. 2 illustrates the structure top view of a kind of non-volatility memorizer after manufacturing is finished of one embodiment of the invention.Wherein, Figure 1A to Fig. 1 E for example is along the manufacturing process profile of I-I ' line among Fig. 2.
Please refer to Figure 1A, substrate 100 at first is provided, substrate 100 has been formed with isolation structure (be not illustrated among Figure 1A to Fig. 1 E, can with reference to the isolation structure 102 of Fig. 2).Isolation structure for example is fleet plough groove isolation structure or field oxide, and its formation method should be known in those skilled in the art, repeats no more in this.In substrate 100, form doped region 105 afterwards.The surface on doped region 105 and substrate 100 surfaces is at a distance of a distance.The formation method of doped region 105 for example be carry out that alloy injects or the alloy diffusion to form it.Then, form at least one groove 107 in substrate 100, the bottom of groove 107 at least for example is to expose doped region 105, that is to say, the substrate 100 at place, groove 107 bottom for example is a doped region 105.The formation method of groove 107 for example is prior to forming one deck patterned mask layer (not illustrating) in the substrate 100, is mask with the patterned mask layer again, removes the substrate 100 of part and forms it.The method that removes part substrate 100 for example is to utilize the chlorine atom to carry out dry-etching to remove it for the reacting gas on basis.
Then, please refer to Figure 1B, in groove 107, form one deck tunneling dielectric layer 110.The material of tunneling dielectric layer 110 for example is a silica, and its formation method for example is thermal oxidation method or chemical vapour deposition technique.Then, in groove 107, form electric charge storage layer 120.The material of relative two side electric charge storage layer 120 for example is conductor materials such as doped polycrystalline silicon, metal or metal silicide, its formation method for example is to form one deck conductor layer (not illustrating) earlier, in the mode of etch-back, remove in the substrate 100 again in the segment conductor layer of groove 107 central authorities; Perhaps also can be after forming conductor layer, utilize chemical mechanical milling tech earlier, remove the conductor layer in the substrate 100, carry out anisotropic etching again, remove the segment conductor layer of groove 107 central authorities.Certainly, electric charge storage layer 120 also can be directly in the etched mode of photoetching, and patterning conductor layer is to form it.The formation method of conductor layer for example is the difference according to its material, adopts chemical vapour deposition technique or physical vaporous deposition to form it.
Electric charge storage layer 120 also can be one deck electric charge capture layer, and its material for example is a silicon nitride, and its formation method for example is a chemical vapour deposition technique.Certainly, the material of electric charge capture layer is not limited to silicon nitride, also can be that other can make electric charge capture in material wherein, for example materials such as tantalum oxide layer, strontium titanate layer and hafnium oxide layer.
What deserves to be mentioned is that the electric charge storage layer 120 among Figure 1B is made up of two Charge Storage blocks that are positioned at groove 107 two sides.Yet, in one embodiment, in formation electric charge storage layer 120, also can not remove the electric charge storage layer 120 of groove 107 bottoms, the electric charge storage layer of Xing Chenging then, just can be along the whole U of one-tenth type electric charge storage layer of groove 107 sidewalls, and can not be separated into two Charge Storage blocks with the bottom.
Then, please refer to Fig. 1 C, in substrate 100, form one deck dielectric materials layer (not illustrating), fill up groove 107 and cover the surface of substrate 100.The material of dielectric materials layer for example is a silica, and its formation method for example is to utilize chemical vapour deposition technique to form it.
Afterwards, the part dielectric materials layer and the Partial charge that remove in substrate 100 lip-deep dielectric materials layers and the groove 107 store layer 120, make the surface of electric charge storage layer 120 be lower than the surface of substrate 100, and form the dielectric layer 130 that layer of surface is lower than electric charge storage layer 120.Removing the method that part dielectric materials layer and Partial charge store layer 120 for example is the dry-etching method of carrying out, by the control of etching period, with the surface etching of dielectric materials layer to the surface that is lower than electric charge storage layer 130.Because dielectric materials layer, tunneling dielectric layer 110 for example is identical materials with isolation structure, therefore, for example be to remove tunneling dielectric layer 110 in the substrate 100 and the part dielectric material in the isolation structure in the lump when removing dielectric materials layer.
Then, in forming dielectric layer 135 between one deck grid in the substrate 100, cover electric charge storage layer 120 at least.The material of dielectric layer 135 for example is a silica between grid, and its formation method for example is a chemical vapour deposition technique.
Then, please refer to Fig. 1 D, in groove 107, form grid 140.The formation method of grid 140 for example is prior to forming one deck conductor material layer (not illustrating) in the substrate 100, fill up groove 107 and cover substrate 100, removes segment conductor material layer in the substrate 100 and in the groove 107 afterwards to form it.The material of conductor material layer for example is doped polycrystalline silicon, metal or metal silicide.Wherein, if the material of conductor material layer is a doped polycrystalline silicon, its formation method for example is after utilizing chemical vapour deposition technique to form one deck undoped polycrystalline silicon layer earlier, to carry out the ion implantation step to form it; Perhaps also can adopt the on-the-spot mode of injecting alloy, form it with chemical vapour deposition technique.If the material of conductor material layer is that metal and metal silicide then can utilize chemical vapour deposition technique or physical vaporous deposition to form it.The method that removes the segment conductor material layer in the substrate 100 and in the groove 107 for example is earlier to remove conductor material layer in the substrate 100 with chemical mechanical milling method, utilizes the segment conductor material layer in dry-etching method or the wet etching etch-back groove 107 again.Because dielectric layer 135 thickness are little between the grid on substrate 100 surfaces, in the time of the conductor material layer that removes in the substrate 100, dielectric layer 135 also may and then be removed between grid.
Then, please refer to Fig. 1 E, on grid 140, form layer protective layer 150, fill up groove 107.The material of protective layer 150 for example is a silicon nitride, and its formation method for example is to utilize chemical vapour deposition technique to form protective layer 150 earlier, again with cmp planarization protective layer 150, polish to substrate 100 surfaces rough contour till.
In one embodiment, protective layer 150 also can be the silica that forms with thermal oxidation method.Be noted that,, in the then above-mentioned formation grid 140, just can not remove the segment conductor material layer in the groove 107 if protective layer 150 is the silica that form with thermal oxidation method.That is to say that grid 140 not necessarily as shown in Fig. 1 D, is lower than substrate 100 surfaces, also can be rough contour with substrate 100 surfaces.
Continue it, form doped region 155 in groove 107 substrate on two sides 100 tops.It is suitable with the degree of depth of protective layer 150 that the degree of depth of doped region 155 is preferably.The formation method of doped region 155 for example is diffusion method or ion implantation technology, and the alloy among the doped region 155 for example is N type alloy or P type alloy, and it is looked closely circuit elements design and decides.
The top view of the non-volatility memorizer that Fig. 2 is illustrated for Fig. 1 E.Please refer to Fig. 2, what the label among the label among Fig. 2 and Fig. 1 E was represented is components identical.Fig. 1 E illustrates among Fig. 2 the generalized section along I-I ' line.From Fig. 2, can clearly see grid 140 for example be strip be arranged in parallel.This is because the part dielectric material in the isolation structure 102, when forming dielectric layer 130 in Fig. 1 C, has been removed, and therefore, grid 140 is to stride across isolation structure 102 and be provided with, and grid 140 for example is to be checkerboard to be staggered with isolation structure 102.120 of electric charge storage layers are to be arranged between the isolation structure 102, are positioned at the below of grid 140.Grid 140 both sides for example are doped regions 155.
The structure of the formed memory of manufacture method of above-mentioned non-volatility memorizer below is described.Fig. 3 illustrates a kind of non-volatile memory structure profile of one embodiment of the invention.
Please refer to Fig. 3; the present invention proposes a kind of non-volatility memorizer, and it is made of with doped region 255 dielectric layer 235, grid 240, protective layer 255, doped region 205 between substrate 200, tunneling dielectric layer 210, electric charge storage layer 220, dielectric layer 230, grid.
Be provided with a groove 207 in the substrate 200.Electric charge storage layer 220 is arranged in the groove 207, and the top of electric charge storage layer 220 is lower than substrate 200 surfaces.Electric charge storage layer 220 for example is as shown in Figure 3, is made of two Charge Storage blocks that are arranged at the relative two side of groove 207.In one embodiment, electric charge storage layer 220 also can be to be provided with along the sidewall of groove 207 and bottom, forms single Charge Storage block (not illustrating) that is the U type.
For example be to be provided with one deck tunneling dielectric layer 210 between electric charge storage layer 220 and the groove 207.Grid 240 is arranged in the groove 207, and grid 240 can also extend in the electric charge storage layer 220.For example be to be provided with dielectric layer 230 between one deck grid between grid 240 and the electric charge storage layer 220.
The material of electric charge storage layer 220 for example is a doped polycrystalline silicon.Perhaps, electric charge storage layer 220 also can be one deck electric charge capture layer, and its material for example is a silicon nitride or other can make electric charge capture in material wherein, for example tantalum pentoxide, strontium titanates thing or hafnium oxide etc.The material of grid 240 for example is a doped polycrystalline silicon.The material of protective layer 250 for example is silica or silicon nitride.Tunneling dielectric layer 210 for example is a silica with the material of dielectric layer 230.The material of dielectric layer 235 for example is a silica between grid.Doped region 205 and doped region 255 for example are the doped regions of N type or P type alloy of having mixed.
Above-mentioned mode of operation with non-volatility memorizer of two electric charge storage layers 220 below is described.When carrying out programming operation, for example be to apply high voltage in doped region 205 (source electrode), apply low-voltage in doped region 255 (drain electrode), apply a little higher than voltage that makes voltage that opens in grid 240, utilize source side to inject (Source Side Injection) effect, among electronics iunjected charge storage layer 220.When programming is carried out, for example be upper limb generation maximum horizontal and vertical electric field, to carry out the programming operation of memory in electric charge storage layer 220.
When carrying out erase operation, for example be to apply high voltage, utilize the F-N tunneling effect, the electronics in the electric charge storage layer 220 is pulled out in grid 240.Certainly, this kind non-volatility memorizer can also by the quantity of electric charge number in the control electric charge storage layer 220, and be stored more bits of data as the application of multistage (Multi-Level) memory.
Described according to the embodiment of the invention, the present invention forms groove again prior to forming doped region in the substrate in substrate.Then in groove, form tunnel oxide, electric charge storage layer and dielectric layer in regular turn, utilize the shape of dielectric layer, directly insert grid, and in the substrate around the groove top, form doped region.Because plough groove type memory of the present invention is that electric charge storage layer and grid erectly are arranged among the groove, therefore can significantly reduce the shared area of each memory cell, not only can dwindle the size of memory cell, improve the integrated level of element, more can increase the space of circuit layout.
In addition, because the channel region of plough groove type memory of the present invention is to be arranged at (rectilinear channel region) in the substrate, therefore can increase the element integrated level, and can control channel length accurately by the degree of depth of control groove, and then the problem that is produced can avoid component size to dwindle the time.And the memory construction of this kind column can improve current density, and promotes the efficient of the program/erase operations of memory component.
Though the present invention discloses as above with preferred embodiment; yet it is not in order to limit the present invention; those skilled in the art can do a little change and retouching without departing from the spirit and scope of the present invention, thus protection scope of the present invention should with claim the person of being defined be as the criterion.
Claims (25)
1. the manufacture method of a non-volatility memorizer comprises:
Substrate is provided;
Form first doped region in this substrate, this first doped region and this substrate surface are at a distance of a distance;
Form groove in this substrate, this channel bottom exposes this first doped region;
Form electric charge storage layer in these groove both sides, the top of this electric charge storage layer is lower than this substrate surface;
Form grid and protective layer in this groove, wherein this protective layer covers the surface of this grid fully; And
This base top in these groove both sides forms second doped region.
2. the manufacture method of non-volatility memorizer as claimed in claim 1, the method that wherein forms this electric charge storage layer comprises:
In this substrate, form the charge storage material layer, insert this groove; And
Remove this charge storage material layer of part in this suprabasil this charge storage material layer and this groove.
3. the manufacture method of non-volatility memorizer as claimed in claim 2, the step of this charge storage material layer of the part in removing this groove wherein, also comprise this charge storage material layer of part that removes this channel bottom, form the two Charge Storage blocks that are positioned at this groove two lateral walls separation.
4. the manufacture method of non-volatility memorizer as claimed in claim 3 wherein also is included in formation and is positioned at after the two Charge Storage blocks of this groove two lateral walls separation, forms dielectric layer between this two Charge Storage block.
5. the manufacture method of non-volatility memorizer as claimed in claim 1, wherein after the step that forms this groove with the step of this electric charge storage layer of formation before, also be included in this groove and form tunneling dielectric layer.
6. the manufacture method of non-volatility memorizer as claimed in claim 5, wherein the formation method of this tunneling dielectric layer comprises thermal oxidation method.
7. the manufacture method of non-volatility memorizer as claimed in claim 1, wherein after the step that forms this electric charge storage layer with the step of this grid of formation before, also be included in and form dielectric layer between grid in this groove, dielectric layer covers this electric charge storage layer at least between these grid.
8. the manufacture method of non-volatility memorizer as claimed in claim 1, wherein the material of this protective layer comprises silicon nitride or silica.
9. the manufacture method of non-volatility memorizer as claimed in claim 1, wherein the formation method of this protective layer comprises chemical vapour deposition technique or thermal oxidation method.
10. the manufacture method of non-volatility memorizer as claimed in claim 1, wherein the material of this electric charge storage layer comprises doped polycrystalline silicon.
11. the manufacture method of non-volatility memorizer as claimed in claim 1, wherein this electric charge storage layer comprises electric charge capture layer.
12. the manufacture method of non-volatility memorizer as claimed in claim 11, wherein the material of this electric charge capture layer comprises silicon nitride.
13. the manufacture method of non-volatility memorizer as claimed in claim 1, wherein the material of this grid comprises doped polycrystalline silicon.
14. the manufacture method of non-volatility memorizer as claimed in claim 1, wherein the formation method of this grid comprises:
In this substrate, form conductor layer, fill up this groove, and cover this substrate; And
Remove this conductor layer of part.
15. a non-volatility memorizer comprises:
Substrate has groove in this substrate;
Electric charge storage layer be arranged at this groove both sides, and the top of this electric charge storage layer is lower than this substrate surface;
Grid and protective layer are arranged in this groove, and this protective layer covers the surface of this grid fully;
First doped region is arranged in this substrate of this channel bottom; And
Second doped region is arranged in this substrate of these both sides, groove top.
16. non-volatility memorizer as claimed in claim 15, wherein this electric charge storage layer is the U type.
17. non-volatility memorizer as claimed in claim 15, wherein this electric charge storage layer is divided into two Charge Storage blocks, and this two Charge Storage block is separated from one another, is arranged in the relative two side of this groove.
18. non-volatility memorizer as claimed in claim 15 wherein also comprises tunneling dielectric layer between this electric charge storage layer and this groove.
19. non-volatility memorizer as claimed in claim 15 wherein also comprises dielectric layer between grid between this grid and this electric charge storage layer.
20. non-volatility memorizer as claimed in claim 15 wherein also comprises dielectric layer in this electric charge storage layer, the surface of this dielectric layer is lower than the top of this electric charge storage layer.
21. non-volatility memorizer as claimed in claim 15, wherein the material of this protective layer comprises silica or silicon nitride.
22. non-volatility memorizer as claimed in claim 15, wherein the material of this electric charge storage layer comprises doped polycrystalline silicon.
23. non-volatility memorizer as claimed in claim 15, wherein this electric charge storage layer comprises electric charge capture layer.
24. non-volatility memorizer as claimed in claim 23, wherein the material of this electric charge capture layer comprises silicon nitride.
25. non-volatility memorizer as claimed in claim 15, wherein the material of this grid comprises doped polycrystalline silicon.
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| CNB2005101297463A CN100463145C (en) | 2005-12-06 | 2005-12-06 | Non-volatile memory and production method |
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| CNB2005101297463A CN100463145C (en) | 2005-12-06 | 2005-12-06 | Non-volatile memory and production method |
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| CN100463145C true CN100463145C (en) | 2009-02-18 |
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| CN101707213B (en) * | 2009-01-23 | 2011-05-25 | 旺宏电子股份有限公司 | Memory and preparation method thereof |
| CN105161492A (en) * | 2015-08-04 | 2015-12-16 | 武汉新芯集成电路制造有限公司 | Floating gate flash memory structure and preparation method thereof |
| TWI685954B (en) * | 2018-12-13 | 2020-02-21 | 力晶積成電子製造股份有限公司 | Non-volatile memory structure and manufacturing method thereof |
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| US5616510A (en) * | 1992-11-02 | 1997-04-01 | Wong; Chun C. D. | Method for making multimedia storage system with highly compact memory cells |
| US20030122204A1 (en) * | 2000-10-26 | 2003-07-03 | Kazumasa Nomoto | Nonvolatile semiconductor storage and method for manufacturing the same |
| CN1464562A (en) * | 2002-06-25 | 2003-12-31 | 中仪科技股份有限公司 | High density flash memory |
| US20040108542A1 (en) * | 2002-10-21 | 2004-06-10 | Chi-Hui Lin | Stacked gate flash memory device and method of fabricating the same |
| US20040209428A1 (en) * | 2002-10-21 | 2004-10-21 | Nanya Technology Corporation | Split gate flash memory device and method of fabricating the same |
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Patent Citations (5)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US5616510A (en) * | 1992-11-02 | 1997-04-01 | Wong; Chun C. D. | Method for making multimedia storage system with highly compact memory cells |
| US20030122204A1 (en) * | 2000-10-26 | 2003-07-03 | Kazumasa Nomoto | Nonvolatile semiconductor storage and method for manufacturing the same |
| CN1464562A (en) * | 2002-06-25 | 2003-12-31 | 中仪科技股份有限公司 | High density flash memory |
| US20040108542A1 (en) * | 2002-10-21 | 2004-06-10 | Chi-Hui Lin | Stacked gate flash memory device and method of fabricating the same |
| US20040209428A1 (en) * | 2002-10-21 | 2004-10-21 | Nanya Technology Corporation | Split gate flash memory device and method of fabricating the same |
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