CN100459128C - Wafer for realizing the chip pin compatibility and method - Google Patents
Wafer for realizing the chip pin compatibility and method Download PDFInfo
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- CN100459128C CN100459128C CNB2007100991517A CN200710099151A CN100459128C CN 100459128 C CN100459128 C CN 100459128C CN B2007100991517 A CNB2007100991517 A CN B2007100991517A CN 200710099151 A CN200710099151 A CN 200710099151A CN 100459128 C CN100459128 C CN 100459128C
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Abstract
The invention discloses a wafer and method that implements the chip pin-compatible, to solve the problem existent in the existing technology that can implement the chip pin-compatible. The said wafer of the invention includes functional circuit unit as well as certain weld pads, wherein the said functional circuit unit is used to implement the various functions of the chip, characterized in that the specific weld pad of the said certain weld pads is linked to the pin of the said chip. This wafer also comprises: a pin-compatible unit for selecting an input signal of said specific weld pad from the input signals of said certain weld pads as an input signal of the said functional circuit unit, based on the specific value connected to the selected signal. The invention also discloses a method for implementing the chip pin-compatible. The invention is used to implement the pin-compatible of various chips, preventing the fussy of the existing technology which needs to redesign chip layout according to application of each kind of chip, as well as the production of the corresponding wafer (die), which makes the design and production of chip more convenient.
Description
Technical field
The present invention relates to electronic technology field, relate in particular to a kind of wafer and method that realizes chip pin compatibility.
Background technology
In a kind of large-scale production of chip, sometimes need and to have the chip application of identical function in different environment, the relevant chip pin distributes also different, for example, the veneer that has is shaped as rectangle, the veneer that has is shaped as square, may require the chip on the veneer also to be rectangle or square so, with shape and the area that meets veneer, the shape that has the chip of said function so may be different in different veneers, input and output pin on the chip also may be different, and therefore, the chip application with said function needs to design different chip pin layouts on different veneers.
The common methods of prior art is at each applied environment, does a chip design again, does a chip production again and realizes the application of this chip in specific environment.
Chip Packaging of the prior art adopts the flat encapsulation (QFP of square more; Quad Flat Package) encapsulation format; distance is very little between the pin of the cpu chip that this technology realizes; pin is very thin; this packing forms of the many employings of general extensive or very lagre scale integrated circuit (VLSIC); for example; in the chip layout of chip pad (pad) (floor plan); (bonding wire) moves weld pad on the corresponding pin to by bonding wire; wherein; described chip layout is a step in the chip design, is meant according to certain requirement and rule each functional unit to be placed in certain area.
In sum, prior art can't realize the pin compatibility (pin-to-pin) of chip, when same chip application during in varying environment, need the redesign chip, wherein, described pin compatibility is meant that the package size of two kinds of chips is identical, and number of pins and the position of putting are identical.
Summary of the invention
The invention provides a kind of wafer and method that realizes chip pin compatibility, have the problem that can't realize chip pin compatibility in the prior art in order to solve.
A kind of wafer of realizing chip pin compatibility provided by the invention, comprise functional circuit unit and some weld pads, described functional circuit unit is used to realize the various functions of chip, and the specific weld pad in described some weld pads links to each other with the pin of described chip, and this wafer also comprises:
The pin compatibility unit is used for according to the particular value that connects the selection signal, and selecting the input signal of described specific weld pad from the input signal of described some weld pads is the input signal of described functional circuit unit.
Described particular value is a high level;
Described pin compatibility unit comprises:
First memory cell is used to store the high value of selecting signal to be provided with for described connection in advance;
First module is used for the high value according to described connection selection signal, and selecting the input signal of described specific weld pad from the input signal of described some weld pads is the input signal of described functional circuit unit.
Described particular value is a low level;
Described pin compatibility unit comprises:
Second memory cell is used to store the low level value of selecting signal to be provided with for described connection in advance;
Unit second is used for the low level value according to described connection selection signal, and selecting the input signal of described specific weld pad from the input signal of described some weld pads is the input signal of described functional circuit unit.
Described pin compatibility unit also comprises:
First is provided with the unit, is used for selecting signal to link to each other with power supply described connection, realizes that it is high level that the value of signal is selected in described connection.
Described pin compatibility unit also comprises:
Second is provided with the unit, is used for selecting signal to link to each other with ground described connection, realizes that it is low level that the value of signal is selected in described connection.
A kind of method that realizes chip pin compatibility provided by the invention, the wafer of described chip comprises functional circuit unit and some weld pads, described method comprises:
Specific weld pad in described some weld pads is linked to each other with the pin of described chip, and in described wafer, the pin compatibility unit is set;
Described pin compatibility unit is according to connecting the particular value of selecting signal, and selecting the input signal of described specific weld pad from the input signal of described some weld pads is the input signal of described functional circuit unit.
Described particular value is a high level;
Described pin compatibility unit is according to the high value of described connection selection signal, and selecting the input signal of described specific weld pad from the input signal of described some weld pads is the input signal of described functional circuit unit.
Described particular value is a low level;
Described pin compatibility unit is according to the low level value of described connection selection signal, and selecting the input signal of described specific weld pad from the input signal of described some weld pads is the input signal of described functional circuit unit.
Described pin compatibility unit realizes that by selecting signal to link to each other with power supply described connection it is high level that the value of signal is selected in described connection.
Described pin compatibility unit realizes that by selecting signal to link to each other with ground described connection it is low level that the value of signal is selected in described connection.
The present invention is by being connected the specific weld pad in the chip with the pin of described chip, and select signal for the connection of described chip particular value is set, according to described particular value, selecting the input signal of described specific weld pad from the input signal of described chip pad is the technical characterictic of the input signal of described chip, realized the pin compatibility of various chips, avoided prior art to redesign chip layout, and produced the loaded down with trivial details of corresponding wafer (die) at the application of every kind of chip.Therefore,,, just can realize the chip that different pins distribute, make that the design of chip and production are more convenient as long as same wafer done different encapsulation by scheme provided by the invention.
Description of drawings
Fig. 1 is the pin distribution schematic diagram of embodiment of the invention chips A;
Fig. 2 is the pin distribution schematic diagram of embodiment of the invention chips B;
Fig. 3 is the chip architecture schematic diagram of the embodiment of the invention one;
Fig. 4 is the chip architecture schematic diagram of the embodiment of the invention two;
Fig. 5 is the pin distribution schematic diagram of the wafer of embodiment of the invention realization;
Fig. 6 is a selector schematic diagram in the embodiment of the invention;
Fig. 7 is the method flow schematic diagram of the embodiment of the invention three;
Fig. 8 is the method flow schematic diagram of the embodiment of the invention four.
Embodiment
A kind of wafer and method that realizes chip pin compatibility provided by the invention, specific weld pad in the chip is connected with the pin of described chip, and select signal for the connection of described chip particular value is set, according to described particular value, selecting the input signal of described specific weld pad from the input signal of described chip pad is the input signal of described chip, by this technical characterictic, realized the pin compatibility of various chips, avoided prior art to redesign chip layout at the application of every kind of chip, and the production relevant chip is loaded down with trivial details, the present invention is as long as do different encapsulation to same wafer, just can realize the chip that different pins distribute, make that the design of chip and production are more convenient.
A kind of wafer of realizing chip pin compatibility that the embodiment of the invention provides, be positioned at chip internal, has only a wafer (Die) on the chip, described wafer is meant that chip removes the part of being exposed behind encapsulation and the connecting line, it is a semiconductor chip, placed the transistor of some numbers above, they couple together has certain function.For example, described wafer can be an image and audio collection chip, behind image and sound collection, be sent on the computer by interface, wafer of the present invention is used for the pin compatibility of realization to many moneys chip (the especially flat encapsulation of square), and needn't design a kind of wafer respectively at every kind of different chip of pin distribution.
Illustrate respectively below in conjunction with accompanying drawing how the embodiment of the invention realizes.
The wafer that the embodiment of the invention provides is used for realizing the pin compatibility of A, two kinds of chips of B, A, two kinds of chips of B be encapsulated as QFP, A has 16 pins, B has 20 pins, their pin is arranged respectively as depicted in figs. 1 and 2, these two kinds of chips all have a signal pin M, the position difference of this signal pin in two kinds of chips.
Quote in the embodiment of the invention to connect and select (BO, Bonding Option) notion adds one and connects selection weld pad (bonding option pad) on the wafer of design, utilize it to distinguish the encapsulation of A, B two class chips, when bonding option is 0, the encapsulation of expression A chip; When bonding option is 1, the encapsulation of expression B chip; In addition, for wafer adds M1, two pad of M2 realize the function of signal pin M.For the encapsulation of A chip, use M1 to realize the function of pin M, for the encapsulation of B chip, use M2 to realize the function of pin M.
Embodiment one:
Referring to Fig. 3, the wafer 31 that the embodiment of the invention provided comprises: functional circuit unit 311, weld pad 312, specific weld pad 313 and pin compatibility unit 314;
Wherein, described pin compatibility unit 314 comprises: first is provided with unit 3141, first memory cell 3142 and first module 3143;
Described functional circuit unit 311 is used to realize the various functions of chip.
Described specific weld pad 313 and other weld pads 312 are the weld pads with said function, and specific weld pad 313 described in the present embodiment links to each other with the pin 32 of chip;
Described pin 32 is used for realizing the function of described pin M.
Described specific weld pad 313 is described weld pad M1, and described other weld pads 312 comprise described weld pad M2.
Described pin compatibility unit 314 is used for according to the particular value that connects the selection signal, and selecting the input signal of described specific weld pad from the input signal of described some weld pads is the input signal of described functional circuit unit 311.
Particular value described in the present embodiment is a high level;
Then described first is provided with unit 3141, is used for selecting signal BO to link to each other with power vd D described connection, realizes that it is high level that the value of signal is selected in described connection;
Described first memory cell 3142 is used to store in advance for connecting the high value of selecting signal to be provided with;
Described first module 3143 is used for the high value according to described connection selection signal, and selecting the input signal of described specific weld pad from the input signal of described some weld pads is the input signal of described functional circuit unit 311.
Embodiment two:
Referring to Fig. 4, a kind of wafer 41 of realizing chip pin compatibility that the embodiment of the invention provides is positioned at chip internal, and described wafer comprises: functional circuit unit 411, weld pad 412, specific weld pad 413 and pin compatibility unit 414;
Wherein, described pin compatibility unit 414 comprises: second is provided with unit 4141, second memory cell 4142 and second unit 4143;
Described functional circuit unit 411 is used to realize the various functions of chip.
Described specific weld pad 413 and other weld pads 412 can be the weld pads with said function, and specific weld pad 413 described in the present embodiment links to each other with the pin 42 of chip;
Described pin 42 is used for realizing the function of described pin M.
Described specific weld pad 413 is described weld pad M2, and described other weld pads 412 comprise described weld pad M1.
Described pin compatibility unit 414 is used for according to the particular value that connects the selection signal, and selecting the input signal of described specific weld pad from the input signal of described some weld pads is the input signal of described functional circuit unit 411.
Described in the present embodiment particular value is a low level;
Then described second is provided with unit 4141, is used for selecting signal BO to link to each other with ground VSS described connection, realizes that it is low level that the value of signal is selected in described connection;
Described second memory cell 4142 is used to store the low level value of selecting signal to be provided with for described connection in advance;
Described second unit 4143 is used for the low level value according to described connection selection signal, and selecting the input signal of described specific weld pad from the input signal of described chip pad is the input signal of described functional circuit unit 411.
To sum up, referring to Fig. 5, among the die that the embodiment of the invention one and embodiment two realize, comprise pad such as BO (bondingoption), M1, M2, VDD and VSS;
In real work, can adopt selector logically to realize the selection function of chip input signal, for example when pin M as when input, from M1 and M2, select a input, referring to Fig. 6 as chip, be the schematic diagram of described selector, the function of this selector is:
When BO is 0, M=M1;
At this moment, realized the function of chip A encapsulation, wherein,, realized that BO is 0 by in advance BO being connected on the VSS;
When BO is 1, M=M2;
At this moment, realized the function of chip B encapsulation, wherein,, realized that BO is 1 by in advance BO being connected on the VDD.
Embodiment three:
Referring to Fig. 7, a kind of method that realizes chip pin compatibility that the embodiment of the invention provides, the wafer of described chip comprises functional circuit unit and some weld pads, and the specific weld pad in described some weld pads links to each other with the pin of described chip, and this method comprises:
S701, by selecting signal to link to each other the connection of described chip with power supply, realize that the value of described connection selection signal is a high level;
S702, select the high value of signal according to described connection, selecting the input signal of described specific weld pad from the input signal of described some weld pads is the input signal of described functional circuit unit.
Embodiment four:
Referring to Fig. 8, a kind of method that realizes chip pin compatibility that the embodiment of the invention provides, the wafer of described chip comprises functional circuit unit and some weld pads, and the specific weld pad in described some weld pads links to each other with the pin of described chip, and this method comprises:
S801, by selecting signal to link to each other the connection of described chip with ground, realize that it is low level that the value of signal is selected in described connection;
S802, select the low level value of signal according to described connection, selecting the input signal of described specific weld pad from the input signal of described some weld pads is the input signal of described functional circuit unit.
In sum, a kind of wafer and method that realizes chip pin compatibility provided by the invention, specific weld pad in the chip is connected with the pin of described chip, and select signal for the connection of described chip particular value is set, according to described particular value, selecting the input signal of described specific weld pad from the input signal of described chip pad is the input signal of described chip, by technical scheme provided by the invention, realized the pin compatibility of various chips, avoided prior art to redesign chip layout at the application of every kind of chip, and produce the loaded down with trivial details of corresponding wafer, by scheme provided by the invention, as long as same wafer done different encapsulation, just can realize the chip that different pins distribute, make that the design of chip and production are more convenient.
Obviously, those skilled in the art can carry out various changes and modification to the present invention and not break away from the spirit and scope of the present invention.Like this, if of the present invention these are revised and modification belongs within the scope of claim of the present invention and equivalent technologies thereof, then the present invention also is intended to comprise these changes and modification interior.
Claims (10)
1, a kind of wafer of realizing chip pin compatibility, comprise functional circuit unit and some weld pads, described functional circuit unit is used to realize the various functions of chip, and described wafer is characterised in that, specific weld pad in described some weld pads links to each other with the pin of described chip, and this wafer also comprises:
The pin compatibility unit is used for according to the particular value that connects the selection signal, and selecting the input signal of described specific weld pad from the input signal of described some weld pads is the input signal of described functional circuit unit.
2, wafer as claimed in claim 1 is characterized in that, described particular value is a high level;
Described pin compatibility unit comprises:
First memory cell is used to store the high value of selecting signal to be provided with for described connection in advance;
First module is used for the high value according to described connection selection signal, and selecting the input signal of described specific weld pad from the input signal of described some weld pads is the input signal of described functional circuit unit.
3, wafer as claimed in claim 1 is characterized in that, described particular value is a low level;
Described pin compatibility unit comprises:
Second memory cell is used to store the low level value of selecting signal to be provided with for described connection in advance;
Unit second is used for the low level value according to described connection selection signal, and selecting the input signal of described specific weld pad from the input signal of described some weld pads is the input signal of described functional circuit unit.
4, wafer as claimed in claim 2 is characterized in that, described pin compatibility unit also comprises:
First is provided with the unit, is used for selecting signal to link to each other with power supply described connection, realizes that it is high level that the value of signal is selected in described connection.
5, wafer as claimed in claim 3 is characterized in that, described pin compatibility unit also comprises:
Second is provided with the unit, is used for selecting signal to link to each other with ground described connection, realizes that it is low level that the value of signal is selected in described connection.
6, a kind of method that realizes chip pin compatibility, the wafer of described chip comprises functional circuit unit and some weld pads, described method is characterised in that described method comprises:
Specific weld pad in described some weld pads is linked to each other with the pin of described chip, and in described wafer, the pin compatibility unit is set;
Described pin compatibility unit is according to connecting the particular value of selecting signal, and selecting the input signal of described specific weld pad from the input signal of described some weld pads is the input signal of described functional circuit unit.
7, method as claimed in claim 6 is characterized in that, described particular value is a high level;
Described pin compatibility unit is according to the high value of described connection selection signal, and selecting the input signal of described specific weld pad from the input signal of described some weld pads is the input signal of described functional circuit unit.
8, method as claimed in claim 6 is characterized in that, described particular value is a low level;
Described pin compatibility unit is according to the low level value of described connection selection signal, and selecting the input signal of described specific weld pad from the input signal of described some weld pads is the input signal of described functional circuit unit.
9, method as claimed in claim 7 is characterized in that, described pin compatibility unit realizes that by selecting signal to link to each other with power supply described connection it is high level that the value of signal is selected in described connection.
10, method as claimed in claim 8 is characterized in that, described pin compatibility unit realizes that by selecting signal to link to each other with ground described connection it is low level that the value of signal is selected in described connection.
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| Application Number | Priority Date | Filing Date | Title |
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| CNB2007100991517A CN100459128C (en) | 2007-05-14 | 2007-05-14 | Wafer for realizing the chip pin compatibility and method |
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| CNB2007100991517A CN100459128C (en) | 2007-05-14 | 2007-05-14 | Wafer for realizing the chip pin compatibility and method |
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| CN101055870A CN101055870A (en) | 2007-10-17 |
| CN100459128C true CN100459128C (en) | 2009-02-04 |
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| CN105633058B (en) * | 2015-12-31 | 2018-06-29 | 上海安路信息科技有限公司 | Device identification structure and its manufacturing method |
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| US6417695B1 (en) * | 2001-03-15 | 2002-07-09 | Micron Technology, Inc. | Antifuse reroute of dies |
| US6563742B1 (en) * | 2001-03-02 | 2003-05-13 | Aplus Flash Technology, Inc. | Method to turn a flash memory into a versatile, low-cost multiple time programmable EPROM |
| CN1525561A (en) * | 2003-08-29 | 2004-09-01 | 北京中星微电子有限公司 | Chip having input and output terminal configurable function and method thereof |
| CN1645603A (en) * | 2004-12-24 | 2005-07-27 | 北京中星微电子有限公司 | Circuit and chip for inter-changing chip pin function |
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- 2007-05-14 CN CNB2007100991517A patent/CN100459128C/en active Active
Patent Citations (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US6563742B1 (en) * | 2001-03-02 | 2003-05-13 | Aplus Flash Technology, Inc. | Method to turn a flash memory into a versatile, low-cost multiple time programmable EPROM |
| US6417695B1 (en) * | 2001-03-15 | 2002-07-09 | Micron Technology, Inc. | Antifuse reroute of dies |
| CN1525561A (en) * | 2003-08-29 | 2004-09-01 | 北京中星微电子有限公司 | Chip having input and output terminal configurable function and method thereof |
| CN1645603A (en) * | 2004-12-24 | 2005-07-27 | 北京中星微电子有限公司 | Circuit and chip for inter-changing chip pin function |
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Effective date of registration: 20210127 Address after: No. 607, 6th floor, shining building, 35 Xueyuan Road, Haidian District, Beijing 100083 Patentee after: BEIJING VIMICRO ARTIFICIAL INTELLIGENCE CHIP TECHNOLOGY Co.,Ltd. Address before: 100083, Haidian District, Xueyuan Road, Beijing No. 35, Nanjing Ning building, 15 Floor Patentee before: Vimicro Corp. |
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