CN100454519C - Semiconductor device and manufacturing method thereof - Google Patents
Semiconductor device and manufacturing method thereof Download PDFInfo
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- CN100454519C CN100454519C CNB2006101321382A CN200610132138A CN100454519C CN 100454519 C CN100454519 C CN 100454519C CN B2006101321382 A CNB2006101321382 A CN B2006101321382A CN 200610132138 A CN200610132138 A CN 200610132138A CN 100454519 C CN100454519 C CN 100454519C
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Abstract
Gate trenches 108 are formed in a memory cell region M using a silicon nitride film 103 as a mask in a state in which the semiconductor substrate 100 in a P-type peripheral circuit region P and an N-type peripheral circuit region N is covered by a gate insulating film 101 s, a protective film 102 , and the silicon nitride film 103 . A gate insulating film 109 is then formed on the inner walls of the gate trenches 108 , and a silicon film 110 that includes an N-type impurity is embedded in the gate trenches 108 . The silicon nitride film 103 is then removed, and a non-doped silicon film is formed on the entire surface, after which a P-type impurity is introduced into the non-doped silicon film on region P, and an N-type impurity is introduced into the non-doped silicon film on regions M and N.
Description
Technical field
The present invention relates to a kind of semiconductor device and manufacture method thereof, in particular to a kind of semiconductor device and manufacture method thereof that possesses trench-gate transistors and double-gated transistor.
Background technology
It is long that the miniaturization of DRAM (dynamic random access memory) unit in recent years always must be accompanied by the grid that shorten memory cell transistor.Yet along with the long shortening of grid, the short-channel effect in the transistor is serious further, and the problem that subthreshold current increases can occur.When increasing substrate doping density so that short-channel effect when minimizing, because the deterioration that the increase of junction leakage causes refreshing characteristic among the DRAM becomes serious problems.
For addressing these problems, be conceived to a kind of so-called trench-gate transistors (being also referred to as the fluted body transistor), it is meant and embeds gate electrode in the formed groove (referring to TOHKEMY No.H9-232535 on silicon substrate, 2001-210801,2005-142203, H7-066297, and 2004-014696).Adopt trench-gate transistors, can structurally keep length of effective channel (grid are long) fully, and make that making the accurate DRAM that possesses 90nm or lower minimum feature size becomes possibility.
Peripheral circuit region at DRAM adopts the transistor that possesses double-gate structure to become inevitable, like this can be so that device performance obtains to improve and its driving voltage is minimized.In double-gate structure, by the gate electrode of the gate electrode that includes the N type polysilicon that has injected N type impurity (phosphorus or other), by the gate electrode of the gate electrode that includes the P type polysilicon that has injected p type impurity (boron or other) as p channel transistor as the N channel transistor.
But, when employing possessed the transistor of above-mentioned two kinds of structures simultaneously in single semiconductor device, described subsequently problem can appear.Particularly, when forming trench-gate transistors in the memory cell district, and when peripheral circuit region forms double-gated transistor, described subsequently problem can appear.
Below at first explanation is used to form the usual method of the electrode of the electrode of trench-gate transistors and double-gated transistor.
Gate electrode in the trench-gate transistors forms by following process: form groove (gate groove) in Semiconductor substrate, and form gate insulating film on the inwall of this gate groove, then, imbed the doping silicon fiml as gate material in gate groove inside.
On the other hand, form the gate electrode of double-gated transistor by the following method: on Semiconductor substrate above the formed gate insulating film, form non-doping silicon fiml, then, cover Etching mask in the zone that forms the N channel transistor, and inject p type impurity in the zone that is used to form p channel transistor.Then, cover Etching mask, and inject N type impurity, thereafter, P type silicon fiml and N type silicon fiml composition are formed the gate electrode shape in the zone that forms the N channel transistor in the zone that forms p channel transistor.
Therefore, can use the method for two types of the following stated to form trench-gate transistors in the memory cell district, form double-gated transistor at peripheral circuit region.Use Figure 21 to Figure 27 that these two kinds of methods are illustrated.In Figure 21 to Figure 27, the described memory cell of " M district " indication district, " P district " and " N district " is provided at peripheral circuit region, wherein, " P district " is meant the zone that forms p channel transistor, and " N district " is meant the zone that forms the N channel transistor, wherein, described p channel transistor has the gate electrode that comprises P type polysilicon, and described N channel transistor has the gate electrode that comprises N type polysilicon.
Figure 21 to Figure 24 is in order to explanation first method (hereinafter referring to do first conventional method).
As shown in figure 21, at first form gate groove 202 in the M district of Semiconductor substrate 200, be to isolate between each district of Semiconductor substrate 200 wherein, then, on the whole surface that has comprised gate groove 202 inwalls, form gate insulating film 203 by STI (shallow trench isolation from) 201.Then, on the whole surface that has comprised gate groove inside, form non-doping silicon fiml 204, as shown in figure 22.As shown in figure 23, cover M district and N district, p type impurity (for example boron) is injected into the P district, remove Etching mask 205 then by the ion injection by Etching mask 205.Subsequently, the P district covers Etching mask 206, injects by ion N type impurity (for example phosphorus) is injected M district and N district, as shown in figure 24.Then that each is regional silicon fiml 204 compositions form the shape of gate electrode.
Yet, in described first conventional method, i.e. technology as shown in figure 24, when the thickness (degree of depth) according to the silicon fiml 204 in the N district carries out the ion injection, the silicon fiml 204 of gate groove 202 inside can not carry out the doping of N type ion fully, described trench gate electrode becomes and exhausts, and then makes and can not embody sufficient performance in the memory cell transistor.Opposite, when injecting N type impurity, this impurity can't be introduced the silicon fiml 204 in N district with suitable concentration, and this impurity can be introduced within the silicon substrate 200 that has formed channel region and source/drain region in it according to the deep ion of gate groove 202.Therefore, can be to the transistorized work generation reaction of formation in the memory cell transistor that forms in the M district and the N district.
All this methods as described below of other method (hereinafter being called second conventional method) can be used for preventing the variety of issue that occurs in described first conventional method.
As shown in figure 21, in an identical manner, at first form gate groove 202 and gate insulating film 203, then, as shown in figure 25, on the whole surface of the inside that has comprised gate groove 202, form doping silicon fiml (doping silicon fiml) 304a.Then, as shown in figure 26, whole surface is eat-back only to stay the doping silicon fiml 304a in the gate groove 202.Subsequently, form non-doping silicon fiml 304b, as shown in figure 27, then,, impurity is injected into non-doping silicon fiml 304b by the ion injection with the same way as shown in Figure 23 and 24 on whole surface.
According to this method, doping silicon fiml 304a is embedded gate groove 202, and then solved the problem that trench gate electrode exhausts.Shown in Figure 23 and 24, when in the same manner impurity being carried out ion when injecting, can also inject, and can avoid that ion is incorporated into silicon and claim the end 200 according to the suitable ion that carries out of the thickness of non-doping silicon fiml 304b.
But the problem that occurs in second kind of conventional method is different from first kind of problem in the conventional method again.Particularly, whole surface is eat-back to cause the impaired of gate insulating film 203 as shown in figure 26.Must heat-treat with oxidation technology to repair the impaired of described gate insulating film 203.Therefore after shown in Figure 26 eat-backing at surface and then the formation high resistance film of doping silicon fiml 304a.Because between described doping silicon fiml 304a and non-doping silicon fiml 304b, there is the interference of high resistance film, so gate resistance increases.
Summary of the invention
Exploitation the invention is intended to overcome the above problems, the method that the purpose of this invention is to provide a kind of semiconductor device and be used for producing the semiconductor devices, wherein when forming trench-gate transistors and double-gated transistor on semi-conductive substrate, two kinds of devices all can have high-performance.
Can realize above-mentioned and other purposes of the present invention by the method that is used for producing the semiconductor devices, this method comprises:
The first step forms first grid dielectric film in memory cell district and peripheral circuit region, and first conductivity type of transistor that wherein said peripheral circuit region possesses Semiconductor substrate forms district and second conductivity type of transistor formation district;
In second step, on described first grid dielectric film, form diaphragm;
The 3rd step formed the mask layer that has opening, and its split shed is used to form gate groove;
In the 4th step, use described mask layer in the described memory cell district of described Semiconductor substrate, to form gate groove;
In the 5th step, form second gate insulating film at the inwall of described gate groove;
In the 6th step, in described gate groove, form first silicon fiml that mixes with second conductive type impurity;
In the 7th step, remove described mask layer;
In the 8th step, on described diaphragm and described first silicon fiml, form non-doping second silicon fiml;
In the 9th step, described first conductivity type of transistor that optionally first conductive type impurity is introduced in described peripheral circuit region forms described second silicon fiml in the district;
In the tenth step, described second conductivity type of transistor that optionally second conductive type impurity is introduced in described peripheral circuit region forms described second silicon fiml in the district;
In the 11 step, described second silicon fiml of composition and described diaphragm form the first grid electrode that comprises described second silicon fiml, have introduced first conductive type impurity in wherein said second silicon fiml; And form second gate electrode that comprises described second silicon fiml, introduced second conductive type impurity in wherein said second silicon fiml.
The film of any kind all can be used as diaphragm, if the transistorized work of this film (for example conductive film or other similar films) described first and second conduction types of not overslaugh, but the non-doping silicon fiml of preferred use.And then impurity is introduced described diaphragm is non-doping silicon fiml, and when impurity being introduced non-doping second silicon fiml, impels the layered membrane that comprises the described diaphragm and second silicon fiml to use as gate electrode.
Above-mentioned and other purposes of the present invention can also be achieved by a kind of semiconductor device, and this semiconductor device comprises:
Semiconductor substrate, it possesses memory cell district, P type peripheral circuit region and N type peripheral circuit region;
Be formed at the trench-gate transistors in described memory cell district;
Be prepared in plane P channel transistor in the described P type peripheral circuit region and that have P type gate electrode, wherein said P type gate electrode includes on described Semiconductor substrate by the formed P type of first grid dielectric film polysilicon; And
Be prepared in plane N channel transistor in the described N type peripheral circuit region and that have N type gate electrode, wherein said N type gate electrode includes on described Semiconductor substrate by the formed N type of first grid dielectric film polysilicon; Wherein
Described P type gate electrode comprises: described conductive film, and on described conductive film formed second silicon fiml; And
The gate electrode of described trench-gate transistors comprises: formed second gate insulating film on the inwall for the gate groove that described Semiconductor substrate provided; In described gate groove, pass through formed the 3rd silicon fiml of described second gate insulating film.
According to the present invention, after in gate groove, forming first silicon fiml that mixed, remove when being used to form the mask of gate groove, by first dielectric film of described peripheral circuit region being protected by non-doping silicon fiml or the made diaphragm (conductive film) of other films.Therefore can avoid damage to first grid dielectric film, and first silicon fiml that mixes can be embedded described gate groove, to form second silicon fiml with non-dopant states earlier at described peripheral circuit region, this second silicon fiml is as the silicon fiml that forms gate electrode, and then the doping of carrying out every type of impurity is to form the silicon fiml of every kind of conduction type.Therefore, when promptly box lunch prepares trench-gate transistors simultaneously and has the transistor of double-gate structure on semi-conductive substrate, also can obtain this two kinds of transistorized high-performance.
Description of drawings
By with reference to the following detailed description of in conjunction with the accompanying drawings the present invention being carried out, above and other purposes of the present invention, feature and advantage can be more apparent, wherein:
Fig. 1 is the artwork that shows the technology that forms thin oxide film and thick oxide film, and this technology is the part of the manufacture method of described semiconductor device according to a preferred embodiment of the invention;
Fig. 2 is the artwork that shows the technology that forms non-doped amorphous silicon and silicon nitride film, and this technology is the part of the manufacture method of described semiconductor device according to a preferred embodiment of the invention;
Fig. 3 is the artwork that shows the technology that forms the resist figure, and this technology is the part of the manufacture method of described semiconductor device according to a preferred embodiment of the invention;
Fig. 4 is the artwork that shows the technology of the groove that is formed for STI, and this technology is the part of the manufacture method of described semiconductor device according to a preferred embodiment of the invention;
Fig. 5 is the artwork that shows the technology that forms silicon oxide film, and this technology is the part of the manufacture method of described semiconductor device according to a preferred embodiment of the invention;
Fig. 6 is the artwork that shows the technology that forms element isolation zone, and this technology is the part of the manufacture method of described semiconductor device according to a preferred embodiment of the invention;
Fig. 7 is the artwork that shows the technology that forms the resist figure, and this technology is the part of the manufacture method of described semiconductor device according to a preferred embodiment of the invention;
Fig. 8 is the artwork that shows the technology of composition silicon nitride film, and this technology is the part of the manufacture method of described semiconductor device according to a preferred embodiment of the invention;
Fig. 9 is the artwork that shows the technology that forms gate groove, and this technology is the part of the manufacture method of described semiconductor device according to a preferred embodiment of the invention;
Figure 10 is the artwork that shows the technology that forms silicon oxide film, and this technology is the part of the manufacture method of described semiconductor device according to a preferred embodiment of the invention;
Figure 11 is presented at the artwork that forms the technology of phosphorus-doped amorphous silicon fiml in the gate groove, and this technology is the part of the manufacture method of described semiconductor device according to a preferred embodiment of the invention;
Figure 12 is the artwork that shows the technology that described phosphorus-doped amorphous silicon fiml is eat-back, and this technology is the part of the manufacture method of described semiconductor device according to a preferred embodiment of the invention;
Figure 13 is the artwork of technology that show to remove the top of the top of described silicon nitride film, element isolation zone and silicon oxide film, and this technology is the part of the manufacture method of described semiconductor device according to a preferred embodiment of the invention;
Figure 14 is the artwork that shows the technology that forms non-doped amorphous silicon film, and this technology is the part of the manufacture method of described semiconductor device according to a preferred embodiment of the invention;
Figure 15 is the artwork that shows the technology of injecting the boron ion, and this technology is the part of the manufacture method of described semiconductor device according to a preferred embodiment of the invention;
Figure 16 is the artwork that shows the technology of injecting phosphonium ion, and this technology is the part of the manufacture method of described semiconductor device according to a preferred embodiment of the invention;
Figure 17 is the artwork that shows the technology that forms the resist figure, and this technology is the part of the manufacture method of described semiconductor device according to a preferred embodiment of the invention;
Figure 18 shows the artwork that layered membrane is carried out the technology of composition, and this technology is the part of the manufacture method of described semiconductor device according to a preferred embodiment of the invention;
Figure 19 is the artwork that shows the technology of formation source/leakage diffusion region, and this technology is the part of the manufacture method of described semiconductor device according to a preferred embodiment of the invention;
Figure 20 is the artwork that shows the technology that forms various line figures and cell capacitance, and this technology is the part of the manufacture method of described semiconductor device according to a preferred embodiment of the invention;
Figure 21 is the artwork that shows the technology that forms STI, gate groove and gate insulating film, and this technology is the part of first conventional method;
Figure 22 is the artwork that shows the technology that forms non-doping silicon fiml, and this technology is the part of first conventional method;
Figure 23 is the artwork that shows the technology of injecting the boron ion, and this technology is the part of first conventional method;
Figure 24 is the artwork that shows the technology of injecting phosphonium ion, and this technology is the part of first conventional method;
Figure 25 is the artwork that shows the technology that forms the doping silicon fiml, and this technology is the part of second conventional method;
Figure 26 is the artwork that shows the technology that described doping silicon fiml is eat-back, and this technology is the part of second conventional method;
Figure 27 is the artwork that shows the technology that forms non-doping silicon fiml, and this technology is the part of second conventional method; And
Figure 28 shows the profile of modified example according to the preferred embodiment of the invention.
Embodiment
Describe the preferred embodiments of the present invention in detail below with reference to accompanying drawing.
Fig. 1 to 20 shows that according to embodiment of the invention manufacturing possesses the schematic diagram of technology of the semiconductor device of double-gate structure transistor and trench-gate transistors.In Fig. 1 to 20, " M district " instruction memory cellular zone, form trench-gate transistors in it, " P district " and " N district " is provided in peripheral circuit, wherein " P district " is the zone (being also referred to as P type peripheral circuit region) that has the plane P channel transistor of gate electrode in it in order to formation, and described gate electrode comprises P type polysilicon, and wherein " N district " is the zone (being also referred to as N type peripheral circuit region) that has the plane N channel transistor of gate electrode in it in order to formation, and described gate electrode comprises N type polysilicon.
At first, as shown in Figure 1, on the surface in the P district of Semiconductor substrate 100 and N district, form thin oxide film 101s with about thickness of 1.5 to 3nm.Beyond the P district of described peripheral circuit region and N district and in it in order to forming a certain regional (not shown) of power circuit etc., and formation possesses the thick oxide film 101t of about 4.5nm to 6nm thickness within the M district.In concrete example, on the whole surface of Semiconductor substrate 100, form the heat oxide film that thickness is slightly less than 6nm by thermal oxidation, cover Etching mask in other zones that do not comprise P district and N district then, remove the heat oxide film in P district and the N district then, subsequently, remove Etching mask, and then clean the whole surface of substrate 100 with acid.This cleaning step with in the M district and the described district that forms power circuit etc. in it on the surface of a part of heat oxide film remove, make the thickness of this heat oxide film reduce to about 5nm.Then, the whole surface of thermal oxidation once more, forming the thin oxide film 101s of about 3nm thickness in P district and N district, and formation possesses the thick oxide film 101t of about 6nm thickness in M district and on the described district's (not shown) that forms power circuit etc. in it.
The reason of oxide-film that formation possesses different-thickness is as follows.At first, the transistor that forms in P district and N district needs thin gate insulating film so that under low pressure work, and therefore described thin oxide film 101s is used as gate insulating film.In the memory cell transistor that in the M district, forms, adopt booster voltage, and described power circuit also needs to possess the gate insulating film of high-tension resistive, make the transistor of the required high pressure of memory cell operation also need to apply high pressure owing to be used to produce.Therefore form thick oxide film 101t as these gate insulating films.
In step subsequently shown in Figure 2, form by CVD (chemical vapor deposition) method and to possess the non-doped amorphous silicon film 102 that is approximately 10 to 30nm thickness, so that protect described thin oxide film 101s as diaphragm.Form the silicon nitride film 103 that possesses about 80 to 150nm thickness by LP (low pressure)-CVD method then.
As shown in Figure 3, according to STI (shallow trench isolation from) technology, on each element isolation zone, form resist figure 104 as the zone of isolated component.
As shown in Figure 4, after using described resist figure 104 described silicon nitride film 103 to be carried out composition as mask, remove described resist figure 104, use the silicon nitride film 103 of composition described non-doped amorphous silicon film 102, thick oxide film 101t, thin oxide film 101s and Semiconductor substrate 100 to be carried out dry etching as mask.Non-doped amorphous silicon film 102, thick oxide film 101t and thin oxide film 101s are therefore patterned, and the described groove 105 that is used for STI forms in Semiconductor substrate 100.
Carry out thermal oxidation then,, afterwards, as shown in Figure 5, form silicon oxide film 106 by HDP (high-density plasma)-CVD method on described whole surface, with filling groove 105 so that remove the etching injury of the inwall of described groove 105.
Then, use silicon nitride film 103 to carry out CMP (chemical machinery cuts open light), by cuing open the silicon oxide film 106 of light removal on described silicon nitride film 103, so that in groove 105, keep described silicon oxide film 106 as stopping layer (stopper).As shown in Figure 6, therefore form element isolation zone 106i.
As shown in Figure 7, form the resist figure 107 that has a plurality of openings in the M district, so that form the gate groove of described trench gate memory cell transistor in the M district.Specifically, by resist figure 107 P district and N district are all covered.In the resist figure 107 on the element isolation zone 106i in M district, form opening, so that be used for gate groove in the memory cell district (not shown) formation that closes on.
Use resist figure 107 as mask, as shown in Figure 8, with the shape composition silicon nitride film 103 of this mask.
After removing described resist figure 107, as shown in Figure 9, described non-doped amorphous silicon film 102 and thick oxide film 101t are carried out etching, and Semiconductor substrate 100 is carried out etching, thereby in Semiconductor substrate 100, form gate groove 108.Be used as mask among Fig. 4 and need not to be removed in order to the described silicon nitride film 103 that forms the sti trench groove and kept, and be used as mask and be used to form described gate groove 108, as shown in Figure 9.
Carry out sacrificial oxidation by thermal oxidation then, removing the damage and the pollution of the etching surface in the described gate groove 108, and remove sacrificial oxidation film by wet etching.As shown in figure 10, form silicon oxide film 109 with gate insulating film as described memory cell transistor.As mentioned above, this silicon oxide film 109 must also possess high-tension resistive, and preferably possesses about thickness of 4.5 to 7.5nm.
Preferably form silicon oxide film 109 here by following technology, promptly, under about 800 ℃ temperature, be approximately the CVD oxide-film (preferably HTO (high-temperature oxide)) of 3.5nm to 5.5nm by CVD method deposition thickness, after this, under about 1050 ℃ of ground temperature, described CVD oxide-film is carried out thermal oxidation, so that described CVD oxide-film is encrypted, remove impurity, and between described CVD oxide-film and the Semiconductor substrate 100 the interface modify.The gate insulating film 109 that in described gate groove 108, forms thereby become layered membrane, this layered membrane comprises the CVD silicon oxide film 109v that forms by the CVD method, and the thickness that forms in the interface between described Semiconductor substrate 100 and CVD silicon oxide film 109v is approximately 1.0 to 2.0nm heat oxide film 109h.Because CVD silicon oxide film 109v also can react in above-mentioned thermal oxidation with the silicon fiml 102 that is exposed to the inwall of described gate groove, thus on the side surface of silicon fiml 102, also can form heat oxide film 109h, as shown in the figure.
When forming the whole gate insulating film of memory cell transistor by thermal oxidation, oxide species can diffuse in the interface of Semiconductor substrate 100 and established element isolation zone 106i.This oxide species that diffuses into can cause Semiconductor substrate 100 oxidations.The result causes, and constitutes the deposit expansion of the silicon oxide layer of described element isolation zone 106i, stress occurs in the Semiconductor substrate 100, and the junction characteristic of described DRAM worsens.As mentioned above, in the present invention, the CVD silicon oxide film 109v that forms by the CVD method is as main gate insulating film, therefore can be with minimise stress, and avoid the deterioration of junction characteristic.
For forming the gate electrode of trench-gate transistors, on the whole surface of the inside that has comprised described gate groove 108, form amorphous silicon film, Doping Phosphorus is as N type impurity in this amorphous silicon film.As shown in figure 11, carry out flatening process as the CMP method that stops layer, thereby the described amorphous silicon film 110 of mixing phosphorus is embedded in the described gate groove 108 by using silicon nitride film 103.
As shown in figure 12, the phosphorus-doped amorphous silicon fimls 110 in the gate groove 108 are eat-back, until with the about identical position of thick oxide film 101t by dry etching.
Carry out wet etching then with the top of removing described silicon nitride film 103, element isolation zone 106i and the top of silicon oxide film 109.As shown in figure 13, therefore the upper surface of element isolation zone 106i and described diaphragm (non-doped amorphous silicon film) 102 be aligned with each other.
In the same manner, in the gate groove 108 in M district, form the amorphous silicon film 110 of selective doping.Therefore can avoid exhausting of trench gate electrode.According to the present invention; on the gate insulating film 101s in P district and N district, form non-doped amorphous silicon film 102; and this film remove silicon nitride film 103 during as diaphragm, wherein said silicon nitride film 103 (seeing Figure 12) when being used to form gate groove 108 as mask.Therefore can avoid damaging gate insulating film 101s.
As shown in figure 14, use the CVD method, form the non-doped amorphous silicon film 111 that thickness is approximately 30nm to 80nm, to become described double-gated transistor gate electrode.
As shown in figure 15, carry out mask, boron (B) is injected into into P district as p type impurity by the ion injection by 112 pairs of M districts of resist figure and N district.This boron ion is infused in 10keV or lower carries out under low-yield.In the heat treatment of carrying out subsequently, the boron ions diffusion of described injection, thereby the non-doped amorphous silicon film 111 in described P district and 102 (seeing Figure 14) become P type amorphous silicon film 111p and 102p.
After removing resist figure 112, P district in this case carries out mask by resist figure 113, and injects phosphorus (P) as N type impurity injection N district and M district, as shown in figure 16 by ion.This phosphonium ion injects also will be 20keV or lower low-yieldly carry out down, injects identically with above-mentioned boron ion, spreads by the described phosphonium ion of heat treatment subsequently.The non-doped amorphous silicon film 111 in N district and 102 (seeing Figure 15) thereby become N type amorphous silicon film 111n and 102n.Inject by ion, the non-doped amorphous silicon film 111 and 102 in M district also becomes N type amorphous silicon film 111n and 102n.
According to the present invention, mix the gate groove 108 that the phosphorus silicon fiml has embedded described M district.Be used to make P type and the non-doping silicon fiml 111 of N type (promptly; the gate electrode of double-gated transistor) in the ion implantation technology; when when the phosphonium ion that carries out the N district injects, carrying out the ion injection in M district; can under suitable injection condition, carry out ion according to the thickness of silicon fiml 111 silicon fiml 102 of diaphragm (and as) and inject, and need not consider injection gate groove 108.
As shown in figure 17, preparing the resist figure 114 that is used to form gate electrode on doped amorphous silicon film 111n and the 111p.
As shown in figure 18, by using resist figure 114 as mask, to comprising the layered membrane of amorphous silicon film 111p and 102p, and the layered membrane that comprises amorphous silicon film 111n and 102n, carry out composition respectively.Therefore, form the gate electrode of the trench-gate transistors of being formed by doped amorphous silicon film 110 and 111n in the M district, form the P type gate electrode of being formed by doped amorphous silicon film 111p and 102p in the P district, form the N type gate electrode of being formed by doped amorphous silicon film 111n and 102n in the N district.
Said example is following situation, i.e. the wherein amorphous silicon film 111n behind the composition and gate groove 108 misalignments in M district.Yet when misalignment occurring, amorphous silicon film 111n and amorphous silicon film 102 still are retained on the thick oxide film 101t, and become the part of gate electrode.Under the situation of the type, described thick oxide film 101t is as the part of gate insulating film in this trench-gate transistors.Yet, to such an extent as to owing in gate insulating film, form oxide-film 101t and possess and described silicon oxide film 109 essentially identical thickness, on the puncture voltage reduction can be minimized.
As shown in figure 19, cover M district and N district, use P type gate electrode, inject by ion p type impurity is injected P district formation P type source/leakage diffusion region 115p as mask with the resist film (not shown).Cover the P district with the resist film (not shown), the gate electrode that uses M district and N district injects N type impurity injection M district and N district by ion as mask.Subsequently, form N type source/leakage diffusion region 115n in the N district, form N type source/leakage diffusion region 116 in the M district.According to this technology, form the trench gate memory cell transistor in the M district, be that peripheral circuit region forms double-gated transistor in P district and M district.
By in order to the heat treatment that activation source/the leakage diffusion region is carried out, perhaps the heating process by carrying out subsequently is converted into polysilicon film with described amorphous silicon film 111n, 111p, 102p, 102n and 110 from amorphous silicon film.
Use various types of lines and the cell capacitance of commonsense method in can stratification M district.Particularly, the DRAM that possesses trench gate memory block cell transistor can form by following technology: form interlayer dielectric (interlayer insulatingfilm) 117 on described memory cell transistor, form connecting hole bolt 118, bit line 119, cell capacitance 120, aluminium line 121 and miscellaneous part then, as shown in figure 20 by described interlayer dielectric 117.
According to embodiments of the invention as mentioned above; on described gate insulating film (thin oxide film) 101s, under described silicon nitride film 103, provide diaphragm 102 in advance; wherein said silicon nitride film 103 when being used to form gate groove 108 as mask layer; and, in described P type peripheral circuit region and N type peripheral circuit region, form gate groove 108.Need not to remove mask layer 103 then and form doped amorphous silicon film 110 in gate groove 108, the mask layer 103 that will be used to form gate groove 108 is then removed.Owing to after gate groove 108 is embedded in and forms described doped amorphous silicon film 110, just remove described mask layer 103, so can avoid damage by the diaphragm that provides in advance to gate insulating film 101s.Therefore, can in gate groove 108, form doped amorphous silicon film 110, and at P type peripheral circuit region, N type peripheral circuit region and be embedded into and form non-doped amorphous silicon film 111 on the doped amorphous silicon film 110 of gate groove.Can under the situation that thin oxide film is not being had damage, form described silicon fiml 110,111 and 102, and trench-gate transistors and double-gate structure transistor can all keep high-performance with suitable impurity concentration.
The present invention is not restricted to the foregoing description, and may make various modifications in the scope of the present invention that claims are stated, natural, these modifications all are contained in the scope of the present invention.
For example, in the above-described embodiments, use non-doped amorphous silicon film as diaphragm 102.Yet this configuration is not restrictive, as long as another kind of material can protect described gate insulating film injury-free and can form the film that does not hinder transistor work when removing mask, so can use this material yet.Particularly, can adopt another kind of material exactly as long as it can form film (conductive film etc.), wherein this film can form required raceway groove when applying voltage to gate electrode.
In the above-described embodiments, described such example, that is, each silicon fiml all is that the heating process that forms then by subsequently with the amorphous silicon attitude earlier is converted into polysilicon film.Yet, if desired, also can use polysilicon film at the very start.
Not only to use silicon fiml to form described gate electrode, can on silicon fiml, form silicide film yet, perhaps prepare a kind of so-called many metal gate electrodes by the stratification metal film.What Figure 28 showed is that gate electrode is the example of many metal gate electrodes, and corresponding to technology shown in Figure 19 in the foregoing description.As shown in figure 28, with metal film 122 stratification on the silicon fiml 110 in M district, and on each silicon fiml 111p in P district and N district and 111n stratification metal film 122 respectively.When being formed when described gate electrode and then by many metal gate electrodes, need carry out ion to the silicon fiml 111 in P district and N district injects, so that before forming metal film 122, the silicon fiml 111 in P district is converted into P type silicon fiml 111p, and the silicon fiml 111 that N goes is converted into N type silicon fiml 111n.
Further, above-mentioned example is following situation, and the mask layer that promptly wherein is used to form the mask layer (described groove 105 is used to STI) of groove 105 and is used to form gate groove 108 is shared in described silicon nitride film 103.Yet, after described STI (element isolation zone) 106i forms, can remove described silicon nitride film 103, and can prepare new silicon nitride film to form mask layer.
Claims (19)
1. method that is used for producing the semiconductor devices, this method comprises:
The first step forms first grid dielectric film in memory cell district and peripheral circuit region, and first conductivity type of transistor that wherein said peripheral circuit region possesses Semiconductor substrate forms district and second conductivity type of transistor formation district;
In second step, on described first grid dielectric film, form diaphragm;
In the 3rd step, form the mask layer that has the opening that is used to form gate groove;
In the 4th step, use described mask layer in the described memory cell district of described Semiconductor substrate, to form gate groove;
In the 5th step, form second gate insulating film at the inwall of described gate groove;
In the 6th step, in described gate groove, form first silicon fiml that mixes with second conductive type impurity;
In the 7th step, remove described mask layer;
In the 8th step, on described diaphragm and described first silicon fiml, form non-doping second silicon fiml;
In the 9th step, described first conductivity type of transistor that optionally first conductive type impurity is introduced in described peripheral circuit region forms described second silicon fiml in the district;
In the tenth step, described second conductivity type of transistor that optionally second conductive type impurity is introduced in described peripheral circuit region forms described second silicon fiml in the district;
In the 11 step, described second silicon fiml of composition and described diaphragm form first grid electrode, and described first grid electrode comprises described second silicon fiml of wherein having introduced first conductive type impurity; And forming second gate electrode, described second gate electrode comprises second silicon fiml of wherein having introduced second conductive type impurity.
2. according to the described method that is used for producing the semiconductor devices of claim 1, wherein,
Described diaphragm is non-doping silicon fiml;
In described the 9th step, also described first conductive type impurity is introduced in the described diaphragm in described first conductivity type of transistor formation district; And
In described the tenth step, also described second conductive type impurity is introduced in the described diaphragm in described second conductivity type of transistor formation district.
3. according to the described method that is used for producing the semiconductor devices of claim 1, wherein,, also described second conductive type impurity synchronously is introduced in described second silicon fiml in the described memory cell district in described the tenth step.
4. according to the described method that is used for producing the semiconductor devices of claim 3, wherein,
In described the 11 step, second silicon fiml in the described memory cell district is patterned into electrode shape, so that be connected to described first silicon fiml, and form trench gate electrode, wherein this trench gate electrode comprises described first silicon fiml and with described second silicon fiml of described electrode shape composition.
5. according to arbitrary described method that is used for producing the semiconductor devices among the claim 1 to 4, wherein, described second gate insulating film is than described first grid insulation thickness.
6. according to arbitrary described method that is used for producing the semiconductor devices among the claim 1 to 4, wherein, the thickness of the described first grid dielectric film in the described memory cell district is greater than the thickness of the described first grid dielectric film on the described peripheral circuit region.
7. according to arbitrary described method that is used for producing the semiconductor devices among the claim 1 to 4, wherein, after described the 6th step and before described the 7th step, cut open light so that described first silicon fiml is removed as stopping layer by using described mask.
8. according to arbitrary described method that is used for producing the semiconductor devices among the claim 1 to 4, wherein after the described first step, form element isolation zone, this element isolation zone is used for insulating and isolating each district that described first conductivity type of transistor forms district, described second conductivity type of transistor formation district and described memory cell district.
9. the described according to Claim 8 method that is used for producing the semiconductor devices, wherein,
Described element isolation zone possesses sti structure; And
In described mask layer, be formed for forming before the described opening of gate groove, described mask layer be used as the mask of the groove of described element isolation zone as formation.
10. according to arbitrary described method that is used for producing the semiconductor devices among the claim 1 to 4, wherein, described the 5th step comprises:
Step by CVD method silicon oxide deposition film;
The step that thermal oxidation is carried out at interface between described silicon oxide film and the described Semiconductor substrate.
11. a method that is used for producing the semiconductor devices, described semiconductor device comprise memory cell district, P type peripheral circuit region and N type peripheral circuit region; The described method that is used for producing the semiconductor devices comprises:
The first step forms gate groove with following state in described memory cell district, described state is meant that first grid dielectric film and diaphragm all cover described P type peripheral circuit region and Semiconductor substrate described N type peripheral circuit region;
In second step, on the inwall at least of described gate groove, form second gate insulating film;
In the 3rd step, at least a portion of described gate groove is filled by first silicon fiml that has mixed;
In the 4th step, on described diaphragm, form second silicon fiml; And
In the 5th step, respectively p type impurity and N type impurity are introduced in described second silicon fiml that forms on described P type peripheral circuit region and the described N type peripheral circuit region.
12. according to the described method that is used for producing the semiconductor devices of claim 11; wherein; the described first step comprises: after forming described first grid dielectric film and described diaphragm and before forming described gate groove; form element isolation zone, each district that described element isolation zone is used for insulation and isolates described memory cell district, described P type peripheral circuit region and described N type peripheral circuit region.
13. a semiconductor device comprises:
Semiconductor substrate, it possesses memory cell district, P type peripheral circuit region and N type peripheral circuit region;
The trench-gate transistors that in described memory cell district, forms;
Be arranged at plane P channel transistor in the described P type peripheral circuit region and that have P type gate electrode, wherein said P type gate electrode is included on the described Semiconductor substrate by the formed P type of first grid dielectric film polysilicon; And
Be arranged at plane N channel transistor in the described N type peripheral circuit region and that have N type gate electrode, wherein said N type gate electrode is included on the described Semiconductor substrate by the formed N type of first grid dielectric film polysilicon; Wherein
Described P type gate electrode comprises conductive film and first silicon fiml that forms on described conductive film;
Described N type gate electrode comprises described conductive film and second silicon fiml that forms on described conductive film; And
The gate electrode of described trench-gate transistors comprises: formed second gate insulating film to the inwall of the gate groove of described Semiconductor substrate is being provided, and in described gate groove by formed the 3rd silicon fiml of described second gate insulating film.
14. according to the described semiconductor device of claim 13, the thickness of wherein said second gate insulating film is greater than the thickness of described first grid dielectric film.
15. according to claim 13 or 14 described semiconductor device, wherein, described second gate insulating film comprises the CVD silicon oxide film and formed heat oxide film below described CVD silicon oxide film.
16. according to claim 13 or 14 described semiconductor device, wherein said conductive film is a silicon fiml.
17. according to claim 13 or 14 described semiconductor device, wherein,
The gate electrode of described trench-gate transistors further is included in the 4th silicon fiml of deposit on described the 3rd silicon fiml;
Described the 3rd silicon fiml is the doping silicon fiml; And
By the ion injection impurity is injected into non-doping silicon fiml, thereby obtain described the 4th silicon fiml.
18. according to claim 13 or 14 described semiconductor device, wherein,
The gate electrode of described trench-gate transistors further is included in institute's metals deposited film on described the 3rd silicon fiml;
Described P type gate electrode further is included in the described metal film of stratification on described first silicon fiml; And
Described N type gate electrode further is included in the described metal film of stratification on described second silicon fiml.
19., wherein, obtain described first silicon fiml and described second silicon fiml thereby impurity is injected into non-doping silicon fiml by the ion injection according to claim 13 or 14 described semiconductor device.
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