CN100454519C - Semiconductor device and manufacturing method thereof - Google Patents

Semiconductor device and manufacturing method thereof Download PDF

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CN100454519C
CN100454519C CN 200610132138 CN200610132138A CN100454519C CN 100454519 C CN100454519 C CN 100454519C CN 200610132138 CN200610132138 CN 200610132138 CN 200610132138 A CN200610132138 A CN 200610132138A CN 100454519 C CN100454519 C CN 100454519C
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semiconductor device
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CN1949481A (en )
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白竹茂
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尔必达存储器株式会社
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Abstract

通过使用氮化硅膜103作为掩模在存储器单元区M内以以下状态形成栅沟槽108,所述状态是指通过栅绝缘膜101s、保护膜102以及氮化硅膜103覆盖P型外围电路P区中的和N型外围电路N区中的半导体衬底100。 By using the silicon nitride film 103 as a mask to form a gate trench 108 in a state in the memory cell region M, the state is through the gate insulating film 101s, the protective film 102 and the silicon nitride film 103 covering the P-type peripheral circuit N and N-type peripheral circuit region of the semiconductor substrate 100 P region. 然后在所述栅沟槽108的内壁上形成栅绝缘膜109,并将包含有N型杂质的硅膜110嵌入所述栅沟槽108。 The gate insulating film 109 is then formed on the inner wall of the trench gate 108, and an N-type impurity comprises silicon film 110 embedded in the gate trench 108. 然后去除所述氮化硅膜103,在整个表面上形成非掺杂硅膜,在此之后,将P型杂质引入P区上的非掺杂硅膜内,并将N型杂质引入M区和N区上的非掺杂硅膜内。 The silicon nitride film 103 is then removed, forming a non-doped silicon film on the entire surface, after which the P-type impurity introduced into the non-doped silicon film on the P region, and introducing N-type impurity region and M a non-doped silicon film on the N region.

Description

半导体器件及其制造方法 Semiconductor device and manufacturing method thereof

技术领域 FIELD

本发明涉及一种半导体器件及其制造方法,具体而言,涉及一种具备沟槽栅晶体管和双栅晶体管的半导体器件及其制造方法。 The present invention relates to a semiconductor device and a manufacturing method, particularly, to a semiconductor device and a manufacturing method of the trench gate transistor and includes a dual-gate transistor.

背景技术 Background technique

近年来DRAM (动态随机存取存储器)单元的小型化总是必然伴随着縮短存储器单元晶体管的栅长。 In recent years, a DRAM (Dynamic Random Access Memory) is always small unit must be accompanied by shortening gate length of the memory cell transistor. 然而,随着栅长的縮短,晶体管中的短沟道效应愈加严重,并且会出现亚阈值电流增加的问题。 However, as the gate length is shortened, the short channel effect transistors become increasingly serious, and the sub-threshold current will be increased. 当增加衬底杂质浓度以使短沟道效应最小化时,由于结泄漏的增加导致DRAM中刷新特性的恶化成为严重问题。 When increasing the impurity concentration of the substrate so that short channel effects are minimized, resulting in increased junction leakage due to the deterioration of the refresh characteristic of a DRAM becomes a serious problem.

为解决这些问题,已经着眼于一种所谓的沟槽栅晶体管(也称为凹槽型晶体管),其是指在硅衬底上所形成的槽中嵌入栅电极(参见日本特开No. H9-232535, 2001-210801, 2005-142203, H7掘297,以及2004-014696)。 To solve these problems, focusing on a so-called trench gate transistors (also referred to as a groove-type transistor), which refers to a groove formed on a silicon substrate a gate electrode is embedded (refer to Japanese Patent Laid-Open No. H9 -232535, 2001-210801, 2005-142203, H7 dig 297, and 2004-014696). 采用沟槽栅晶体管,可以在结构上充分地维持有效沟道长度(栅长),并使得制造具备90nm或者更低的最小特征尺寸的精密DRAM成为可能。 Using a trench-gate transistor can be sufficiently maintained effective channel length (gate length) in the structure, makes the manufacturing and 90nm or less have a minimum feature size of the DRAM becomes possible precision.

在DRAM的外围电路区采用具备双栅结构的晶体管已成必然,这样可以使得器件性能获得改进并且其驱动电压得以降低。 A transistor in the peripheral circuit region includes a DRAM using a double gate structure become inevitable, so that the device performance may be improved and the driving voltage is obtained is reduced. 在双栅结构中,由包含有注入了N型杂质(磷或其他)的N型多晶硅的栅电极作为N沟道晶体管的栅电极,由包含有注入了P型杂质(硼或其他)的P型多晶硅的栅电极作为P沟道晶体管的栅电极。 In the double-gate structure, the gate electrode is implanted with N-type impurities (phosphorus or other) of the N-type polysilicon gate electrode of the N-channel transistor, comprising the implanted P-type impurities (boron or other) of P type polysilicon gate electrode as the gate electrode of the P-channel transistor.

但是,.当在单个半导体器件中同时釆用具备上述两种结构的晶体管时,会出现随后所述问题。 However, when Bian simultaneously in a single semiconductor device includes a transistor with the above-described two structures, then the problem will be. 具体而言,当在存储器单元区形成沟槽 Specifically, when the trench is formed in the memory cell region

栅晶体管,而在外围电路区形成双栅晶体管时,会出现随后所述问题。 When the gate transistor, and a double gate transistor formed in the peripheral circuit region, then a problem occurs.

以下首先说明用于形成沟槽栅晶体管的电极和双栅晶体管的电极的通常方法。 First, the following conventional method for forming the electrode trench gate electrode of the transistor and a double gate transistor.

沟槽栅晶体管中的栅电极通过以下过程形成:在半导体衬底内形成槽(栅沟槽),并在该栅沟槽的内壁上形成栅绝缘膜,然后,在栅沟槽内部埋入作为栅电极材料的掺杂硅膜。 The gate electrode trench gate transistor is formed by the following procedure: forming a groove (trench gate) in a semiconductor substrate, and a gate insulating film formed on an inner wall of the gate trench, and then, is buried inside the trench as the gate a doped silicon film as a gate electrode material.

另一方面,通过以下方法形成双栅晶体管的栅电极:在半导体衬底上所形成的栅绝缘膜的上面,形成非掺杂硅膜,然后,在形成N沟道晶体管的区域覆盖抗蚀剂掩模,并在用于形成P沟道晶体管的区域注入P型杂质。 On the other hand, the gate electrode of the double gate transistor is formed by the following method: The above gate insulating film formed on a semiconductor substrate, and forming a non-doped silicon film, and then, in the region forming the N-channel transistor covered with a resist mask, and the P-channel transistor in the region for forming the P-type impurity implantation. 然后,在形成P沟道晶体管的区域覆盖抗蚀剂掩模, Then, the P-channel transistor forming region covered with the resist mask,

并在形成N沟道晶体管的区域注入N型杂质,其后,将P型硅膜和N 型硅膜构图形成栅电极形状。 Region and N-channel transistor formed in an N-type impurity implantation, and thereafter, the P-type silicon film and the N-type silicon film is patterned to form the gate electrode shape.

因此,可以使用以下所述两种类型的方法在存储器单元区形成沟槽栅晶体管,在外围电路区形成双栅晶体管。 Thus, the following two types of methods of forming the trench gate transistor in a memory cell region to form a double gate transistor in the peripheral circuit region. 使用图21至图27对这两种方法予以说明。 Use 21 to 27 be described two methods. 在图21至图27中,"M区"指示所述存储器单元区,在外围电路区提供"P区"和"N区",其中,"P区"是指形成P沟道晶体管的区域,"N区"是指形成N沟道晶体管的区域,其中,所述P 沟道晶体管带有包含P型多晶硅的栅电极,所述N沟道晶体管带有包含N型多晶硅的栅电极。 In FIG 21 to FIG. 27, "M region" indicates that the memory cell area, "area P" and "N region" in the peripheral circuit area, wherein, "P region" means a region formed in P-channel transistor, "N region" means a region formed of N-channel transistor, wherein said P-channel transistor having a gate electrode comprising a P-type polycrystalline silicon, comprising the N-channel transistor having a gate electrode of N-type polysilicon.

图21至图24用以说明第一种方法(下文指作第一常规方法)。 21 to 24 for a first method (hereinafter referred to as a first conventional method) is described.

如图21所示,首先在半导体衬底200的M区形成栅沟槽202,其中半导体衬底200的各区之间是通过STI(浅沟槽隔离)201所隔离的, 然后,在包含了栅沟槽202内壁的整个表面上形成栅绝缘膜203。 21, the first gate trench 202 is formed in the M region of the semiconductor substrate 200, wherein between the zones of the semiconductor substrate 200 by STI (shallow trench isolation) 201 is isolated, and then, the gate comprising the gate insulating film 203 is formed on the entire surface of the inner wall 202 of the trench. 然后, 在包含了栅沟槽内部的整个表面上形成非掺杂硅膜204,如图22所示。 Then, comprising the non-dope silicon film 204 is formed on the entire inner surface of the gate trench, shown in Figure 22.

如图23所示,通过抗蚀剂掩模205覆盖M区和N区,通过离子注入将P型杂质(例如硼)注入到P区,然后去除抗蚀剂掩模205。 23, a resist mask 205 covering the M and N regions, P-type impurity (e.g., boron) implanted into the P region by ion implantation, the resist mask 205 is then removed. 随后, P区覆盖抗蚀剂掩模206,通过离子注入将N型杂质(例如磷)注入M 区和N区,如图24所示。 Subsequently, P - region covered with the resist mask 206, the N-type impurity (e.g., phosphorus) implanted M and N regions by ion implantation, shown in Figure 24. 然后将每个区域的硅膜204构图形成栅电极的形状。 The shape of the gate electrode and the patterned silicon film 204 is formed in each region.

然而,在所述第一常规方法中,即如图24所示工艺,当根据在N 区上的硅膜204的厚度(深度)进行离子注入时,栅沟槽202内部的硅膜204不能够充分地进行N型离子的掺杂,所述沟槽栅电极成为耗尽的,进而使得存储器单元晶体管内不可能体现充分的性能。 However, the first conventional method, i.e. the process shown in FIG. 24, when the ion implantation is performed in accordance with the thickness (depth) on the N-region silicon film 204, the gate trench 202 inside the silicon film 204 can not be sufficiently doped N type ions, the trench gate electrode becomes depleted, thereby making impossible to realize the full memory cell transistors within the performance. 相反的, 当根据栅沟槽202的深度离子注入N型杂质时,无法将该杂质以适当的浓度引入N区的硅膜204,且该杂质会被引入到其内已形成沟道区和源/漏区的硅衬底200之内。 Conversely, when the depth of the implanted N-type impurity ions according to the gate trench 202, the impurities can not be introduced at an appropriate concentration region of N silicon film 204, and the impurity may be introduced into a channel formed therein and a source region within the silicon substrate / drain regions 200. 因此,会对在M区形成的存储器单元晶体管和N区内形成的晶体管的工作产生反作用。 Thus, operation of the transistor of the memory cell transistor formed region and the N-M would be formed in the region counterproductive.

另一方法(下文中称为第二常规方法)诸如以下所述这一方法可以用于防止在所述第一常规方法中出现的各种问题。 Another method (hereinafter referred to as a second conventional method) such that the following method may be used to prevent the various problems in the first conventional method.

如图21所示,以相同的方式,首先形成栅沟槽202和栅绝缘膜203, 然后,如图25所示,在包含了栅沟槽202的内部的整个表面上形成己掺杂质的硅膜(掺杂硅膜)304a。 As shown in FIG 21, in the same manner, the first gate trench 202 and the gate insulating film 203 is formed, and then, as shown in FIG 25 includes the entire surface of the inner gate trench 202 is formed already doped silicon film (doped silicon film) 304a. 然后,如图26所示,对整个表面进行回蚀以仅留下栅沟槽202中的掺杂硅膜304a。 Then, as shown in FIG. 26, the entire surface is etched back to leave only the silicon film doped gate 304a in the grooves 202. 随后,在整个表面形成非掺杂硅膜304b,如图27所示,然后,以图23和24中所示的相同方式,通过离子注入将杂质注入进非掺杂硅膜304b。 Subsequently, the entire surface is formed of non-doped silicon film 304b, as shown in FIG. 27, and then, in the same manner as shown in FIGS. 23 and 24, the impurity is implanted by ion implantation into the non-doped silicon film 304b.

根据该方法,将掺杂硅膜304a嵌入栅沟槽202,进而解决了沟槽栅电极耗尽的问题。 According to this method, doped silicon film 304a embedded in the gate trench 202, thereby solving the problem of depletion of the gate electrode trench. 如图23和24所示,当以相同方式对杂质进行离子注入时,还可以根据非掺杂硅膜304b的厚度适当的进行离子注入, 并可以避免将离子引入到硅称底200。 23 and, when impurities are ion-implanted in the same manner, can also be appropriate depending on the thickness of the ion implantation 304b is a non-doped silicon film 24, and to avoid the ions into said silicon substrate 200.

但是,在第二种常规方法中出现的问题又不同于第一种常规方法 However, problems in the second conventional method is different from the first conventional method

中的问题。 The problem. 具体而言,如图26所示的对整个表面进行回蚀会引起栅绝缘膜203的受损。 Specifically, as to the entire surface 26 shown in etch-back may cause damage to the gate insulating film 203. 必须进行热处理和氧化工艺以修复所述栅绝缘膜203 的受损。 It must be heat and oxidation process to repair damage to the gate insulating film 203. 因此在图26所示的回蚀之后在掺杂硅膜304a的表面进而形成高阻膜。 Therefore, after the etch-back as shown in FIG. 26 in the surface of the doped silicon film 304a is further formed high-resistance film. 因为在所述掺杂硅膜304a和非掺杂硅膜304b之间存在高阻膜的干扰,所以栅电阻增加。 Since the doped and undoped silicon film 304a interference between the high-resistance film is a silicon film 304b, so that the gate resistance increases.

发明内容 SUMMARY

开发本发明意在解决以上问题,本发明的目的是提供一种半导体器件以及用于制造半导体器件的方法,其中当在同一半导体衬底上形成沟槽栅晶体管和双栅晶体管时,两种器件均可具有高性能。 In the development of the present invention is intended to solve the above problems, an object of the present invention is to provide a semiconductor device and a method for manufacturing a semiconductor device, wherein the gate trench is formed when the double gate transistors, and a transistor on the same semiconductor substrate, the two devices You can have high performance.

通过用于制造半导体器件的方法可以实现本发明的上述和其他目 Above and other objects can be achieved according to the present invention by a method for manufacturing a semiconductor device

的,该方法包括: , The method comprising:

第一步,在存储器单元区和外围电路区形成第一栅绝缘膜,其中 First step of forming a first gate insulating film in the memory cell region and the peripheral circuit region, wherein

所述外围电路区具备半导体衬底的第一导电类型晶体管形成区和第二 A first conductivity type region of the peripheral circuit transistor formation region of a semiconductor substrate and a second

导电类型晶体管形成区; Conductivity type transistor formation region;

第二步,在所述第一栅绝缘膜上形成保护膜; A second step of forming a protective film on said first gate insulating film;

第三步,形成带有开口的掩模层,其中开口用于形成栅沟槽; A third step of forming a mask layer having an opening, wherein the opening for forming the gate trench;

第四步,使用所述掩模层在所述半导体衬底的所述存储器单元区 A fourth step, using the mask layer on the semiconductor substrate in the memory cell region

内形成栅沟槽; Forming a gate within the trench;

第五步,在所述栅沟槽的内壁形成第二栅绝缘膜; A fifth step, the second gate insulating film formed on the inner wall of the gate trench;

第六步,在所述栅沟槽内形成以第二导电类型杂质掺杂的第一硅 A sixth step of forming a first silicon doped to a second conductivity type impurity in the gate trench

膜; membrane;

第七步,去除所述掩模层; A seventh step of removing the mask layer;

第八步,在所述保护膜和所述第一硅膜上形成非掺杂第二硅膜; 第九步,选择性的将第一导电类型杂质引入在所述外围电路区的 An eighth step, the protective film and the first silicon film formed in a second non-doped silicon film; ninth step, selectively introducing an impurity of the first conductivity type in said peripheral circuit region

所述第一导电类型晶体管形成区上的所述第二硅膜; Said first conductivity type on said second transistor forming region of the silicon film;

第十步,选择性的将第二导电类型杂质引入在所述外围电路区的 Tenth step, selectively introducing an impurity of the second conductivity type in said peripheral circuit region

所述第二导电类型晶体管形成区上的所述第二硅膜; The second silicon film on the second conductive type transistor formation region;

第十一步,构图所述第二硅膜和所述保护膜,形成包含所述第二硅膜的第一栅电极,其中所述第二硅膜内引入了第一导电类型杂质; 以及形成包含所述第二硅膜的第二栅电极,其中所述第二硅膜内引入了第二导电类型杂质。 A tenth step, patterning the second silicon film and the protective film, a first gate electrode comprises forming the second silicon film, wherein the second silicon film of the first conductivity type impurity is introduced; and forming a second gate electrode comprising the second silicon film, wherein the second silicon film of a second conductivity type impurity is introduced.

任何类型的膜均可以作为保护膜,只要该膜(例如导电薄膜或者其他类似的膜)不防碍所述第一和第二导电类型的晶体管的工作,但是优选使用非掺杂硅膜。 Any type of film can be used as a protective film, so long as the film (e.g. conductive film or a similar film) does not interfere with operation of the first transistor and the second conductivity type, but preferably a non-doped silicon film. 进而将杂质引入所述保护膜即非掺杂硅膜, 并且当将杂质引入非掺杂第二硅膜时,促使包含所述保护膜和第二硅膜的分层膜作为栅电极使用。 Further impurities are introduced to the protective membrane, the non-doped silicon film, and when the second impurities into the silicon film undoped promote layered membrane comprising the protective film and the second silicon film used as a gate electrode.

本发明的上述以及其他目的还可以通过一种半导体器件予以实现,该半导体器件包括: The above and other objects of the present invention can also be achieved by a semiconductor device, the semiconductor device comprising:

半导体衬底,其具备存储器单元区、P型外围电路区、以及N型外围电路区; A semiconductor substrate, which includes a memory cell region, P-type region of the peripheral circuit, the peripheral circuit region and an N-type;

形成于所述存储器单元区的沟槽栅晶体管; It is formed in the memory cell region of a trench gate transistor;

制备于所述P型外围电路区内的并带有P型栅电极的平面P沟道晶体管,其中所述P型栅电极包含有在所述半导体衬底上通过第一栅绝缘膜所形成的P型多晶硅;以及 Prepared in the P-region and the peripheral circuit with a P-type gate electrode of P-channel transistor of the plane, wherein the gate electrode comprises P-type on the semiconductor substrate through a first gate insulating film is formed P-type polycrystalline silicon; and

制备于所述N型外围电路区内的并带有N型栅电极的平面N沟道晶体管,其中所述N型栅电极包含有在所述半导体衬底上通过第一栅 Preparation of N-type in said peripheral circuit region and the N-channel transistor with a planar N-type gate electrode, wherein the gate electrode includes N-type on said semiconductor substrate through a first gate

绝缘膜所形成的N型多晶硅;其中 N-type polysilicon formed on an insulating film; wherein

所述P型栅电极包含:所述导电薄膜,以及在所述导电薄膜上所形成的第二硅膜;以及 The P-type gate electrode comprising: a conductive film and a second silicon film on said conductive film is formed; and

所述沟槽栅晶体管的栅电极包含:在为所述半导体衬底所提供的栅沟槽的内壁上所形成的第二栅绝缘膜;在所述栅沟槽内通过所述第二栅绝缘膜所形成的第三硅膜。 The gate electrode trench gate transistor includes: a second gate insulating film on the inner wall of the gate trench of the semiconductor substrate is provided to be formed; in the second gate trench through the gate insulating third silicon film formed film.

根据本发明,当在栅沟槽内形成已掺杂第一硅膜后,去除用于形成栅沟槽的掩模时,通过由非掺杂硅膜或其他膜所制成的保护膜(导 According to the present invention, after a first gate trench formed in the doped silicon film is removed for forming a gate trench mask, the protective film of a non-doped silicon film or a film made of other (guide

电薄膜)对所述外围电路区的第一绝缘膜进行保护。 Thin film) on a first insulating film of the peripheral circuit region is protected. 因此可以避免对第一栅绝缘膜的损坏,并可以将已掺杂第一硅膜嵌入所述栅沟槽,以在所述外围电路区先以非掺杂状态形成第二硅膜,该第二硅膜作为形成栅电极的硅膜,进而,进行每种类型杂质的掺杂以形成每种导电类型的硅膜。 Thus avoiding damage to the first gate insulating film, and may be doped first silicon film is embedded in the gate trench to the peripheral circuit region to form a second state of non-doped silicon film, the second two silicon film as a gate electrode is formed of a silicon film, in turn, for each type of doping impurity of each conductivity type to form a silicon film. 因此,即便当在同一半导体衬底上同时制备沟槽栅晶体管和具有双栅结构的晶体管时,也可以获得该两种晶体管的高性能。 Therefore, even when preparing a trench gate transistor simultaneously on the same semiconductor substrate and a transistor having the double gate structure, high performance can be obtained of the two kinds of transistors.

附图说明 BRIEF DESCRIPTION

通过参考下面的结合附图对本发明进行的详细说明,本发明的以上以及其他目的、特征和优点可以更加显而易见,其中: By reference to the following detailed description in conjunction with the accompanying drawings of the present invention, the above and other objects, features and advantages of the present invention may be more apparent, wherein:

图1是显示形成薄氧化膜和厚氧化膜的工艺的工艺图,该工艺是根据本发明的优选实施例的所述半导体器件的制造方法的一部分; FIG. 1 is a process showing the process of forming a thin oxide film and a thick oxide film, the process is part of the method of manufacturing a semiconductor device according to a preferred embodiment of the present invention;

图2是显示形成非掺杂非晶硅和氮化硅膜的工艺的工艺图,该工艺是根据本发明的优选实施例的所述半导体器件的制造方法的一部分; FIG 2 is a process of forming a non-doped amorphous silicon and silicon nitride FIG film process, which process is part of the method of manufacturing a semiconductor device according to a preferred embodiment of the present invention;

图3是显示形成抗蚀剂图形的工艺的工艺图,该工艺是根据本发明的优选实施例的所述半导体器件的制造方法的一部分; FIG. 3 is a process diagram of a process of forming a resist pattern, the process is part of the method of manufacturing a semiconductor device according to a preferred embodiment of the present invention;

图4是显示形成用于STI的沟槽的工艺的工艺图,该工艺是根据本发明的优选实施例的所述半导体器件的制造方法的一部分; FIG 4 is a view of a process for a process of forming the STI trench, the process is part of the method of manufacturing a semiconductor device according to a preferred embodiment of the present invention;

图5是显示形成氧化硅膜的工艺的工艺图,该工艺是根据本发明的优选实施例的所述半导体器件的制造方法的一部分; FIG 5 is a process view of a process of forming a silicon oxide film, the process is part of the method of manufacturing a semiconductor device according to a preferred embodiment of the present invention;

图6是显示形成元件隔离区的工艺的工艺图,该工艺是根据本发明的优选实施例的所述半导体器件的制造方法的一部分; FIG 6 is a process diagram of the process of forming the element isolation region, a part of the process is a method of manufacturing the semiconductor device according to a preferred embodiment of the present invention;

图7是显示形成抗蚀剂图形的工艺的工艺图,该工艺是根据本发明的优选实施例的所述半导体器件的制造方法的一部分; FIG. 7 is a process diagram of a process of forming a resist pattern, the process is part of the method of manufacturing a semiconductor device according to a preferred embodiment of the present invention;

图8是显示构图氮化硅膜的工艺的工艺图,该工艺是根据本发明的优选实施例的所述半导体器件的制造方法的一部分; FIG 8 is a process diagram of the process of the patterned silicon nitride film, the process is part of the method of manufacturing a semiconductor device according to a preferred embodiment of the present invention;

图9是显示形成栅沟槽的工艺的工艺图,该工艺是根据本发明的优选实施例的所述半导体器件的制造方法的一部分; FIG 9 is a process of forming the gate trench of FIG process, the process is part of the method of manufacturing a semiconductor device according to a preferred embodiment of the present invention;

图IO是显示形成氧化硅膜的工艺的工艺图,该工艺是根据本发明 FIG IO process is a process diagram for forming a silicon oxide film, the process according to the present invention

的优选实施例的所述半导体器件的制造方法的一部分; The method of manufacturing a portion of the semiconductor device of the preferred embodiment;

图11是显示在栅沟槽中形成掺磷非晶硅膜的工艺的工艺图,该工艺是根据本发明的优选实施例的所述半导体器件的制造方法的一部分; FIG 11 is a process showing the process of a phosphorus-doped amorphous silicon film is formed in the gate trench, the process is part of the method of manufacturing a semiconductor device according to a preferred embodiment of the present invention;

图12是显示对所述掺磷非晶硅膜进行回蚀的工艺的工艺图,该工艺是根据本发明的优选实施例的所述半导体器件的制造方法的一部分; FIG 12 is a graph showing the phosphorus-doped amorphous silicon film is subjected to etch-back process of FIG process, the process is part of the method of manufacturing a semiconductor device according to a preferred embodiment of the present invention;

图13是显示去除所述氮化硅膜、元件隔离区的上部和氧化硅膜的上部的工艺的工艺图,该工艺是根据本发明的优选实施例的所述半导体器件的制造方法的一部分; FIG 13 is a process of removing the silicon nitride film showing the process of an upper portion, and an upper silicon oxide film is an element isolation region, a part of the process is the method of manufacturing a semiconductor device according to a preferred embodiment of the present invention;

图14是显示形成非掺杂非晶硅膜的工艺的工艺图,该工艺是根据本发明的优选实施例的所述半导体器件的制造方法的一部分; FIG 14 is a non-doped amorphous silicon film forming process of FIG process, the process is part of the method of manufacturing a semiconductor device according to a preferred embodiment of the present invention;

图15是显示注入硼离子的工艺的工艺图,该工艺是根据本发明的优选实施例的所述半导体器件的制造方法的一部分; FIG 15 is a process showing the process of implantation of boron ions, the process is part of the method of manufacturing a semiconductor device according to a preferred embodiment of the present invention;

图16是显示注入磷离子的工艺的工艺图,该工艺是根据本发明的优选实施例的所述半导体器件的制造方法的一部分; FIG 16 is a process showing the process of implantation of phosphorus ions, the process is part of the method of manufacturing a semiconductor device according to a preferred embodiment of the present invention;

图17是显示形成抗蚀剂图形的工艺的工艺图,该工艺是根据本发明的优选实施例的所述半导体器件的制造方法的一部分; FIG 17 is a process diagram of a process of forming a resist pattern, the process is part of the method of manufacturing a semiconductor device according to a preferred embodiment of the present invention;

图18是显示对分层膜进行构图的工艺的工艺图,该工艺是根据本发明的优选实施例的所述半导体器件的制造方法的一部分; FIG 18 is a process diagram of the process of the layered film is patterned, the process is part of the method of manufacturing a semiconductor device according to a preferred embodiment of the present invention;

图19是显示形成源/漏扩散区的工艺的工艺图,该工艺是根据本发明的优选实施例的所述半导体器件的制造方法的一部分; FIG 19 is a process showing the process of forming the source / drain diffusion regions, the process is part of the method of manufacturing a semiconductor device according to a preferred embodiment of the present invention;

图20是显示形成各种连线图形和单元电容的工艺的工艺图,该工艺是根据本发明的优选实施例的所述半导体器件的制造方法的一部分; FIG 20 is a wiring pattern to form various cell capacitor and a process illustrating a process, the process is part of the method of manufacturing a semiconductor device according to a preferred embodiment of the present invention;

图21是显示形成STI、栅沟槽和栅绝缘膜的工艺的工艺图,该工艺是第一常规方法的一部分; FIG 21 is a process diagram form the STI process, the gate trench and the gate insulating film, a first part of the process is a conventional process;

图22是显示形成非掺杂硅膜的工艺的工艺图,该工艺是第一常规 FIG 22 is a process showing the process of forming a non-doped silicon film, the process is a first conventional

方法的一部分; Part of the method;

图23是显示注入硼离子的工艺的工艺图,该工艺是第一常规方法200610132138.2 FIG 23 is a process showing the process of implantation of boron ions, the first process is a conventional process 200610132138.2

说明书第8/15页 Instructions Page 8/15

的一部分; a part of;

图24是显示注入磷离子的工艺的工艺图,该工艺是第一常规方法 FIG 24 is a process showing the process of implantation of phosphorus ions, the process is a first conventional method

的一部分; a part of;

图25是显示形成掺杂硅膜的工艺的工艺图,该工艺是第二常规方法的一部分; FIG 25 is a doped silicon film forming process of FIG process, the process is a part of the second conventional method;

图26是显示对所述掺杂硅膜进行回蚀的工艺的工艺图,该工艺是第二常规方法的一部分; FIG 26 is a doped silicon film on the etch-back process of FIG process, the process is a part of the second conventional method;

图27是显示形成非掺杂硅膜的工艺的工艺图,该工艺是第二常规 FIG 27 is a process showing the process of forming a non-doped silicon film, the second process is a conventional

方法的一部分;以及 Part of the method; and

图28是显示根据本发明优选实施例的修改示例的剖面图。 FIG 28 is a sectional view showing a modified example of the embodiment of the present invention according to a preferred embodiment.

具体实施方式 detailed description

以下参考附图详细说明本发明的优选实施例。 Reference to the drawings preferred embodiments of the present invention will be described.

图l至20是显示根据本发明实施例制造具备双栅结构晶体管和沟槽栅晶体管的半导体器件的工艺的示意图。 L to FIG. 20 is a display example embodiment includes a process of manufacturing a semiconductor device and a double gate structure transistor trench-gate transistor according to the present invention in a schematic view. 在图1至20中,"M区"指示存储器单元区,其内形成沟槽栅晶体管,在外围电路内提供"P区" 和"N区",其中"P区"是其内用以形成带有栅电极的平面P沟道晶体管的区域(也称为P型外围电路区),并且所述栅电极包含P型多晶硅, 而其中"N区"是其内用以形成带有栅电极的平面N沟道晶体管的区域(也称为N型外围电路区),并且所述栅电极包含N型多晶硅。 In Figures 1 20, "M region" indicates that the memory cell area, a trench gate transistor formed therein, to provide "P region" and "N region" in the peripheral circuit, wherein "P zone" formed therein is used planar region with the gate electrode of P-channel transistor (also referred to as a P-type peripheral circuit region) and the gate electrode comprises P-type polysilicon, and where "N region" to form a gate electrode having an inner planar region N-channel transistor (also referred to as N-type peripheral circuit region) and the N-type polysilicon gate electrode comprises.

首先,如图1所示,在半导体衬底100的P区和N区的表面上形成具有大约1.5至3nm的厚度的薄氧化膜101s。 First, as shown, forming a thin oxide film having a thickness of about 1.5 to 101s of 3nm on one surface of the P and N regions of the semiconductor substrate 100. 在所述外围电路区的P 区和N区以外的并且其内用以形成电源电路等的某一区域(未示出), 以及M区之内形成具备大约4.5nm至6nm厚度的厚氧化膜101t。 In the region other than the peripheral circuit region P and N regions and a region thereof for forming the power supply circuit or the like (not shown), and a thick oxide film comprising a thickness of from about 4.5nm to 6nm is formed in the region of M 101t. 在具体示例中,通过热氧化在半导体衬底100的整个表面上形成厚度略小于6nm的热氧化膜,然后在不包含P区和N区的其他区域覆盖抗蚀剂掩模,然后去除P区和N区上的热氧化膜,随后,去除抗蚀剂掩模, 进而用酸清洗衬底100的整个表面。 In a particular example, formed by thermal oxidation on the entire surface of the semiconductor substrate 100 is slightly smaller than the thickness of the thermal oxide film 6nm, then no other regions in the P and N regions covering the resist mask is then removed region P and a thermal oxide film on the N region, and then, the resist mask is removed, thereby cleaning the entire surface of the substrate 100 with an acid. 该清洗步骤将M区上的以及所述 The washing step and the upper region of the M

其内形成电源电路等的区上的热氧化膜的一部分的表面进行了去除, Portion of the surface of the thermal oxide film formed on the inner region of the power supply circuit and the like have been removed,

使得该热氧化膜的厚度降为大约5nm。 So that the thermal oxide film thickness reduced to about 5nm. 然后,再次热氧化整个表面, 以在P区和N区上形成大约3nm厚度的薄氧化膜101s,以及在M区上和所述其内形成电源电路等的区(未示出)上形成具备大约6nm厚度的厚氧化膜101t。 Is then formed, the entire surface of the thermally oxidized again to form a thin oxide film 101s of about 3nm thickness on the P and N regions, and forming a region (not shown) in the power supply circuit M is provided within the region and a thickness of about 6nm thick oxide film 101t.

形成具备不同厚度的氧化膜的原因如下。 With different reasons for forming an oxide film thickness is as follows. 首先,在p区和N区内形成的晶体管需要薄栅绝缘膜以便于在低压下工作,因此所述薄氧化膜101s被用作栅绝缘膜。 First, a transistor in the p-region and the N region formed in the thin gate insulating film is required in order to operate at low voltage, thus the thin oxide film is used as the gate insulating film 101s. 在M区内形成的存储器单元晶体管内,采用升压电压,并且所述电源电路也需要具备高压电阻的栅绝缘膜,由于用于产生使存储器单元运行所需的高压的晶体管也需要施加高压。 In the memory cell transistor formed region M, step-up voltage, the power supply circuit and the gate insulating film also need to have high pressure resistance, since the transistor for generating a high voltage required for operating the memory cells need to apply a high voltage. 因此形成作为这些栅绝缘膜的厚氧化膜101t。 Thereby forming a thick oxide film 101t such as a gate insulating film.

在图2所示的随后的步骤中,通过CVD (化学气相淀积)方法形成具备大约为10至30nm的厚度的作为保护膜的非掺杂非晶硅膜102, 以便于保护所述薄氧化膜101s。 In a subsequent step shown in FIG. 2, is formed by CVD (chemical vapor deposition) method to have a thickness of about 10 to 30nm as a protective film of non-doped amorphous silicon film 102, in order to protect the thin oxide film 101s. 然后通过LP (低压)一CVD方法形成具备大约80至150nm厚度的氮化硅膜103。 Then (low pressure) is formed comprising a LP CVD method, the silicon nitride film 80 of about 103 to 150nm thickness.

如图3所示,根据STI (浅沟槽隔离)技术,在用作隔离元件的区域的每个元件隔离区上,形成抗蚀剂图形104。 As shown in FIG. 3, the STI (shallow trench isolation) technique, in each element isolation region is used as the isolation element region, a resist pattern 104 is formed.

如图4所示,当使用所述抗蚀剂图形104作为掩模对所述氮化硅膜103进行构图后,去除所述抗蚀剂图形104,使用构图的氮化硅膜103作为掩模对所述非掺杂非晶硅膜102、厚氧化膜101t、薄氧化膜101s 以及半导体衬底100进行干法刻蚀。 4, when the resist pattern 104 as a mask after patterning of the silicon nitride film 103, the resist pattern 104 is removed using the patterned silicon nitride film 103 as a mask the non-doped amorphous silicon film 102, a thick oxide film 101T, 101s thin oxide film and the semiconductor substrate 100 is dry etched. 非掺杂非晶硅膜102、厚氧化膜101t和薄氧化膜101s因此被构图,并且所述用于STI的沟槽105在半导体衬底100内形成。 A non-doped amorphous silicon film 102, a thick oxide film 101t and 101s Thus a thin oxide film is patterned, and for the STI trench 105 formed in the semiconductor substrate 100.

然后进行热氧化处理,以便于去除所述沟槽105的内壁的刻蚀损伤,之后,如图5所示,通过HDP (高密度等离子体)一CVD方法在 Followed by thermal oxidation treatment, in order to remove etch damage of the inner wall of the trench 105, then, as shown in FIG. 5, by the HDP (High Density Plasma) CVD method, a

所述整个表面形成氧化硅膜106,以填充沟槽105。 The entire surface of the silicon oxide film 106 is formed to fill the trenches 105.

然后,使用氮化硅膜103作为停止层(stopper)进行CMP (化学机械剖光),通过剖光去除在所述氮化硅膜103上的氧化硅膜106,以使得在沟槽105内保留所述氧化硅膜106。 Then, a silicon nitride film 103 as a stopper (a stopper) for CMP (chemical mechanical polishing), Polishing by removing the silicon oxide film 106 on the silicon nitride film 103 within the trench so that the retained 105 the silicon oxide film 106. 如图6所示,因此形成元件隔离区106i。 6, thus forming an element isolation region 106i.

如图7所示,在M区形成带有多个开口的抗蚀剂图形107,以便于在M区形成所述沟槽栅存储器单元晶体管的栅沟槽。 As shown in FIG 7, a resist pattern 107 is formed with a plurality of openings in the M region, so as to form a gate trench in the trench gate memory cell transistors M in the region. 这次,通过抗蚀剂图形107将P区和N区全部覆盖。 This time, the entire cover 107 by the resist pattern P and N regions. 在M区的元件隔离区106i上面的抗蚀剂图形107内,形成幵口,以便于用于在临近的存储器单元区(未示出)形成的栅沟槽。 106i in the upper region of the element isolation region M of the resist pattern 107, Jian port formed so as to adjacent to the gate trench in a memory cell region (not shown) is formed.

使用抗蚀剂图形107作为掩模,如图8所示,以该掩模的形状构图氮化硅膜103。 Using the resist pattern 107 as a mask, the mask is patterned to form the silicon nitride film 103 as shown in FIG. 8.

在去除所述抗蚀剂图形107之后,如图9所示,对所述非掺杂非晶硅膜102和厚氧化膜101t进行刻蚀,并对半导体衬底IOO进行刻蚀, 从而在半导体衬底100内形成栅沟槽108。 After removing the resist pattern 107 shown in Figure 9, the non-doped amorphous silicon film 102 and the thick oxide film 101t is etched, the semiconductor substrate IOO and etched so that the semiconductor forming a gate trench 108 within the substrate 100. 图4中被作为掩模用以形成STI沟槽的所述氮化硅膜103无需被去除而予以保留,并被作为掩模用于形成所述栅沟槽108,如图9所示。 FIG 4 is to be preserved as a mask the silicon nitride film 103 for forming an STI trench need not be removed, and as a mask for forming the gate trench 108, as shown in FIG.

然后通过热氧化进行牺牲氧化,以去除所述栅沟槽108内的刻蚀表面的损伤和污染,并通过湿法刻蚀去除牺牲氧化膜。 Then the sacrificial oxide by thermal oxidation, etching to remove damage and contamination of the inner surface of the trench gate 108, and removing the sacrificial oxide film by wet etching. 如图10所示, 形成氧化硅膜109以作为所述存储器单元晶体管的栅绝缘膜。 10, a silicon oxide film 109 is formed as a gate insulating film of the memory cell transistor. 如上所述,该氧化硅膜109必须也具备高压电阻,并且优选地具备大约4.5至7.5nm的厚度。 As described above, the silicon oxide film 109 must have high pressure resistance, and preferably have a thickness of about 4.5 to 7.5nm.

在这里优选地通过以下工艺形成氧化硅膜109,即,在大约80CTC 的温度下通过CVD方法淀积厚度大约为3.5nm至5.5nm的CVD氧化 CVD silicon oxide film where oxide is preferably formed by a process 109, i.e., at a temperature of about 80CTC is deposited to a thickness of about 3.5nm by a CVD method in order to 5.5nm

膜(优选地是HTO (高温氧化物)),在此之后,在大约105(TC地温度下对所述CVD氧化膜进行热氧化,以便于使所述CVD氧化膜加密, 去除杂质,并且对所述CVD氧化膜和半导体衬底IOO之间地界面进行修饰。在所述栅沟槽108内形成的栅绝缘膜109因而成为分层膜,该分层膜包括通过CVD方法形成的CVD氧化硅膜109v,和在所述半导体衬底IOO与CVD氧化硅膜109v之间的界面内形成的厚度大约为1.0 至2.0nm的热氧化膜109h。由于CVD氧化硅膜109v和暴露于所述栅沟槽的内壁的硅膜102也会在上述的热氧化中进行反应,所以在硅膜102的侧表面上也会形成热氧化膜109h,如图所示。 Film (preferably the HTO (high temperature oxide)), after which, in (TC at a temperature of about 105 the CVD oxide film thermally oxidized, so as to cause said encryption CVD oxide film to remove impurities, and to the interface between the CVD oxide film and the semiconductor substrate IOO be modified. the gate insulating film 109 formed within the gate trench 108 and thus become layered membrane, which layered film comprises CVD silicon oxide formed by a CVD method film 109v, and a thickness within the interface formed between the semiconductor substrate and the CVD silicon oxide film IOO 109V about 1.0 to 2.0nm thermal oxide film 109h. Since the CVD silicon oxide film is exposed to 109V and the gate trench inner wall of the groove in the silicon film 102 is also above the thermal oxidation reaction, the thermal oxide film is formed also on the side surface 109h of the silicon film 102, as shown in FIG.

当通过热氧化形成存储器单元晶体管的全部的栅绝缘膜时,氧化物种会扩散进半导体衬底100和已形成的元件隔离区106i的界面中。 When all the gate insulating film of the memory cell transistor is formed by thermal oxidation, the oxide species may diffuse into the semiconductor substrate interface and the element isolation region 100 formed of a 106i. 该扩散进的氧化物种会引起半导体衬底100氧化。 The diffusion of oxidizing species into the oxide 100 causes the semiconductor substrate. 结果导致,构成所述元件隔离区106i的硅氧化膜的淀积扩张,半导体衬底100内出现应力,并且所述DRAM的结特性恶化。 Result, the expansion of the silicon oxide film is deposited constituting the element isolation region 106i, the stress occurs within the semiconductor substrate 100, and the DRAM junction characteristics deteriorate. 如上所述,在本发明,通过CVD 方法形成的CVD氧化硅膜109v用作主要的栅绝缘膜,因此可以将应力最小化,并避免结特性的恶化。 As described above, in the present invention, 109v CVD silicon oxide film formed by a CVD method is used as the primary gate insulating film stress can be minimized, and to avoid a deterioration in the junction characteristics.

为形成沟槽栅晶体管的栅电极,在包含了所述栅沟槽108的内部的整个表面上形成非晶硅膜,该非晶硅膜内掺杂磷作为N型杂质。 To form the gate electrode trench gate transistor comprising the amorphous silicon film is formed on the entire inner surface of the trench gate 108, the amorphous silicon film doped with phosphorus as an N-type impurity. 如图11所示,通过使用氮化硅膜103作为停止层的CMP方法进行平坦化工艺,从而将所述掺磷的非晶硅膜IIO嵌入所述栅沟槽108内。 As shown, by using the silicon nitride film 103 as a CMP stop layer is a method planarization process 11, so that the P-doped amorphous silicon film IIO 108 is embedded in the gate trench.

如图12所示,对栅沟槽108内的掺磷非晶硅膜IIO进行回蚀,直至与通过干法刻蚀的厚氧化膜101t大约相同的位置。 As shown in FIG. 12, a phosphorus-doped amorphous silicon film 108 IIO within the gate trench is etched back until the oxide film thickness by dry etching 101t approximately the same position.

然后进行湿法刻蚀以去除所述氮化硅膜103、元件隔离区106i的上部和氧化硅膜109的上部。 And then wet etching is performed to remove an upper portion of the silicon nitride film 103, the silicon oxide film 109 and the upper portion of the element isolation region 106i. 如图13所示,元件隔离区106i的上表面和所述保护膜(非掺杂非晶硅膜)102因此互相对准。 As shown, the upper surface of element isolation region 106i and the protective film (non-doped amorphous silicon film) 102 13 thus aligned with each other. 以相同方式,在M区的栅沟槽108内形成选择性掺杂的非晶硅膜110。 In the same manner, a selectively doped amorphous silicon film 110 in the gate trench 108 M region. 因此可以避免沟槽栅电极的耗尽。 Thus avoiding the trench gate electrode depletion. 根据本发明,在P区和N区的栅绝缘膜101s上形成非掺杂非晶硅膜102,并且该膜在去除氮化硅膜103的期间作为保护膜,其中所述氮化硅膜103 (见图12)是用于形成栅沟槽108时作为掩模的。 According to the present invention, a non-doped amorphous silicon film 102 is formed on the gate insulating film 101s P and N regions, and the film during the removal of the silicon nitride film 103 as a protective film, wherein said silicon nitride film 103 (see FIG. 12) for forming a gate trench 108 as a mask. 因此可以避免损伤栅绝缘膜101s。 Thus avoiding damage the gate insulating film 101s.

如图14所示,使用CVD方法,形成厚度大约为30nm至80nm的非掺杂非晶硅膜111,以成为所述双栅晶体管栅电极。 14, using a CVD method, non-doped amorphous silicon film 111 formed in a thickness of about 30nm to 80nm to become a double gate transistor gate electrode.

如图15所示,通过抗蚀剂图形112对M区和N区进行掩模,将硼(B)作为P型杂质通过离子注入将其注入进P区。 15, a mask by the resist pattern 112 pairs of M and N regions, boron (B) as a P-type impurity is injected by ion implantation into the P region. 该硼离子注入在10keV或者更低的低能量下进行。 The boron ion implantation at 10keV or lower for low-energy. 在随后进行的热处理中,所述注入的硼离子扩散,因而所述P区的非掺杂非晶硅膜111和102 (见图14) 成为P型非晶硅膜lllp和102p。 In the ensuing heat treatment, the diffusion of implanted boron ions, and thus the non-doped amorphous silicon film 111 and the P region 102 (see FIG. 14) become P-type amorphous silicon film lllp and 102p.

在去除抗蚀剂图形112后,在该情况下的P区通过抗蚀剂图形113 进行掩模,并通过离子注入将磷(P)作为N型杂质注入N区和M区, 如图16所示。 After removing the resist pattern 112, a mask region P in this case by the resist pattern 113, and by ion implantation of phosphorus (P) as an N-type impurity implantation region M and N region, 16 in FIG. shows. 该磷离子注入也要在20keV或者更低的低能量下进行, 与上述的硼离子注入相同,通过随后的热处理所述磷离子扩散。 The phosphorus ions implanted at 20keV must also be low-energy or lower, with the same above-described boron implantation, diffusion through the subsequent heat treatment of the phosphorus ions. N区的非掺杂非晶硅膜111和102 (见图15)因而成为N型非晶硅膜llln 和102n。 A non-doped amorphous silicon film 111 and the N region 102 (see FIG. 15) and thus become N type amorphous silicon film llln and 102n. 通过离子注入,M区的非掺杂非晶硅膜lll和102也成为N 型非晶硅膜llln和〗.02n。 By ion implantation, a non-doped amorphous silicon film 102 and lll M region has become N type amorphous silicon film and llln〗 .02n.

根据本发明,掾磷硅膜已经嵌入所述M区的栅沟槽108。 According to the present invention, auxiliary phosphorus silicon film 108 has been embedded in the gate trench region M. 在用于制造P型和N型非掺杂硅膜111 (即,双栅晶体管的栅电极)的离子注入工艺中,在进行N区的磷离子注入的同时进行M区的离子注入时, 可以根据硅膜lll (以及作为保护膜的硅膜102)的厚度在适当的注入条件下进行离子注入,而不用考虑对栅沟槽108的注入。 When for the manufacture of P-type and N-type non-doped silicon film 111 (i.e., the gate electrode of the double gate transistor) ion implantation process, the N-region while performing the ion implantation of phosphorus is ion implanted region M may be ion implantation at a suitable implantation conditions according to the film thickness of the silicon LLL (silicon film and the protective film 102), irrespective of the injection gate trench 108.

如图17所示,在已掺杂的非晶硅膜llln和lllp上制备用于形成栅电极的抗蚀剂图形114。 As shown in FIG 17, a resist pattern 114 is formed on the gate electrode is a doped amorphous silicon film and lllp for preparing llln.

如图18所示,通过使用抗蚀剂图形114作为掩模,对包含非晶硅膜lllp和102p的分层膜,以及包含非晶硅膜llln和102n的分层膜, 分别进行构图。 18, by using the resist pattern 114 as a mask, and the amorphous silicon film containing lllp layered film 102p and 102n and the amorphous silicon film containing llln layered films were patterned. 因此,在M区形成由掺杂非晶硅膜IIO和llln所组成的沟槽栅晶体管的栅电极,在P区形成由掺杂非晶硅膜lllp和102p 所组成的P型栅电极,在N区形成由掺杂非晶硅膜llln和102n所组成的N型栅电极。 Thus, a gate electrode trench gate transistor and a doped amorphous silicon film IIO llln consisting of M region, a doped region formed in the P and P-type amorphous silicon film lllp composed of a gate electrode 102p, in N region is formed by doping N-type amorphous silicon film and the gate electrode llln consisting 102n.

在此所述示例是如下情况,即其中构图后的非晶硅膜llln与M 区的栅沟槽108未对准。 In this case the example is as follows, in which the amorphous silicon film llln gate trench and the patterned M region 108 is not aligned. 然而,当出现未对准时,非晶硅膜llln和非晶硅膜102仍保留在厚氧化膜101t上,并成为栅电极的一部分。 However, when misalignment occurs, the amorphous silicon film and the amorphous silicon film 102 llln remains on the thick oxide film 101T, and become part of the gate electrode. 在该类型的情况下,所述厚氧化膜101t作为该沟槽栅晶体管中栅绝缘膜的一部分。 In the case of this type, the thick oxide film 101t as part of the trench gate transistor gate insulating film. 然而,由于在栅绝缘膜中形成氧化膜101t以至于具备和所述氧化硅膜109基本相同的厚度,则击穿电压上的的降低可以被最小化。 However, since the oxide film 101t is formed on the gate insulating film and is provided so that the silicon oxide film 109 is substantially the same thickness, on the lowering of the breakdown voltage can be minimized.

如图19所示,用抗蚀剂膜(未示出)覆盖M区和N区,使用P 19, with a resist film (not shown) covering the M and N regions, a P

型栅电极作为掩模,通过离子注入将P型杂质注入P区形成P型源/漏扩散区115p。 Type gate electrode as a mask, ion implantation by implanting P-type impurity region P P-type source / drain diffusion regions 115p formed. 用抗蚀剂膜(未示出)覆盖P区,使用M区和N区的栅电极作为掩模,通过离子注入将N型杂质注入M区和N区。 With a resist film (not shown) covers the P region, using the gate electrodes M and N regions as a mask, by ion implantation of N-type impurity implantation M and N regions. 随后,在N区形成N型源/漏扩散区115n,在M区形成N型源/漏扩散区116。 Subsequently, N-type source / drain diffusion region 115n in the N region, an N-type source / drain diffusion regions 116 in the M region. 根据该工艺,在M区形成沟槽栅存储器单元晶体管,在P区和M区即外围电路区形成双栅晶体管。 According to this process, a trench gate memory cell transistors M in the area, i.e. the peripheral circuit region is formed in a double gate transistor region and the P region M.

通过用以活化源/漏扩散区所进行的热处理,或者通过随后进行的加热工艺,将所述非晶硅膜llln、 lllp、 102p、 102n以及110从非晶 By the heat treatment for activating a source / drain diffusion regions are carried out, or by subsequent heating process, the amorphous silicon film llln, lllp, 102p, 102n, and 110 from the amorphous

硅膜转化为多晶硅膜。 Silicon film into a polysilicon film.

使用普通方法可以成层M区内的各种类型的连线和单元电容。 Common methods may be used as various types of wiring layer and M cell capacitor area. 具体而言,具备沟槽栅存储区单元晶体管的DRAM可以通过以下工艺形 Specifically, the trench gate includes a storage area of ​​the DRAM cell transistor can be formed by the following process

成:在所述存储器单元晶体管上形成层间绝缘膜(mterlayer insulating mm) 117,然后形成通过所述层间绝缘膜117的连接孔栓118、位线119、单元电容120、铝连线121以及其他部件,如图20所示。 To: interlayer insulating film (mterlayer insulating mm) 117 formed on the memory cell transistors, and is formed by the interlayer insulating film 117 is connected via plug 118, the bit line 119, the capacitor unit 120, and an aluminum wiring 121 other components, as shown in Figure 20.

根据如上所述本发明的实施例,在所述栅绝缘膜(薄氧化膜)101s 之上在所述氮化硅膜103之下预先提供有保护膜102,其中所述氮化硅膜103在用于形成栅沟槽108时作为掩模层,并且,在所述P型外围电路区和N型外围电路区内形成栅沟槽108。 According to an embodiment of the present invention as described above, over the gate insulating film (thin oxide film) 101S provided in advance in the silicon nitride film 103 under the protective film 102, wherein the silicon nitride film 103 in trench 108 for forming the gate as a mask layer, and the gate trench 108 is formed in the peripheral circuit region P-type and N-type peripheral circuit region. 然后无需去除掩模层103 而在栅沟槽108内形成掺杂非晶硅膜110,然后将用于形成栅沟槽108 的掩模层103去除。 It is then doped amorphous silicon film 110 is formed in gate trench 108, and then removing the mask layer 103 for forming the gate trench 108 without removing the mask layer 103. 由于在栅沟槽108内嵌入和形成所述掺杂非晶硅膜IIO之后才去除所述掩模层103,所以可以通过预先提供的保护膜避免对栅绝缘膜101s的损伤。 Since only after removing the mask layer 103 is embedded in the gate trench 108 and the doped amorphous silicon film is formed IIO, it is possible to prevent damage to the gate insulating film 101s of the protective film previously provided. 因此,可以在栅沟槽108内形成掺杂非晶硅膜110,并在P型外围电路区、N型外围电路区以及被嵌入栅沟槽的掺杂非晶硅膜IIO上形成非掾杂非晶硅膜111。 Thus, doped amorphous silicon film 110 may be formed in gate trench 108, and forms a non-type auxiliary heteroatom in the peripheral circuit region P, N-type region and the peripheral circuit IIO doped amorphous silicon film is embedded in the gate trench an amorphous silicon film 111. 可以在对薄氧化膜没有损伤的情况下以合适的杂质浓度形成所述硅膜110、 111和102,并且沟槽栅晶体管和双栅结构晶体管可以均保持高性能。 Suitable impurity concentration may be formed without damage to the thin oxide film where the silicon film 110, 111 and 102, and the trench gate transistor and a double gate structure transistor can remain high performance.

本发明不限制于上述实施例,而且在权利要求书所陈述的本发明的范围内可能作出各种修改,自然而然的,这些修改均被包含于本发 The present invention is not limited to the above embodiments, and various modifications may be made within the scope of the invention set forth in the appended claims, and naturally these modifications are included in the present invention

明的范围内。 Out of the range.

例如,在上述实施例中,使用非掺杂非晶硅膜作为保护膜102。 For example, in the above embodiments, a non-doped amorphous silicon film 102 as a protective film. 然而,该配置不是限制性的,只要另一种材料能够在去除掩模的时候保护所述栅绝缘膜不受损伤并且可以形成不妨碍晶体管工作的膜,那么也可以使用该材料。 However, this configuration is not limiting, so long as another material capable of protecting the gate insulating film is not damaged when the mask is removed and does not interfere with operation of the transistor may form a film, then the material may be used. 具体而言,就是可以釆用另一种材料只要其可以形成膜(导电薄膜等),其中该膜可以在给栅电极施加电压时形成所需的沟道。 Specifically, that may preclude long as it can form a film (conductive film), the film may be formed where the desired channel when voltage is applied to the gate electrode of another material.

在上述实施例中,描述了这样一个示例,即,每个硅膜均是先以非晶硅态形成然后通过随后的加热工艺转化为多晶硅膜。 In the above embodiment, such an example is described, i.e., each of the silicon film are first formed and then converted to amorphous state to a polycrystalline silicon film by the subsequent heating process. 然而,如果需要,也可以一开始就使用多晶硅膜。 However, if desired, you may start out with a polysilicon film.

不是必须仅使用硅膜形成所述栅电极,也可以在硅膜上形成硅化 Forming the gate electrode is not necessary to use only a silicon film, a silicide may be formed on the silicon film

物膜,或者通过成层金属膜而制备一种所谓的多金属栅电极。 Film, or prepared by a so-called multi-layered metal gate electrode is formed by a metal film. 图28显示的是栅电极是多金属栅电极的示例,并对应于上述实施例中图19所示的工艺。 Figure 28 shows an example of the multi-gate electrode is a metal gate electrode, and the process corresponding to the above-described embodiment shown in FIG. 19. 如图28所示,将金属膜122成层在M区的硅膜110上,并在P区和N区的每个硅膜lllp和llln上分别成层金属膜122。 28, a metal film 122 on the silicon layer into a film of 110 M region, and the metal film 122 are layered on each silicon film lllp and llln P and N regions of. 当所述栅电极进而由多金属栅电极所组成时,需要对P区和N区的硅膜111 进行离子注入,以使得在形成金属膜122之前,将P区的硅膜111转化为P型硅膜lllp,并将N去的硅膜lll转化为N型硅膜llln。 Further, when the gate electrode by a plurality of metal gate electrode composed of the silicon film 111 needs to P and N regions of ion implantation, such that prior to forming the metal film 122, a silicon film 111 P into P-type region silicon film lllp, and N lll silicon film to be converted to an N-type silicon film llln.

进一步的,上述示例是如下情况,即其中用于形成沟槽105的掩模层(所述沟槽105被用于STI ),和用于形成栅沟槽108的掩模层在所述氮化硅膜103内是共用的。 Further, the above-described example is a case, in which the mask layer for forming the trench 105 (the trench for the STI 105), and a mask layer is formed in gate trench 108 of the nitriding silicon film 103 are common. 然而,当所述STI (元件隔离区)106i 形成之后,可以去除所述氮化硅膜103,并且可以制备新的氮化硅膜以形成掩模层。 However, after the STI (element isolation region) 106i is formed, the silicon nitride film 103 may be removed and may be prepared in a new film to form a silicon nitride mask layer.

Claims (19)

  1. 1.一种用于制造半导体器件的方法,该方法包括: 第一步,在存储器单元区和外围电路区形成第一栅绝缘膜,其中所述外围电路区具备半导体衬底的第一导电类型晶体管形成区和第二导电类型晶体管形成区; 第二步,在所述第一栅绝缘膜上形成保护膜; 第三步,形成带有用于形成栅沟槽的开口的掩模层; 第四步,使用所述掩模层在所述半导体衬底的所述存储器单元区内形成栅沟槽; 第五步,在所述栅沟槽的内壁形成第二栅绝缘膜; 第六步,在所述栅沟槽内形成以第二导电类型杂质掺杂的第一硅膜; 第七步,去除所述掩模层; 第八步,在所述保护膜和所述第一硅膜上形成非掺杂第二硅膜; 第九步,选择性的将第一导电类型杂质引入在所述外围电路区的所述第一导电类型晶体管形成区上的所述第二硅膜; 第十步,选择性的将第二导电类型杂质引 A method of manufacturing a semiconductor device, the method comprising: a first step, a first gate insulating film formed in the memory cell region and the peripheral circuit region, wherein the peripheral circuit region includes a semiconductor substrate of a first conductivity type transistor forming region and the second conductivity type transistor formation regions; a second step of forming gate insulating film on the first protective film; a third step of forming a mask layer having an opening for forming the gate trench; fourth step, using the mask layer in the memory cell region of said semiconductor substrate, forming a gate trench; a fifth step, the second gate insulating film formed on the inner wall of the gate trench; sixth step, in the gate is formed in the first silicon film doped with an impurity of a second conductivity type in the trench; a seventh step of removing the mask layer; eighth step, the protective film and the first silicon film formed in the a ninth step of the second silicon film, selectively introducing an impurity of the first conductivity type on said peripheral circuit region of the first conductivity type transistor formation region;; second non-doped silicon film tenth step selective second conductivity type impurity primer 在所述外围电路区的所述第二导电类型晶体管形成区上的所述第二硅膜; 第十一步,构图所述第二硅膜和所述保护膜,形成第一栅电极,所述第一栅电极包含其中引入了第一导电类型杂质的所述第二硅膜;以及形成第二栅电极,所述第二栅电极包含其中引入了第二导电类型杂质的第二硅膜。 On the peripheral circuit region in said second region of a second conductivity type transistor forming a silicon film; eleventh step, patterning the second silicon film and the first gate electrode of said protective film is formed, the wherein said first gate electrode comprises introducing the impurity of the first conductivity type second silicon film; and forming a second gate electrode, the second gate electrode comprises a second silicon film into which an impurity of a second conductivity type.
  2. 2. 根据权利要求l所述用于制造半导体器件的方法,其中, 所述保护膜是非掺杂硅膜;在所述第九步,还将所述第一导电类型杂质引入在所述第一导电类型晶体管形成区上的所述保护膜;以及在所述第十步,还将所述第二导电类型杂质引入在所述第二导电类型晶体管形成区上的所述保护膜。 2. The method of claim l for manufacturing a semiconductor device, wherein said protective film is a non-doped silicon film; in the ninth step, also the first conductivity type impurity is introduced in the first the protective film on the conductive type transistor formation region; and in the tenth step, the second conductivity type impurity is also introduced on the second conductivity type transistor formation region of the protective film.
  3. 3. 根据权利要求l所述用于制造半导体器件的方法,其中,在所述第十步,还将所述第二导电类型杂质同步地引入在所述存储器单元区上的所述第二硅膜。 3. A method according to claim l for manufacturing a semiconductor device, wherein, in the tenth step, the second conductivity type impurity is also introduced into the region on the memory cell in synchronization with a second silicon membrane.
  4. 4. 根据权利要求3所述用于制造半导体器件的方法,其中, 在所述第十一步,将所述存储器单元区上的第二硅膜构图成电极形状,以便于连接至所述第一硅膜,以及形成沟槽栅电极,其中该沟槽栅电极包括所述第一硅膜和以所述电极形状构图的所述第二硅膜。 The method for manufacturing a semiconductor device according to claim 3, wherein, in the tenth step, the second silicon film on the memory cell region is patterned into an electrode shape, so as to be connected to the first a silicon film, and forming a trench gate electrode, wherein the first trench gate electrode comprising the silicon film and the electrode shape in the patterned second silicon film.
  5. 5. 根据权利要求1至4之中任一所述用于制造半导体器件的方法, 其中,所述第二栅绝缘膜比所述第一栅绝缘膜厚。 Among 1-4 according to any one of the method for manufacturing a semiconductor device as claimed in claim, wherein said second gate insulating film than the first gate insulating film thickness.
  6. 6. 根据权利要求1至4之中任一所述用于制造半导体器件的方法, 其中,所述存储器单元区上的所述第一栅绝缘膜的厚度大于所述外围电路区上的所述第一栅绝缘膜的厚度。 6. A method for manufacturing a semiconductor device according to one among claims 1 to 4, wherein a thickness of the memory cell region on the first gate insulating film is greater than the upper region of the peripheral circuit the first thickness of the gate insulating film.
  7. 7. 根据权利要求1至4之中任一所述用于制造半导体器件的方法, 其中,在所述第六步之后且所述第七步之前,通过使用所述掩模作为停止层进行剖光以将所述第一硅膜去除。 7. A method for manufacturing a semiconductor device according to one among claims 1 to 4, wherein, after said sixth step and before said seventh step, by using the mask layer as a stop section removing the first light to the silicon film.
  8. 8. 根据权利要求1至4之中任一所述用于制造半导体器件的方法, 其中在所述第一步之后,形成元件隔离区,该元件隔离区用于绝缘和隔离所述第一导电类型晶体管形成区、所述第二导电类型晶体管形成区和所述存储器单元区中的各区。 8. A method for manufacturing a semiconductor device according to one among claims 1 to 4, wherein after said first step, an element isolation region, the element isolation region for insulating and isolating said first conductive type transistor forming region, the second conductivity type transistor formation region and a region of the memory cell zones.
  9. 9. 根据权利要求8所述用于制造半导体器件的方法,其中, 所述元件隔离区具备STI结构;以及在所述掩模层内形成用于形成栅沟槽的所述开口之前,将所述掩模层作为形成用作所述元件隔离区的沟槽的掩模。 9. A method for manufacturing a semiconductor device according to claim 8, wherein the element isolation region STI structure comprising; prior to and forming a gate trench for forming an opening in the mask layer, The forming said mask layer as a trench element isolation region as the mask.
  10. 10. 根据权利要求1至4之中任一所述用于制造半导体器件的方法,其中,所述第五步包括:通过CVD方法淀积氧化硅膜的步骤;对所述氧化硅膜和所述半导体衬底之间的界面进行热氧化的步骤。 A method according to claim 10 for manufacturing a semiconductor device according to any one among 1-4, wherein said fifth step comprises the steps of: depositing by a CVD method, a silicon oxide film; the silicon film and the oxidation said interface between the semiconductor substrate in the step of thermal oxidation.
  11. 11. 一种用于制造半导体器件的方法,所述半导体器件包括存储器单元区、P型外围电路区和N型外围电路区;所述用于制造半导体器件的方法包括:第一步,以下述状态在所述存储器单元区内形成栅沟槽,所述状态是指第--栅绝缘膜和保护膜均覆盖所述P型外围电路区的和所述N 型外围电路区的半导体衬底;第二步,在所述栅沟槽的至少内壁上形成第二栅绝缘膜; 第三步,通过已掺杂的第一硅膜对所述栅沟槽的至少一部分进行填充:第四步,在所述保护膜上形成第二硅膜;以及第五步,分别将P型杂质和N型杂质引入在所述P型外围电路区和所述N型外围电路区上形成的所述第二硅膜内。 11. A method for manufacturing a semiconductor device, the semiconductor device includes a memory cell region, P-type and N-type region of the peripheral circuit the peripheral circuit region; the method for manufacturing a semiconductor device comprising: a first step, the following forming a gate trench in the state of the memory cell region, it refers to the state - of the gate insulating film and the protective film covering both the P-type peripheral circuit region and the N-type semiconductor substrate of the peripheral circuit region; the second step, a second gate insulating film is formed on at least an inner wall of the gate trench; a third step of filling at least a portion of the gate trench through the first doped silicon film: a fourth step, the second protective film, a silicon film is formed; and a fifth step, respectively, and the P-type impurity introduced into the N-type impurities is formed on the P-type region and a peripheral circuit of the peripheral circuit region of the second N-type silicon film.
  12. 12. 根据权利要求ll所述用于制造半导体器件的方法,其中,所述第一步包括:在形成所述第一栅绝缘膜和所述保护膜之后且在形成所述栅沟槽之前,形成元件隔离区,所述元件隔离区用于绝缘以及隔离所述存储器单元区、所述P型外围电路区以及所述N型外围电路区之各区。 12. The method of manufacturing a semiconductor device as claimed in claim ll of the used, wherein the first step comprises: a first gate insulating film before and after the protective film and is formed in the trench forming the gate, forming an element isolation region, said element isolation region for insulating and isolating the memory cell region, peripheral circuit region of the P-type and N-type zones of the peripheral circuit zone.
  13. 13. —种半导体器件,包括:半导体衬底,其具备存储器单元区、P型外围电路区以及N型外围电路区;在所述存储器单元区内形成的沟槽栅晶体管; 设置于所述P型外围电路区内的并带有P型栅电极的平面P沟道晶体管,其中所述P型栅电极包括在所述半导体衬底上通过第--栅绝缘膜所形成的P型多晶硅;以及设置于所述N型外围电路区内的并带有N型栅电极的平面N沟道晶体管,其中所述N型栅电极包括在所述半导体衬底上通过第一栅绝缘膜所形成的N型多晶硅;其中所述P型栅电极包括导电薄膜和在所述导电薄膜上形成的第一硅膜;所述N型栅电极包括所述导电薄膜和在所述导电薄膜上形成的第二硅膜;以及所述沟槽栅晶体管的栅电极包括:在提供至所述半导体衬底的栅沟槽的内壁上所形成的第二栅绝缘膜,以及在所述栅沟槽内通过所述第二栅绝缘膜所形成的第 13. - semiconductor device, comprising: a semiconductor substrate, which includes a memory cell region, P-type and N-type region of the peripheral circuit the peripheral circuit region; trench gate transistor formed in the memory cell region; disposed on the P type region and the peripheral circuit with a plane P-type P-channel transistor gate electrode, wherein the gate electrode comprises P-type on the semiconductor substrate through a first - P, polycrystalline silicon is formed a gate insulating film; and N-channel transistor and is provided with a planar N-type gate electrode in the peripheral circuit N-type region, wherein the gate electrode includes N-type N formed by a first gate insulating film on the semiconductor substrate, type polysilicon; wherein said P-type gate electrode comprises a first conductive thin film and a silicon film formed on the conductive film; the N-type gate electrode comprising the conductive thin film and the second silicon formed on the conductive film film; and a gate electrode of the trench gate transistor comprising: a second gate insulating film on the inner wall of the trench to provide the gate to the semiconductor substrate to be formed, and by the first within the gate trench the second gate insulating film is formed 硅膜。 Silicon film.
  14. 14. 根据权利要求13所述半导体器件,其中所述第二栅绝缘膜的厚度大于所述第一栅绝缘膜的厚度。 14. The semiconductor device according to claim 13, wherein a thickness of the second gate insulating film thicker than the first gate insulating film.
  15. 15. 根据权利要求13或14所述半导体器件,其中,所述第二栅绝缘膜包括CVD氧化硅膜和在所述CVD氧化硅膜的下方所形成的热氧化膜。 13 14 or 15. The semiconductor device according to claim, wherein said second gate insulating film comprises a silicon oxide film and a CVD oxide film below the thermal CVD silicon oxide film is formed.
  16. 16. 根据权利要求13或14所述半导体器件,其中所述导电薄膜是硅膜。 13 14 or 16. The semiconductor device according to claim, wherein said conductive film is a silicon film.
  17. 17. 根据权利要求13或14所述半导体器件,其中, 所述沟槽栅晶体管的栅电极进一步包括在所述第三硅膜上淀积的第四硅膜;所述第三硅膜是掺杂硅膜;以及通过离子注入将杂质注入进非掺杂硅膜,从而获得所述第四硅膜。 13 14 or 17. The semiconductor device according to claim, wherein the gate electrode of the trench gate transistor further comprises a fourth said third silicon film deposited silicon film; the third silicon film is doped heteroaryl silicon film; and the impurities implanted by ion implantation into the non-doped silicon film, thereby obtaining the fourth silicon film.
  18. 18. 根据权利要求13或14所述半导体器件,其中, 所述沟槽栅晶体管的栅电极进一步包括在所述第三硅膜上所淀积的金属膜;所述P型栅电极进一步包括在所述第一硅膜上成层的所述金属膜;以及所述N型栅电极进一步包括在所述第二硅膜上成层的所述金属膜。 13 14 or 18. The semiconductor device according to claim, wherein the gate trench gate electrode of the transistor further comprises a third metal film on said silicon film is deposited; the P-type gate electrode further comprises said first metal film into the silicon film layer; and the N-type gate electrode further comprises a second metal film on the silicon film into a layer.
  19. 19. 根据权利要求13或14所述半导体器件,其中,通过离子注入将杂质注入进非掺杂硅膜从而获得所述第一硅膜和所述第二硅膜。 13 14 or 19. The semiconductor device according to claim, wherein the impurity is implanted by ion implantation into the non-doped silicon film so as to obtain the first silicon film and the second silicon film.
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Citations (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US6414364B1 (en)
US6414364B2 (en) 1998-08-17 2002-07-02 Micron Technology, Inc. Isolation structure and process therefor
CN1650437A (en) 2002-05-03 2005-08-03 快捷半导体有限公司 Low voltage high density trench-gated power device with uniformly doped channel and its edge termination technique

Patent Citations (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US6414364B1 (en)
US6414364B2 (en) 1998-08-17 2002-07-02 Micron Technology, Inc. Isolation structure and process therefor
CN1650437A (en) 2002-05-03 2005-08-03 快捷半导体有限公司 Low voltage high density trench-gated power device with uniformly doped channel and its edge termination technique

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