CN100452411C - Semiconductor structure and producing method thereof - Google Patents
Semiconductor structure and producing method thereof Download PDFInfo
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- CN100452411C CN100452411C CNB2007100873722A CN200710087372A CN100452411C CN 100452411 C CN100452411 C CN 100452411C CN B2007100873722 A CNB2007100873722 A CN B2007100873722A CN 200710087372 A CN200710087372 A CN 200710087372A CN 100452411 C CN100452411 C CN 100452411C
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Abstract
This invention provides a semiconductor structure including a base plate, a grid set on the base plate, an insulation layer set on the base plate and covering said grid, a patternized semiconductor layer set on the insulation layer, a source and a drain set on said patternized semiconductor layer, a protection layer covering said insulation layer, said source and part borders covering said drain to expose part drain and a pixel electrode set on said base plate and covers said protection layer of said drain border and connected with the exposed drain. This invention provides a manufacturing method.
Description
Technical field
The invention relates to a kind of semiconductor structure, particularly about a kind of semiconductor structure and manufacture method thereof of avoiding the pixel electrode broken string.
Background technology
Fig. 1 is the vertical view of known semiconductor structure.Fig. 2 A is the generalized section of Fig. 1 along A-A ' hatching gained.And Fig. 2 A～Fig. 2 D is the manufacture method of known semiconductor structure.
See also Fig. 1 and Fig. 2 A, at first, provide a substrate 1.Afterwards, form one first metal wire 2 on substrate 1.First metal wire 2 can be grid line (gate line) or common wire (common line).Then, form an insulating barrier 3 on substrate 1, and cover first metal wire 2.Afterwards, form semi-conductor layer 4 on insulating barrier 3.Then, form one second metal wire 5 on semiconductor layer 4.Afterwards, form a protective layer 6 on second metal wire 5.Then, form a photoresist layer 7 on protective layer 6, cover first metal wire 2, exposed portions serve insulating barrier 3, semiconductor layer 4, second metal wire 5 and protective layer 6.
Then, seeing also Fig. 2 B, is a mask with photoresist layer 7, from top to bottom defines protective layer 6, second metal wire 5, semiconductor layer 4 and insulating barrier 3, and exposes substrate 1.Because insulating barrier 3 is different with the material of second metal wire 5 and semiconductor layer 4, cause when carrying out the etching definition, different etch-rates is arranged, and make the interface between the relatively slow semiconductor layer 4 of the comparatively faster insulating barrier 3 of etch-rate and etch-rate produce non-continuous event, promptly so-called undercutting (under cut) 8.
After removing part photoresist layer 7 as Fig. 2 C, deposit an indium tin oxidizing electrode 9 in photoresist layer 7, protective layer 6, second metal wire 5, semiconductor layer 4 and substrate 1 surface, shown in Fig. 2 D.It should be noted that because insulating barrier 3 and the undercutting (under cut) that semiconductor layer 4 interfaces produce, make the indium tin oxidizing electrode 9 that is deposited on the substrate 1 and be deposited on the indium tin oxidizing electrode 9 that other layer do not go up and form continuous morphology, and cause broken string 19.
Summary of the invention
The invention provides a kind of semiconductor structure, comprising: a substrate; One grid is arranged on this substrate; One insulating barrier is arranged on this substrate and covers this grid; One patterned semiconductor layer is arranged on this insulating barrier; An one source pole and a drain electrode are arranged on this patterned semiconductor layer; One protective layer covers this insulating barrier, this source electrode and is covered in the segment boundary of this drain electrode, and exposed portions serve should drain electrode; And a pixel electrode, be arranged on this substrate and cover this protective layer of this grain boundaries, and electrically connect with this drain electrode of exposing.
The present invention provides a kind of manufacture method of semiconductor structure in addition, comprising: a substrate is provided; Form one and comprise the active element of a drain electrode on this substrate; Form a protective layer on this substrate, and cover this active element; Form a photoresist layer on this protective layer, this photoresist layer has one first thickness and one second thickness, and this first thickness is greater than this second thickness, and this photoresist layer that wherein has this second thickness covers the segment boundary of this drain electrode; With this photoresist layer is a mask, defines this protective layer, to expose this substrate and this drain electrode of part; Reduce the thickness of this photoresist layer,, make this protective layer of part cover the segment boundary of this drain electrode to remove this photoresist layer with this second thickness; Deposit a transparency conducting layer in this substrate and cover this protective layer of this grain boundaries, and electrically connect with this drain electrode of exposing; And remove remaining this photoresist layer and this transparency conducting layer on it, to form a pixel electrode.
For above-mentioned purpose of the present invention, feature and advantage can be become apparent, a preferred embodiment cited below particularly, and conjunction with figs. are described in detail below.
Description of drawings
Fig. 1 is the vertical view of known semiconductor structure;
Fig. 2 A～Fig. 2 D is the manufacture method of known semiconductor structure;
Fig. 3 is the generalized section of semiconductor structure of the present invention;
Fig. 4 is the generalized section of semiconductor structure of the present invention;
Fig. 5 A～Fig. 5 E is the manufacture method of semiconductor structure of the present invention;
Fig. 6 is the vertical view of Fig. 5 B structure;
Fig. 7 A～Fig. 7 E is the manufacture method of semiconductor structure of the present invention;
Fig. 8 is the vertical view of Fig. 7 A and Fig. 7 B structure;
The form that Fig. 9 A and Fig. 9 B are provided with for photoresist layer of the present invention.
Wherein, Reference numeral is:
Known Fig. 1 and Fig. 2 A～Fig. 2 D:
1～substrate; 2～the first metal wires;
3～insulating barrier; 4～semiconductor layer;
5～the second metal wires; 6～protective layer;
7～photoresist layer; 8～undercutting;
9～indium tin oxidizing electrode; 19～broken string.
Fig. 3 of the present invention, Fig. 4, Fig. 5 A～Fig. 5 E, Fig. 6, Fig. 7 A～Fig. 7 E, Fig. 8, Fig. 9 A and Fig. 9 B:
10,100～semiconductor structure; 12,120～substrate;
14,140～grid; 16,160～insulating barrier;
18,180～patterned semiconductor layer; 20,200～source electrode;
22,220～drain electrode;
24,24 ', 24 ", 240,240 '～protective layer;
25,250～transparency conducting layer; 26,260～pixel electrode;
28,280～electric capacity; 30,300～the first metal wires;
32～the second metal wires; 34,340～active element;
36,36 ', 36 ", 38,38 ', 38 ", 360,360 ', 360 ", 380～photoresist layer;
H, h1, h2, h3, h4～photoresist layer thickness.
Embodiment
Fig. 3 is the generalized section according to an embodiment of semiconductor structure of the present invention.See also Fig. 3, semiconductor structure 10 comprises a substrate 12, a grid 14, an insulating barrier 16, a patterned semiconductor layer 18, one source pole 20, drain electrode 22, one protective layer 24 and a pixel electrode 26.Substrate 12 can be a glass substrate.Insulating barrier 16 can comprise silica, silicon nitride or silicon oxynitride with protective layer 24.
Fig. 4 is the generalized section according to another embodiment of semiconductor structure of the present invention.See also Fig. 4, semiconductor structure 100 comprises a substrate 120, a grid 140, an insulating barrier 160, a patterned semiconductor layer 180, one source pole 200, drain electrode 220, one protective layer 240 and a pixel electrode 260.Substrate 120 can be a glass substrate.Insulating barrier 160 can comprise silica, silicon nitride or silicon oxynitride with protective layer 240.
The manufacture method of Fig. 5 A～Fig. 5 E explanation semiconductor structure of the present invention.See also Fig. 5 A, at first, provide a substrate 12.Afterwards, form one and comprise the active element 34 of a drain electrode 22 on substrate 12.Then, form a protective layer 24 on substrate 12, and cover active element 34.Afterwards, form a photoresist layer 36 on protective layer 24.Photoresist layer 36 has one first thickness h 1 and one second thickness h 2, and first thickness h 1 is greater than second thickness h 2.The photoresist layer 36 that wherein has second thickness h 2 " cover the segment boundary of drain electrode 22.Then, be a mask with photoresist layer 36, definition protective layer 24 is to expose substrate 12 and partly to drain 22, shown in Fig. 5 B.Simultaneously, please contrast Fig. 6, the plan structure in the right half of active element of key diagram 5B district (the right half of active element of Fig. 5 B district is the generalized section of Fig. 6 along A-A ' hatching gained).Can clearlyer find out to have the photoresist layer 36 of second thickness h 2 by Fig. 6 " position of its covering is positioned at the boundary of drain electrode 22.
Wait to remove photoresist layer 36 with second thickness h 2 " after, partial protection layer 24 ' promptly covers the segment boundary of drain electrode 22, shown in Fig. 5 C.
See also Fig. 5 D, deposit the protective layer 24 ' of a transparency conducting layer 25, and electrically connect with the drain electrode 22 of exposing in substrate 12 and covering drain electrode 22 borders.
See also Fig. 5 E, remove remaining photoresist layer 36 ' and the transparency conducting layer 25 on it, to form a pixel electrode 26.
Below be described in more detail at above-mentioned each processing step.See also Fig. 5 A, the step of above-mentioned formation active element 34 is described.At first, form a grid 14 on substrate 12.Then, form an insulating barrier 16 on substrate 12, and cover gate 14.Afterwards, form a patterned semiconductor layer 18 on insulating barrier 16.Then, form an one source pole 20 and a drain electrode 22 on the patterned semiconductor layer 18 of grid 14 both sides.The step that wherein forms grid 14 also comprises formation one the first metal layer (not shown) on substrate 12, and the patterning the first metal layer, to form grid 14.
In addition, formation patterned semiconductor layer 18, source electrode 20 comprise also that with the step of drain electrode 22 formation semi-conductor layer (not shown) is on insulating barrier 16.Then, form one second metal level (not shown) on semiconductor layer.Afterwards, form a photoresist layer (not shown) on second metal level.Photoresist layer has two different-thickness.The photoresist layer that wherein has big thickness covers the predetermined position that forms source electrode 20 and drain electrode 22 of second metal level.Then, be a mask with photoresist layer, define the semiconductor layer and second metal level simultaneously.After waiting to remove photoresist layer, promptly form patterned semiconductor layer 18, source electrode 20 and drain electrode 22.
The manufacture method of semiconductor structure of the present invention comprises that also formation one electric capacity is on substrate.Fig. 5 A, Fig. 5 C and Fig. 5 E explanation form the step of electric capacity on substrate.See also Fig. 5 A, at first, form one first metal wire 30 on substrate 12.Then, cover insulating barrier 16 in first metal wire 30.Afterwards, form one second metal wire 32 on insulating barrier 16.Then, form protective layer 24 on second metal wire 32.Afterwards; define protective layer 24 on second metal wire 32 with half accent type (half-tone) or tone type (gray-tone) mask process; so that protective layer 24 " cover the segment boundary of second metal wire 32, and exposed portions serve second metal wire 32, shown in Fig. 5 C.
See also Fig. 5 E, cover pixel electrode 26 in the protective layer 24 on second metal wire, 32 borders ", and electrically connect with second metal wire 32 that exposes.
Above-mentioned to define the step of the online protective layer of second metal with half accent type (half-tone) or tone type (gray-tone) mask process identical, can explain by Fig. 5 A～Fig. 5 E.See also Fig. 5 A, at first, form a photoresist layer 38 on the protective layer 24 on second metal wire 32.Photoresist layer 38 has one the 3rd thickness h 3 and one the 4th thickness h 4, and the 3rd thickness h 3 is greater than the 4th thickness h 4.The photoresist layer 38 that wherein has the 4th thickness h 4 " cover the segment boundary of second metal wire 32.Then, be a mask with photoresist layer 38, definition protective layer 24 is with exposed portions serve second metal wire 32, shown in Fig. 5 B.Simultaneously, please contrast Fig. 6, the plan structure of the half of capacitive region in a key diagram 5B left side (the half of capacitive region in Fig. 5 B left side is the generalized section of Fig. 6 along B-B ' hatching gained).Can clearlyer find out to have the photoresist layer 38 of the 4th thickness h 4 by Fig. 6 " position of its covering, be positioned at the boundary of second metal wire 32 really.Find behind the semiconductor structure of Fig. 6 of the present invention and known Fig. 1 that relatively both are obviously different, its discrepancy is that the photoresist layer 38 of Fig. 6 of the present invention has two different-thickness, and the photoresist layer of less thickness is positioned at the boundary of second metal wire 32.Yet the photoresist layer 7 of known Fig. 1 only has single thickness, and on the border of second metal wire 5, there is no any photoresist layer is set.In addition, the photoresist layer 38 of Fig. 6 " be positioned at the border of second metal wire, 32 centers, yet the present invention is not limited to this, has the photoresist layer 38 of less thickness " also can be arranged at the position on for example right half of or left half of border of second metal wire 32.
Wait to remove photoresist layer 38 with the 4th thickness h 4 " after, protective layer 24 " promptly cover the segment boundary of second metal wire 32, shown in Fig. 5 C.
See also Fig. 5 D, deposit transparent conductive layer 25 goes up and covers the protective layer 24 on second metal wire, 32 borders in remaining photoresist layer 38 ' ", and electrically connect with second metal wire 32 that exposes.
See also Fig. 5 E, remove remaining photoresist layer 38 ' and the transparency conducting layer 25 on it.
Above-mentioned formation electric capacity 28 comprises also that in the step on the substrate 12 formation patterned semiconductor layer 18 is between the insulating barrier 16 and second metal wire 32.
The manufacture method of Fig. 7 A～Fig. 7 E explanation semiconductor structure of the present invention.See also Fig. 7 A, at first, provide a substrate 120.Afterwards, form one and comprise the active element 340 of a drain electrode 220 on substrate 120.Then, form a protective layer 240 on substrate 120, and cover active element 340.Afterwards, form a photoresist layer 360 on protective layer 240.Photoresist layer 360 has one first thickness h 1 and one second thickness h 2, and first thickness h 1 is greater than second thickness h 2.The photoresist layer 360 that wherein has second thickness h 2 " cover the segment boundary of drain electrode 220.Then, be a mask with photoresist layer 360, definition protective layer 240 is to expose substrate 120 and partly to drain 220, shown in Fig. 7 B.Simultaneously, please contrast Fig. 8, the plan structure in the right half of active element of key diagram 7B district (the right half of active element of Fig. 7 B district is the generalized section of Fig. 8 along A-A ' hatching gained).Can clearlyer find out to have the photoresist layer 360 of second thickness h 2 by Fig. 8 " position of its covering is positioned at the boundary of drain electrode 220.Yet the present invention has the photoresist layer 360 of less thickness " setting also can comprise shown in Fig. 9 A, Fig. 9 B different shape across drain electrode 220 borders.
Wait to remove photoresist layer 360 with second thickness h 2 " after, partial protection layer 240 ' promptly covers the segment boundary of drain electrode 220, shown in Fig. 7 C.
See also Fig. 7 D, deposit the protective layer 240 ' of a transparency conducting layer 250, and electrically connect with the drain electrode 220 of exposing in substrate 120 and covering drain electrode 220 borders.
See also Fig. 7 E, remove remaining photoresist layer 360 ' and the transparency conducting layer 250 on it, to form a pixel electrode 260.
Below be described in more detail at above-mentioned each processing step.See also Fig. 7 A, the step of above-mentioned formation active element 340 is described.At first, form a grid 140 on substrate 120.Then, form an insulating barrier 160 on substrate 120, and cover gate 140.Afterwards, form a patterned semiconductor layer 180 on insulating barrier 160.Then, form an one source pole 200 and a drain electrode 220 on the patterned semiconductor layer 180 of grid 140 both sides.The step that wherein forms grid 140 also comprises formation one the first metal layer (not shown) on substrate 120, and the patterning the first metal layer, to form grid 140.
In addition, formation patterned semiconductor layer 180, source electrode 200 comprise also that with the step of drain electrode 220 formation semi-conductor layer (not shown) is on insulating barrier 160.Then, form one second metal level (not shown) on semiconductor layer.Afterwards, form a photoresist layer (not shown) on second metal level.Photoresist layer has two different-thickness.The photoresist layer that wherein has big thickness covers the predetermined position that forms source electrode 200 and drain electrode 220 of second metal level.Then, be a mask with photoresist layer, define the semiconductor layer and second metal level simultaneously.After waiting to remove photoresist layer, promptly form patterned semiconductor layer 180, source electrode 200 and drain electrode 220.
The manufacture method of semiconductor structure of the present invention comprises that also formation one electric capacity is on substrate.Fig. 7 A, Fig. 7 C and Fig. 7 E explanation form the step of electric capacity on substrate.See also Fig. 7 A, at first, form one first metal wire 300 on substrate 120.Then, cover insulating barrier 160 in first metal wire 300.Afterwards, form protective layer 240 on insulating barrier 160, and utilize half accent type (half-tone) or tone type (gray-tone) mask process to make protective layer 240 extend the segment boundary that covers to first metal wire 300, shown in Fig. 7 C.
See also Fig. 7 E, pixel deposition electrode 260 is on protective layer 240.
Above-mentioned utilization half accent type (half-tone) or tone type (gray-tone) mask process can explain protective layer extension covering to the step of the segment boundary of first metal wire by Fig. 7 A, Fig. 7 C and Fig. 7 D.See also Fig. 7 A, at first, form a photoresist layer 380 on the protective layer on the insulating barrier 160 240.Photoresist layer 380 only has a thickness h identical with second thickness h 2.Photoresist layer 380 extends the segment boundary that covers to first metal wire 300.Simultaneously, please contrast Fig. 8, the plan structure of the half of capacitive region in a key diagram 7A left side (the half of capacitive region in Fig. 7 A left side is the generalized section of Fig. 8 along B-B ' hatching gained).Can clearlyer find out to have the position of photoresist layer 380 its coverings of thickness h by Fig. 8, extend to the boundary of first metal wire 300 really.
After waiting to remove photoresist layer 380, protective layer 240 promptly extends the segment boundary that covers to first metal wire 300, shown in Fig. 7 C.
See also Fig. 7 D, deposit transparent conductive layer 250 is on protective layer 240.
The manufacture method of semiconductor structure of the present invention owing to utilize the design of different photoresist layer thickness, make originally must four to five times the gold-tinted step only be reduced to must three times, help that productive rate promotes and the reduction of cost.And this technology and metal-insulator-metal (metal-insulator-metal, MIM) electric capacity and metal-insulator layer-indium tin oxidation (metal-insulator-ITO, MII) compatible making of electric capacity.The more important thing is, the problem of known indium tin oxidizing electrode broken string, can be easily by adjusting different photoresist layer thickness and photoresist layer being arranged on drain electrode or the borderline protective layer of metal wire is solved.In addition, the present invention only must provide among a small circle half accent type (half-tone) or tone type (gray-tone) mask can reach above-mentioned effect.
Though the present invention with preferred embodiment openly as above; yet it is not in order to limit the present invention; any those of ordinary skill in the art; without departing from the spirit and scope of the present invention; when can doing to change and retouching, so protection scope of the present invention is as the criterion when looking the accompanying Claim book person of defining.
Claims (13)
1, a kind of manufacture method of semiconductor structure is characterized in that, comprising:
One substrate is provided;
Form one and comprise the active element of a drain electrode on this substrate;
Form a protective layer on this substrate, and cover this active element;
Form a photoresist layer on this protective layer, this photoresist layer has one first thickness and one second thickness, and this first thickness is greater than this second thickness, and this photoresist layer that wherein has this second thickness covers the segment boundary of this drain electrode;
With this photoresist layer is a mask, defines this protective layer, to expose this substrate and this drain electrode of part;
Reduce the thickness of this photoresist layer,, make this protective layer of part cover the segment boundary of this drain electrode to remove this photoresist layer with this second thickness;
Deposit a transparency conducting layer in this substrate and cover this protective layer of this grain boundaries, and electrically connect with this drain electrode of exposing; And
Remove remaining this photoresist layer and this transparency conducting layer on it, to form a pixel electrode.
2, the manufacture method of semiconductor structure according to claim 1 is characterized in that, the step that forms this active element comprises:
Form a grid on this substrate;
Form an insulating barrier on this substrate, and cover this grid;
Form a patterned semiconductor layer on this insulating barrier; And
Forming one source pole and drains on this patterned semiconductor layer of these grid both sides.
3, the manufacture method of semiconductor structure according to claim 2 is characterized in that, the step that forms this grid comprises:
Form a first metal layer on this substrate; And
This first metal layer of patterning is to form this grid.
4, the manufacture method of semiconductor structure according to claim 2 is characterized in that, the step that forms this patterned semiconductor layer, this source electrode and this drain electrode comprises:
Form semi-conductor layer on this insulating barrier;
Form one second metal level on this semiconductor layer; And
Define this semiconductor layer and this second metal level with half accent type or tone type mask process, to form this patterned semiconductor layer, this source electrode and this drain electrode.
5, the manufacture method of semiconductor structure according to claim 2 is characterized in that, more comprises forming an electric capacity on this substrate.
6, the manufacture method of semiconductor structure according to claim 5 is characterized in that, forms the step of this electric capacity on this substrate and comprises:
Form one first metal wire on this substrate;
Cover this insulating barrier in this first metal wire;
Form one second metal wire on this insulating barrier;
Form this protective layer on this second metal wire;
Define this protective layer on this second metal wire with half accent type or tone type mask process, so that this protective layer covers the segment boundary of this second metal wire, and this second metal wire of exposed portions serve; And
Cover this pixel electrode this protective layer, and electrically connect with this second metal wire that exposes in this second metal wire border.
7, the manufacture method of semiconductor structure according to claim 6 is characterized in that, the step that defines this protective layer on this second metal wire with half accent type or tone type mask process comprises:
Form another photoresist layer on this protective layer on this second metal wire, this another photoresist layer has one the 3rd thickness and one the 4th thickness, and the 3rd thickness is greater than the 4th thickness, and this photoresist layer that wherein has the 4th thickness covers the segment boundary of this second metal wire;
With this another photoresist layer is a mask, defines this protective layer with this second metal wire of exposed portions serve;
Reduce the thickness of this another photoresist layer,, make this protective layer cover the segment boundary of this second metal wire to remove this another photoresist layer with the 4th thickness;
Deposit this transparency conducting layer on remaining this another photoresist layer and cover this protective layer on this second metal wire border, and electrically connect with this second metal wire that exposes; And
Remove remaining this another photoresist layer and this transparency conducting layer on it.
8, the manufacture method of semiconductor structure according to claim 6 is characterized in that, this first metal wire and this grid form simultaneously.
9, the manufacture method of semiconductor structure according to claim 6 is characterized in that, this first metal wire comprises grid line or common wire.
10, the manufacture method of semiconductor structure according to claim 6 is characterized in that, this second metal wire and this source electrode form simultaneously with drain electrode.
11, the manufacture method of semiconductor structure according to claim 6 is characterized in that, forms the step of this electric capacity on this substrate, more comprises forming this patterned semiconductor layer between this insulating barrier and this second metal wire.
12, the manufacture method of semiconductor structure according to claim 5 is characterized in that, forms the step of this electric capacity on this substrate and comprises:
Form one first metal wire on this substrate;
Cover this insulating barrier on this first metal wire;
Form this protective layer on this insulating barrier, and make this protective layer extend the segment boundary that covers to this first metal wire; And
Deposit this pixel electrode on this protective layer.
13, the manufacture method of semiconductor structure according to claim 12 is characterized in that, this first metal wire comprises grid line or common wire.
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| CNB2007100873722A CN100452411C (en) | 2007-03-14 | 2007-03-14 | Semiconductor structure and producing method thereof |
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| CNB2007100873722A CN100452411C (en) | 2007-03-14 | 2007-03-14 | Semiconductor structure and producing method thereof |
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| CN2008102139189A Division CN101359672B (en) | 2007-03-14 | 2007-03-14 | Semiconductor structure |
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| CN101226932B (en) * | 2008-02-18 | 2010-10-27 | 友达光电股份有限公司 | Pixel structure and manufacturing method thereof |
| CN105097826A (en) * | 2015-06-04 | 2015-11-25 | 京东方科技集团股份有限公司 | Gate driver on array (GOA) unit, fabrication method thereof, display substrate and display device |
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| US20050140858A1 (en) * | 2003-12-30 | 2005-06-30 | Lg Philips Lcd Co., Ltd. | Liquid crystal display device and method of manufacturing the same |
| US20050170592A1 (en) * | 1999-04-08 | 2005-08-04 | Bum-Ki Baek | Thin film transistor array panels for a liquid crystal display and a method for manufacturing the same |
| CN1747171A (en) * | 2004-09-09 | 2006-03-15 | Lg.菲利浦Lcd株式会社 | Thin film transistor array substrate and fabricating method thereof |
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| US20050170592A1 (en) * | 1999-04-08 | 2005-08-04 | Bum-Ki Baek | Thin film transistor array panels for a liquid crystal display and a method for manufacturing the same |
| US6451635B2 (en) * | 2000-03-13 | 2002-09-17 | Samsung Electronics Co., Ltd. | Photolithography system and a method for fabricating a thin film transistor array substrate using the same |
| US20050140858A1 (en) * | 2003-12-30 | 2005-06-30 | Lg Philips Lcd Co., Ltd. | Liquid crystal display device and method of manufacturing the same |
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