CN100452356C - Nonvolatile memory unit, manufacturing method, and opertion method - Google Patents
Nonvolatile memory unit, manufacturing method, and opertion method Download PDFInfo
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- CN100452356C CN100452356C CNB2005100921290A CN200510092129A CN100452356C CN 100452356 C CN100452356 C CN 100452356C CN B2005100921290 A CNB2005100921290 A CN B2005100921290A CN 200510092129 A CN200510092129 A CN 200510092129A CN 100452356 C CN100452356 C CN 100452356C
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Abstract
The non-volatile memory is at least composed of substrate, storage unit, and regions of source pole/drain pole. Including at least first memory unit and second memory unit, the storage unit is setup on the substrate. First memory unit includes floating grid and first control grid started from substrate. Including charge trapping layer and second control grid, second memory unit is setup on sidewall of first memory unit. Regions of source pole/drain pole are setup on substrate on two sides of storage unit.
Description
Technical field
The present invention relates to a kind of semiconductor element, particularly relate to a kind of non-volatility memorizer and manufacture method thereof and method of operation.
Background technology
Can electricity erasing and programmable read only memory (EEPROM) has the actions such as depositing in, read, erase that can carry out repeatedly data in the non-volatility memorizer, and the advantage that the data that deposit in also can not disappear after outage, thus become personal computer and electronic equipment a kind of memory component of extensively adopting.
Typically can erase and polysilicon (polysilicon) the making floating grid (floating gate) and control grid (control gate) of programmable read only memory by electricity to mix.By applying bias voltage, operate for this read-only memory in control grid and source/drain regions.Yet, because this kind read-only memory memory is easy to generate excessively the problem of (over-erase) of erasing, and causes the erroneous judgement of data when carrying out the erasing of data.Moreover, in order to meet the trend of current semiconductor industry towards high integration, the size of memory is dwindled, the length of passage is also shorter and shorter, so when this memory cell of sequencing, abnormal electrical perforation (punch through) just takes place between drain region and the source area easily, so will have a strong impact on the electrical performance of memory.
In the prior art, also there is the silicon nitride layer of employing to replace polysilicon floating gate, and forms silicon oxide/silicon nitride/silicon oxide (oxide-nitride-oxide is called for short ON0) composite bed.This kind element is commonly referred to as silicon/oxidative silicon/nitrogenize silicon/oxidative silicon/silicon (SONOS) element.Because silicon nitride has the characteristic of catching electronics, therefore, the electronics that injects silicon nitride layer can't be uniformly distributed among the whole layer, but concentrates on the regional area of silicon nitride layer.By the voltage that is applied on the source/drain regions that changes grid and its both sides, just can be among the single silicon nitride layer in the and arranged on left and right sides of memory, respectively deposit a position in, and constitute the non-volatility memorizer of two (2bits/cell) storages of a kind of single memory cell.
Yet said memory cells can face the memory cell integrated level equally and promote the situation that passage length is shorter and shorter.Under this situation, two positions of memory cell can interact each other, make the charge-distribution curve of two positions become wide and link together, and produce so-called second effect (second biteffect).Therefore, when erasing, injecting the formed distribution curve of hot hole in silicon nitride layer can't coincide together with electron distribution curve, and cause erasing fully and the problem of needs than the long time of erasing.This problem also may reduce the reliability (reliability) of element except the service speed that causes memory descends, usefulness is relatively poor.
By above explanation as can be known, a kind of can have the non-volatility memorizer that the single memory cell multidigit stores, and don't can produce second effect or aforementionedly excessively erase, the electrical memory of problem such as perforation, will be the needed innovation of industry.
Summary of the invention
In view of this, purpose of the present invention is providing a kind of non-volatility memorizer exactly, can store bits of data in single memory cell, and can not produce the problem of second effect.
Another purpose of the present invention provides a kind of manufacture method of non-volatility memorizer, and the step of technology is simple, and the memory of manufacturing can not take place excessively to erase or electrical problem such as perforation.
Another object of the present invention provides a kind of method of operation of non-volatility memorizer, the efficient height of its operator scheme, and the required voltage that applies is low, can save power consumption, improves the running speed of element.
The present invention proposes a kind of non-volatility memorizer, and it is made of substrate, memory cell and source/drain regions.Memory cell is arranged in the substrate, and memory cell for example is to comprise first memory cell and second memory cell.Wherein, first memory cell by substrate rise at least for example be comprise floating grid and first control grid.Second memory cell is arranged at a sidewall of first memory cell, and second memory cell is risen by substrate and comprises the charge immersing layer and the second control grid.Source/drain regions is arranged in the memory cell substrate on two sides.
According to the described non-volatility memorizer of embodiments of the invention, above-mentioned second memory cell comprises a charge trapping structure, charge trapping structure comprises charge immersing layer, and charge trapping structure is arranged between the second control grid and the substrate, and extends between the second control grid and first memory cell.
According to the described non-volatility memorizer of embodiments of the invention, it for example is to comprise tunneling dielectric layer, charge immersing layer and stop dielectric layer that above-mentioned charge trapping structure is risen by substrate.Wherein the material of charge immersing layer for example is a silicon nitride.
According to the described non-volatility memorizer of embodiments of the invention, comprise one dielectric layer between above-mentioned floating grid and the substrate.Comprise dielectric layer between one deck grid between above-mentioned first control grid and the floating grid.The material of dielectric layer for example is a silicon oxide/silicon nitride/silicon oxide between grid.
According to the described non-volatility memorizer of embodiments of the invention, the material of above-mentioned floating grid for example is a doped polycrystalline silicon.The material of the above-mentioned first control grid and the second control grid can be a doped polycrystalline silicon.
Non-volatility memorizer of the present invention, in conjunction with first memory cell and second memory cell, can avoid existing and can electricity erase and programmable read only memory can produce the problem of excessively erasing, and second effect can not take place, and be able in single memory cell, store two positions.
The present invention proposes a kind of manufacture method of non-volatility memorizer, and a substrate at first is provided.Form first memory cell afterwards in substrate, first memory cell is risen by substrate and comprises the dielectric layer and the first control grid between dielectric layer, floating grid, grid.Then, in substrate, form charge trapping structure, in substrate, form one deck conductor layer again.Then, remove the segment conductor layer, form the second control grid with the sidewall in first memory cell, this charge trapping structure and this second control grid constitute one second memory cell.Then, in the not adjacent side of first memory cell with second memory cell, and not adjacent with first memory cell side of second memory cell, form two doped regions.
According to the manufacture method of the described non-volatility memorizer of embodiments of the invention, on be set forth in before the step that forms first memory cell, can also in substrate, form N type well region.Cooperate N type well region, above-mentioned two doped regions are P type doped region.
According to the manufacture method of the described non-volatility memorizer of embodiments of the invention, above-mentioned charge trapping structure is risen by substrate and comprises tunneling dielectric layer, charge immersing layer and stop dielectric layer.The material of charge immersing layer for example is a silicon nitride.
According to the manufacture method of the described non-volatility memorizer of embodiments of the invention, the above-mentioned method that removes the segment conductor layer for example is to be etch stop layer with the charge trapping structure earlier, removes the conductor layer on first memory cell.In substrate, form patterning photoresist layer afterwards, cover the conductor layer of the sidewall of first memory cell.Then, be mask with patterning photoresist layer, remove the conductor layer that exposes.The above-mentioned method that removes the conductor layer that exposes comprises anisotropic etch process
The manufacture method of above-mentioned non-volatility memorizer, because charge trapping structure is different with the etching selectivity of conductor layer, therefore can be with charge trapping structure as alignment mask voluntarily, remove the conductor layer on first memory cell, its processing step is simple, can reach the effect that prevents that memory from electrically connecting again.
The present invention proposes a kind of method of operation of P type channel memory, and this P type channel memory comprises the N type well region that is arranged in the substrate; Be arranged at the memory cell on the N type well region, memory cell for example is to comprise first memory cell, second memory cell with a sidewall that is arranged at first memory cell, wherein, first memory cell is risen by substrate and comprises the floating grid and the first control grid at least, second memory cell is risen by substrate and comprises the charge immersing layer and the second control grid at least, and floating grid is suitable for storing first, and charge immersing layer is suitable for storing second; Be arranged at first source/drain regions and second source/drain regions in the N type well region of memory cell both sides.This method of operation comprises:
When carrying out programming operations, apply first voltage in first source/drain regions, apply second voltage in second source/drain regions, apply tertiary voltage in the first control grid, apply the 4th voltage, apply the 5th voltage in N type well region in the second control grid, wherein tertiary voltage is greater than first voltage, bring out the hot electron injection effect between valence band-conduction band to utilize, electronics is injected floating grid, deposit first in.
According to the method for operation of the described non-volatility memorizer of embodiments of the invention, above-mentioned first voltage is negative voltage, and tertiary voltage is a positive voltage.First voltage is about-5 volts, and second voltage is about 0 volt, and tertiary voltage is about 6 volts, and the 4th voltage is about 0 volt, and the 5th voltage is about 0 volt.
Method of operation according to the described non-volatility memorizer of embodiments of the invention, on be set forth in when carrying out programming operations, also be included in first source/drain regions and apply first voltage, apply second voltage in second source/drain regions, apply the 6th voltage in the first control grid, apply the 7th voltage in the second control grid, apply the 5th voltage in N type well region, wherein the 7th voltage is greater than first voltage, first voltage is greater than the 6th voltage, to utilize the passage hot hole to bring out the hot electron injection effect,, deposit second in electronics iunjected charge immersed layer.
According to the method for operation of the described non-volatility memorizer of embodiments of the invention, above-mentioned the 6th voltage is about-12 volts, and the 7th voltage is about-1 volt.
Method of operation according to the described non-volatility memorizer of embodiments of the invention, on be set forth in when carrying out erase operation for use, apply the 8th voltage in second source/drain regions, apply the 9th voltage in the first control grid, apply the tenth voltage in the second control grid, apply the 11 voltage in N type well region, first source/drain regions is floated, wherein the 9th voltage and the tenth voltage are less than the 11 voltage, to utilize passage FN tunneling effect, to be stored in the electronics of floating grid and charge immersing layer, import in the N type well region.
According to the method for operation of the described non-volatility memorizer of embodiments of the invention, above-mentioned the 8th voltage is about 0 volt, and the 9th voltage is about-15 volts, and the tenth voltage is about-15 volts, and the 11 voltage is about 0 volt.
Method of operation according to the described non-volatility memorizer of embodiments of the invention, on be set forth in when carrying out read operation, apply the 12 voltage in first source/drain regions, apply the 13 voltage in second source/drain regions, apply the 14 voltage in the first control grid, apply the 15 voltage in the second control grid, apply the 16 voltage in N type well region, wherein the 15 voltage is less than the 14 voltage, and the 14 voltage is less than the 13 voltage, opening the passage of second memory cell below, and read in the floating grid first.
Method of operation according to the described non-volatility memorizer of embodiments of the invention, above-mentioned the 12 voltage is about 0 volt, and the 13 voltage is about-1.5 volts, and the 14 voltage is about-3 volts, the 15 voltage is about-6 volts, and the 16 voltage is about 0 volt.
Method of operation according to the described non-volatility memorizer of embodiments of the invention, on be set forth in when carrying out read operation, also be included in first source/drain regions and apply the 12 voltage, apply the 13 voltage in second source/drain regions, apply the 17 voltage in the first control grid, apply the 18 voltage in the second control grid, apply the 16 voltage in N type well region, wherein the 17 voltage is less than the 18 voltage, and the 18 voltage is less than the 13 voltage, opening the passage of first memory cell below, and in the reading electric charges immersed layer second.
According to the method for operation of the described non-volatility memorizer of embodiments of the invention, above-mentioned the 17 voltage is about-6 volts, and the 18 voltage is about-3 volts.
The method of operation of non-volatility memorizer of the present invention, sequencing of being adopted and the operator scheme of erasing, efficient is higher, can more promptly electronics be injected or pull out, so be minimized the operating voltage of memory, reduce the consumption of power, improve the running speed of element.
For above and other objects of the present invention, feature and advantage can be become apparent, embodiment cited below particularly, and conjunction with figs. is described in detail below.
Description of drawings
Fig. 1 is the section of structure that illustrates a kind of non-volatility memorizer of one embodiment of the invention.
Fig. 2 A to Fig. 2 E is the manufacturing process profile that illustrates a kind of non-volatility memorizer of one embodiment of the invention.
Fig. 3 A is left the programming operations schematic diagram that illustrates a kind of P type channel memory of one embodiment of the invention.
Fig. 3 B is right the programming operations schematic diagram that illustrates a kind of P type channel memory of one embodiment of the invention.
Fig. 3 C is left the read operation schematic diagram that illustrates a kind of P type channel memory of one embodiment of the invention.
Fig. 3 D is right the read operation schematic diagram that illustrates a kind of P type channel memory of one embodiment of the invention.
Fig. 3 E is the erase operation for use schematic diagram that illustrates a kind of P type channel memory of one embodiment of the invention.
The simple symbol explanation
100: substrate
103:N type well region
110: memory cell
120a, 120b: source/drain regions
130: the first memory cell
131,141a: tunneling dielectric layer
131 ', 135 ': dielectric materials layer
133: floating grid
133 ', 137 ', 143 ': conductor material layer
135: dielectric layer between grid
135a, 135a ', 135c, 135c ': silicon oxide layer
135b, 135b ': silicon nitride layer
137,143: the control grid
140: the second memory cell
141: charge trapping structure
141b: charge immersing layer
141c: stop dielectric layer
Embodiment
Fig. 1 is the section of structure that illustrates a kind of non-volatility memorizer of one embodiment of the invention.
Please refer to Fig. 1, this non-volatility memorizer is made up of substrate 100, memory cell 110, source/ drain regions 120a, 120b at least.Memory cell 110 is arranged in the substrate 100, and memory cell 110 is to comprise memory cell 130 and memory cell 140 at least.Wherein, memory cell 130 for example is to comprise dielectric layer 135 and control grid 137 between tunneling dielectric layer 131, floating grid 133, grid by 100 of substrates.Memory cell 140 is arranged at the sidewall of memory cell 130.Memory cell 140 is made of with charge trapping structure 141 control grid 143, control grid 143 is arranged at the sidewall of memory cell 130, charge trapping structure 141 is arranged between control grid 143 and the memory cell 130, and between control grid 143 and the substrate 100.Source/ drain regions 120a, 120b are arranged in memory cell 110 substrate on two sides 100.
Tunneling dielectric layer 131 in the memory cell 130, its material for example are silica.The material of floating grid 133 for example is doped polycrystalline silicon or other conductor material.The material of control grid 137 for example is doped polycrystalline silicon or other conductor material such as metal, metal silicide.Wherein, dielectric layer 135 can be a composite dielectric layer between grid, from bottom to top is silicon oxide layer 135a, silicon nitride layer 135b and silicon oxide layer 135c in regular turn.Certainly, dielectric layer 135 also may be to include only silicon oxide layer 135a and silicon nitride layer 135b between grid, perhaps only is one deck silicon oxide layer 135a.That is to say that the material of dielectric layer 135 between grid is so long as suitable dielectric material can stop that electronics stored in the floating grid 133 enters control grid 137 and gets final product.Memory cell 130 can be in the middle store charge of floating grid 133, and deposits the data of a position in.
Above-mentioned non-volatility memorizer is chained together memory cell 130 and memory cell 140, and wherein any memory cell is as the usefulness of selection grid.By controlling its down opening or closing of square channel, and then avoid the existing problem of excessively erasing or electrically connecting that can electricity be erased and programmable read only memory produced, and the situation of prevention data erroneous judgement takes place.In addition, memory cell 130 can store a position respectively with memory cell 140, and therefore non-volatility memorizer of the present invention is the structure of two of single memory cells.And, be different from the silicon nitride ROM that has single memory cell two bit architectures now, because two positions of the present invention are to be stored in separately among the different structure, therefore, second effect can not take place, and be improved the usefulness and the reliability of element.
The manufacture method of above-mentioned non-volatility memorizer below promptly is described.Please refer to Fig. 2 A to Fig. 2 E, it is the manufacturing process profile that illustrates a kind of non-volatility memorizer of one embodiment of the invention.
Please refer to Fig. 2 A, substrate 100 at first is provided, substrate 100 for example is the substrate of P type.Afterwards, in substrate 100, form isolation structure (not illustrating).Then, in substrate 100, form N type well region 103.The formation method of N type well region 103 for example is that the method injected with alloy diffusion or alloy is in substrate 100 doped N-type alloys.
Then, in substrate 100, form dielectric materials layer 131 ' in regular turn, conductor material layer 133 ', dielectric materials layer 135 ' and conductor material layer 137 '.The material of dielectric materials layer 131 ' for example is a silica, and its formation method for example is a thermal oxidation method.The material of conductor material layer 133 ' for example is a doped polycrystalline silicon, and its formation method for example is a chemical vapour deposition technique.Because conductor material layer 133 ' is the usefulness as floating grid 133, therefore, after conductor material layer 133 ' forms, can carry out one time patterning step earlier.Form dielectric materials layer 135 ' and conductor material layer 137 ' more successively.
The material of conductor material layer 137 ' for example is a doped polycrystalline silicon, and its formation method for example is a chemical vapour deposition technique.Certainly, conductor material layer 133 ', 137 ' may be suitable conductor materials such as metal, metal silicide also, and its formation method for example is a physical vaporous deposition.Dielectric materials layer 135 ' from bottom to top for example is to comprise silicon oxide layer 135a ', silicon nitride layer 135b ' and silicon oxide layer 135c '.The formation method of silicon oxide layer 135a ', 135c ' for example is a chemical vapour deposition technique.The formation method of silicon nitride layer 135b ' for example is a chemical vapour deposition technique.Dielectric materials layer 135 ' in the present embodiment is that example explains with the composite dielectric layer, yet, because dielectric materials layer 135 ' is the usefulness as dielectric layer 135 between follow-up grid, therefore, its material can be suitable dielectric materials such as silica or silica/silicon nitride also, and it is looked closely circuit elements design and decides.
Then, please refer to Fig. 2 B, patterned dielectric material layer 131 ', conductor material layer 133 ', dielectric materials layer 135 ' and conductor material layer 137 ' are to form memory cell 130.The method of patterning above-mentioned material layer for example is to go up in control gate material layers 137 ' to form one deck patterning photoresist layer (not illustrating), with this patterning photoresist layer is mask, carry out anisotropic etching, and define dielectric layer 135 (silicon oxide layer 135c, silicon nitride layer 135b and silicon oxide layer 135a), floating grid 133 and tunneling dielectric layer 131 between control grid 137, grid.Wherein, conductor material layer 133 ' will form the floating grid 133 of block shape through after the twice photoetching etched step, and the floating grid 133 in the memory cell 130 can be used for store charge.
Afterwards, please refer to Fig. 2 C, on memory cell 130, form charge trapping structure 141.Charge trapping structure 141 for example is tunneling dielectric layer 141a, charge immersing layer 141b by 100 of substrates and stops dielectric layer 141c.The material of tunneling dielectric layer 141a for example is a silica, and its formation method for example is a chemical vapour deposition technique.The material of charge immersing layer 141b for example is a silicon nitride, and its formation method for example is a chemical vapour deposition technique.The material that stops dielectric layer 141c for example is a silica, and its formation method for example is a chemical vapour deposition technique.Certainly, tunneling dielectric layer 141a and stop that dielectric layer 141c also can be other materials similar.The material of charge immersing layer 141b is not limited to silicon nitride, also can be that other can make electric charge be absorbed in material wherein, for example tantalum pentoxide, strontium titanates thing and hafnium oxide etc.
Next, please refer to Fig. 2 D, in substrate 100, form one deck conductor material layer 143 '.The material of conductor material layer 143 ' for example is a doped polycrystalline silicon, its formation method for example is after utilizing chemical vapour deposition technique to form one deck undoped polycrystalline silicon, carry out the ion implantation step to form it, can certainly adopt the mode of injecting alloy when participating in the cintest to form doped polysilicon layer with chemical vapour deposition technique.The material of conductor material layer 143 ' can be suitable conductor materials such as metal, metal oxide also, and its formation method is decided on the difference of material.Afterwards, remove conductor material layer 143 ' on the memory cell 130.Because charge trapping structure 141 is different with the etching selectivity of conductor material layer 143 ', therefore, can utilize charge trapping structure 141 to be etch stop layer, etched conductors material layer 143 '.
Then, please refer to Fig. 2 E, patterned conductor material layer 143 ' forms control grid 143 with the sidewall in memory cell 130.The method of patterned conductor material layer 143 ' for example is to go up in conductor material layer 143 ' to form one deck patterning photoresist layer (not illustrating), covers the conductor material layer 143 ' and charge trapping structure 141 of memory cell 130 1 sidewalls.Then, be mask with patterning photoresist layer, carry out anisotropic etching process, remove the conductor material layer 143 ' of memory cell 130 another sidewalls.Certainly, in etching is carried out, also the charge trapping structure 141 of this another sidewall can be removed in the lump.Control grid 143 constitutes memory cell 140 with charge trapping structure 141, and the charge immersing layer 141b in the memory cell 140 can store charge.Memory cell 130 constitutes memory cell 110 with memory cell 140.Afterwards, form source/ drain regions 120a, 120b in the both sides of memory cell 110.Alloy among source/drain regions 120a, the 120b for example is a P type alloy, and its formation method for example is the alloy injection technology.Formed non-volatility memorizer is the memory of P type passage.
The manufacture method of above-mentioned non-volatility memorizer, because both etching selectivities of charge trapping structure 141 and conductor material layer 143 ' are different, therefore, can utilize charge trapping structure 141 conducts alignment mask voluntarily, remove the conductor material layer 143 ' on the memory cell 130, and increase process margin.And this processing step is simple, again can be in conjunction with memory cell 130 and memory cell 140, and form the structure of two of single memory cells, quite have the value on the industry.
The method of operation of non-volatility memorizer of the present invention then, is described.Please refer to Fig. 3 A to Fig. 3 E.Fig. 3 A is left the programming operations schematic diagram that illustrates a kind of P type channel memory of one embodiment of the invention.Fig. 3 B is right the programming operations schematic diagram that illustrates a kind of P type channel memory of one embodiment of the invention.Fig. 3 C is left the read operation schematic diagram that illustrates a kind of P type channel memory of one embodiment of the invention.Fig. 3 D is right the read operation schematic diagram that illustrates a kind of P type channel memory of one embodiment of the invention.Fig. 3 E is the erase operation for use schematic diagram that illustrates a kind of P type channel memory of one embodiment of the invention.
Please refer to Fig. 3 A, when carrying out programming operations, apply voltage V in source/drain regions 120a
P1, it for example is about-5 volts.Apply voltage V in source/drain regions 120b
P2, it for example is about 0 volt.Apply voltage V in control grid 137
PG1, it for example is about 6 volts.Apply voltage V in control grid 143
PC1, it for example is about 0 volt.Apply voltage V in N type well region 103
NW, it for example is about 0 volt.Wherein control the voltage V of grid 137
PG1Voltage V greater than source/drain regions 120a
P1, and the voltage V of source/drain regions 120b
P2Voltage V greater than source/drain regions 120a
P1, bring out the hot electron injection effect between valence band-conduction band to utilize, electronics is injected the floating grid 133 of memory cell 130, deposit position, a left side in.
Please refer to Fig. 3 B, when carrying out programming operations, can also apply voltage V in source/drain regions 120a
P1, it for example is about-5 volts.Apply voltage V in source/drain regions 120b
P2, it for example is about 0 volt.Apply voltage V in control grid 137
PG2, it for example is about-12 volts.Apply voltage V in control grid 143
PC2, it for example is about-1 volt.Apply voltage V in N type well region 103
NW, it for example is about 0 volt.Wherein control the voltage V of grid 143
PC2Voltage V greater than source/drain regions 120a
P1, the voltage V of source/drain regions 120a
P1Voltage V greater than control grid 137
PG2, and the voltage V of source/drain regions 120b
P2Voltage V greater than source/drain regions 120a
P1, bring out the hot electron injection effect to utilize the passage hot hole, electronics is injected the charge trapping structure 141 of memory cell 140, deposit right position in.
Please refer to Fig. 3 C, when carrying out read operation, apply voltage V in source/drain regions 120a
R1, it for example is about 0 volt.Apply voltage V in source/drain regions 120b
R2, it for example is about-1.5 volts.Apply voltage V in control grid 137
RG1, it for example is about-3 volts.Apply voltage V in control grid 143
RC1, it for example is about-6 volts.Apply voltage V in N type well region 103
NW, it for example is about 0 volt.Wherein control the voltage V of grid 143
RC1Voltage V less than control grid 137
RG1, the voltage V of control grid 137
RG1Voltage V less than source/drain regions 120b
R2, and the voltage V of source/drain regions 120b
R2Voltage V less than source/drain regions 120a
R1, opening the passage of memory cell 140 belows, and the position, a left side in the reading cells 130.
Please refer to Fig. 3 D, when carrying out read operation, can also apply voltage V in source/drain regions 120a
R1, it for example is about 0 volt.Apply voltage V in source/drain regions 120b
R2, it for example is about-1.5 volts.Apply voltage V in control grid 137
RG2, it for example is about-6 volts.Apply voltage V in control grid 143
RC2, it for example is about-3 volts.Apply voltage V in N type well region 103
NW, it for example is about 0 volt.Wherein control the voltage V of grid 137
RG2Less than control grid 143 voltage V
RC2, the voltage V of control grid 143
RC2Voltage V less than source/drain regions 120b
R2, and the voltage V of source/drain regions 120b
R2Voltage V less than source/drain regions 120a
R1, opening the passage of memory cell 130 belows, and the right position in the reading cells 140.
Please refer to Fig. 3 E, when carrying out erase operation for use, apply voltage V in source/drain regions 120b
E2, it for example is about 0 volt.Apply voltage V in control grid 137
EG, it for example is about-15 volts.Apply voltage V in control grid 143
EC, it for example is about-15 volts.Apply voltage V in N type well region 103
NW, it for example is about 0 volt, and source/drain regions 120a is floated.Wherein, the voltage V of control grid 137
EGVoltage V with control grid 143
ECVoltage V less than N type well region 103
NWTo utilize passage FN tunneling effect, with the electronics in the floating grid 133 that is stored in the memory cell 130, with the electronics in the charge trapping structure 141 that is stored in the memory cell 140, import in the N type well region 103 position, a left side and right position that the memory cell of erasing 130 and memory cell 140 had before deposited in.
The method of operation of the non-volatility memorizer that the present invention proposes is utilized and is brought out the hot electron injection effect between valence band-conduction band, electronics is injected the floating grid 133 of memory cell 130; Utilize the passage hot hole to bring out the hot electron injection effect, electronics is injected the charge trapping structure 141 of memory cell 140.The mechanism that these electronics inject, its efficient is higher, can improve the service speed of non-volatility memorizer, and required voltage is low, can also save power consumption.
In sum, non-volatility memorizer of the present invention is chained together memory cell and memory cell, not only can store the data of two positions in single memory cell, and can not produce existing excessively erasing or the problem of second effect etc.In addition, the operator scheme efficient height of this kind non-volatility memorizer, when memory carried out programming operations, required voltage was low, can save power consumption, improved the running speed of element, quite had the value on the industry.
Though the present invention discloses as above with preferred embodiment; yet it is not in order to limit the present invention; those skilled in the art can do a little change and retouching without departing from the spirit and scope of the present invention, thus protection scope of the present invention should with accompanying Claim the person of being defined be as the criterion.
Claims (27)
1. non-volatility memorizer comprises:
One substrate;
One memory cell is arranged in this substrate, and this memory cell comprises:
One first memory cell, this first memory cell are risen by this substrate and comprise a floating grid and one first control grid at least;
One second memory cell is arranged at a sidewall of this first memory cell, and this second memory cell is risen by this substrate and comprises a charge immersing layer and one second control grid; And
Source is arranged in this substrate of these memory cell both sides.
2. non-volatility memorizer as claimed in claim 1, wherein this second memory cell comprises a charge trapping structure, this charge trapping structure comprises this charge immersing layer, and this charge trapping structure is arranged between this second control grid and this substrate and extends to this and second controls between grid and this first memory cell.
3. non-volatility memorizer as claimed in claim 2, wherein this charge trapping structure is risen by this substrate and comprises that a tunneling dielectric layer, this charge immersing layer and stop dielectric layer.
4. non-volatility memorizer as claimed in claim 1, wherein the material of this charge immersing layer comprises silicon nitride.
5. non-volatility memorizer as claimed in claim 1 wherein comprises a dielectric layer between this floating grid and this substrate.
6. non-volatility memorizer as claimed in claim 1 wherein comprises dielectric layer between grid between this first control grid and this floating grid.
7. non-volatility memorizer as claimed in claim 6, wherein the material of dielectric layer comprises silicon oxide/silicon nitride/silicon oxide between these grid.
8. non-volatility memorizer as claimed in claim 1, wherein the material of this floating grid comprises doped polycrystalline silicon.
9. non-volatility memorizer as claimed in claim 1, wherein the material of this first control grid and this second control grid comprises doped polycrystalline silicon.
10. the manufacture method of a non-volatility memorizer comprises:
One substrate is provided;
Form one first memory cell in this substrate, this first memory cell is risen by this substrate and comprises dielectric layer and one first control grid between a dielectric layer, a floating grid, grid;
In this substrate, form a charge trapping structure;
In this substrate, form a conductor layer;
Remove this conductor layer of part, form one second control grid with the sidewall in this first memory cell, wherein this charge trapping structure and this second control grid constitute one second memory cell; And
In the not adjacent side of this first memory cell with this second memory cell, and not adjacent with this first memory cell side of this second memory cell, two doped regions formed.
11. the manufacture method of non-volatility memorizer as claimed in claim 10 also is included in before the step that forms this first memory cell, forms a N type well region in this substrate.
12. the manufacture method of non-volatility memorizer as claimed in claim 11, wherein this two doped region is a P type doped region.
13. the manufacture method of non-volatility memorizer as claimed in claim 10, wherein this charge trapping structure is risen by this substrate and comprises that a tunneling dielectric layer, a charge immersing layer and stop dielectric layer.
14. the manufacture method of non-volatility memorizer as claimed in claim 13, wherein the material of this charge immersing layer comprises silicon nitride.
15. the manufacture method of non-volatility memorizer as claimed in claim 10, the method that wherein removes this conductor layer of part comprises:
With this charge trapping structure is etch stop layer, removes this conductor layer on this first memory cell;
In this substrate, form a patterning photoresist layer, cover this conductor layer of this sidewall of this first memory cell; And
With this patterning photoresist layer is mask, removes this conductor layer that exposes.
16. the manufacture method of non-volatility memorizer as claimed in claim 15, the method that wherein removes this conductor layer that exposes comprises anisotropic etch process.
17. the method for operation of a P type channel memory, this P type channel memory comprises a N type well region, is arranged in the substrate; One memory cell, be arranged on this N type well region, this memory cell comprises one first memory cell and one second memory cell that is arranged at a sidewall of this first memory cell, wherein, this first memory cell is risen by this substrate and comprises a floating grid and one first control grid at least, this second memory cell is risen by this substrate and comprises a charge immersing layer and one second control grid at least, and this floating grid is suitable for storing one first, and this charge immersing layer is suitable for storing one second; One first source/drain regions and one second source/drain regions are arranged at respectively in this N type well region of the first memory cell side of this memory cell and the second memory cell side; This method of operation comprises:
When carrying out programming operations, apply one first voltage in this first source/drain regions, apply one second voltage in this second source/drain regions, apply a tertiary voltage in this first control grid, apply one the 4th voltage in this second control grid, apply one the 5th voltage in this N type well region, wherein this tertiary voltage is greater than this first voltage, this second voltage is greater than this first voltage, bring out the hot electron injection effect between valence band-conduction band to utilize, electronics is injected this floating grid, deposit this first in.
18. the method for operation of P type channel memory as claimed in claim 17, wherein this first voltage is negative voltage, and this tertiary voltage is a positive voltage.
19. the method for operation of P type channel memory as claimed in claim 17, wherein this first voltage is-5 volts, and this second voltage is 0 volt, and this tertiary voltage is 6 volts, and the 4th voltage is 0 volt, and the 5th voltage is 0 volt.
20. the method for operation of P type channel memory as claimed in claim 17, wherein when carrying out programming operations, also be included in this first source/drain regions and apply this first voltage, apply this second voltage, apply one the 6th voltage in this first control grid in this second source/drain regions; Apply one the 7th voltage in this second control grid; Apply the 5th voltage in this N type well region, wherein the 7th voltage is greater than this first voltage, and this first voltage is greater than the 6th voltage, this second voltage is greater than this first voltage, to utilize the passage hot hole to bring out the hot electron injection effect, electronics is injected this charge immersing layer, deposit this second in.
21. the method for operation of P type channel memory as claimed in claim 20, wherein the 6th voltage is-12 volts, and the 7th voltage is-1 volt.
22. the method for operation of P type channel memory as claimed in claim 17, wherein when carrying out erase operation for use, apply one the 8th voltage in this second source/drain regions, apply one the 9th voltage in this first control grid, apply 1 the tenth voltage in this second control grid, apply 1 the 11 voltage in this N type well region, this first source/drain regions is floated, wherein the 9th voltage and the tenth voltage are less than the 11 voltage, to utilize passage FN tunneling effect, to be stored in the electronics of this floating grid and this charge immersing layer, import in this N type well region.
23. the method for operation of P type channel memory as claimed in claim 22, wherein the 8th voltage is 0 volt, and the 9th voltage is-15 volts, and the tenth voltage is-15 volts, and the 11 voltage is 0 volt.
24. the method for operation of P type channel memory as claimed in claim 17, wherein when carrying out read operation, apply 1 the 12 voltage in this first source/drain regions, apply 1 the 13 voltage in this second source/drain regions, apply 1 the 14 voltage in this first control grid, apply 1 the 15 voltage in this second control grid, apply 1 the 16 voltage in this N type well region, wherein the 15 voltage is less than the 14 voltage, and the 14 voltage is less than the 13 voltage, the 13 voltage is less than this 12 voltage, opening the passage of this second memory cell below, and reads in this floating grid this first.
25. the method for operation of P type channel memory as claimed in claim 24, wherein the 12 voltage is 0 volt, and the 13 voltage is-1.5 volts, and the 14 voltage is-3 volts, and the 15 voltage is-6 volts, and the 16 voltage is 0 volt.
26. the method for operation of P type channel memory as claimed in claim 24, wherein when carrying out read operation, also be included in this first source/drain regions and apply the 12 voltage, apply the 13 voltage in this second source/drain regions, apply 1 the 17 voltage in this first control grid, apply 1 the 18 voltage in this second control grid, apply the 16 voltage in this N type well region, wherein the 17 voltage is less than the 18 voltage, and the 18 voltage is less than the 13 voltage, the 13 voltage is less than this 12 voltage, opening the passage of this first memory cell below, and reads in this charge immersing layer this second.
27. the method for operation of P type channel memory as claimed in claim 26, wherein the 17 voltage is-6 volts, and the 18 voltage is-3 volts.
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| CNB2005100921290A CN100452356C (en) | 2005-08-19 | 2005-08-19 | Nonvolatile memory unit, manufacturing method, and opertion method |
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Citations (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US5278439A (en) * | 1991-08-29 | 1994-01-11 | Ma Yueh Y | Self-aligned dual-bit split gate (DSG) flash EEPROM cell |
| US6472706B2 (en) * | 2000-07-12 | 2002-10-29 | Koninklijke Philips Electronics Nv | Semiconductor device |
| WO2004038728A1 (en) * | 2002-10-24 | 2004-05-06 | Koninklijke Philips Electronics N.V. | Self-aligned 2-bit 'double poly cmp' flash memory cell |
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2005
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Patent Citations (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US5278439A (en) * | 1991-08-29 | 1994-01-11 | Ma Yueh Y | Self-aligned dual-bit split gate (DSG) flash EEPROM cell |
| US6472706B2 (en) * | 2000-07-12 | 2002-10-29 | Koninklijke Philips Electronics Nv | Semiconductor device |
| WO2004038728A1 (en) * | 2002-10-24 | 2004-05-06 | Koninklijke Philips Electronics N.V. | Self-aligned 2-bit 'double poly cmp' flash memory cell |
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