CN100451792C - Storage cell, pixel structure and manufacturing method of storage cell - Google Patents
Storage cell, pixel structure and manufacturing method of storage cell Download PDFInfo
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- CN100451792C CN100451792C CNB2005101232331A CN200510123233A CN100451792C CN 100451792 C CN100451792 C CN 100451792C CN B2005101232331 A CNB2005101232331 A CN B2005101232331A CN 200510123233 A CN200510123233 A CN 200510123233A CN 100451792 C CN100451792 C CN 100451792C
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Abstract
The invention discloses a memory module. The memory module is installed on a substrate. The memory module includes an island polysilicon layer, a first dielectric layer, a floating layer, a second dielectric layer and the control gate. The island polysilicon layer is installed on the substrate and the polycrystalline silicon island includes a source of doping, doped drain region and at the very source and drain doping region between the doped channels. The crossing of the surface has a number of laws with a tip. The first dielectric layer is placed in polycrystalline silicon layer on the island. The floating layer is installed at the first dielectric layer, and the second dielectric layer is installed at the floating layer and the control gate is installed at the second dielectric layer. The memory module can be integrated at low temperature polysilicon LCD panel or organic light-emitting diode display panels manufacture.
Description
Technical field
The present invention relates to a kind of storage unit (memory cell) and manufacture method thereof, and be particularly related to a kind of metal-oxide-nitride that can on glass substrate, make-oxide-polysilicon kenel (Metal-Oxide-Nitride-Oxide-Poly Silicon, storage unit MONOS) (memory cell).
Background technology
Because LCD and organic light emitting diode display have gently, thin, short, little advantage, therefore in the past in 20 years, become the show tools that carries with terminal system gradually, especially stable twisted nematic LCD (TN-LCD), STN Super TN type LCD (STN-LCD) and Thin Film Transistor-LCD (TFT-LCD) have become the indispensable articles for daily use of people.In general common Thin Film Transistor-LCD, its pixel is made of thin film transistor (TFT), storage capacitors and a pixel electrode.The view data that is written in each pixel can be stored in the storage capacitors, and each frame period (frame) all can be updated once, therefore the power consumption of the Thin Film Transistor-LCD of this framework is very high.
In present many portable type electronic products, its LCD is to be used for showing still image (static image) in most of the time, so stored view data there is no need to upgrade always in the pixel.In the case,, be embedded in each pixel, can reduce the power consumption of LCD significantly as static RAM (SRAM) or dynamic RAM (DRAM) if with storer (memory).
Fig. 1 is the circuit diagram of known pixel structure.Please refer to Fig. 1, known dot structure 100 in order to the demonstration tableaux comprises thin film transistor (TFT) 110, liquid crystal capacitance 120, memorizer control circuit 130 and static RAM 140.Wherein, the grid G of thin film transistor (TFT) 110 is electrically connected with sweep trace SL, and the source S of thin film transistor (TFT) 110 is electrically connected with data line DL, and the drain D of thin film transistor (TFT) 110 is electrically connected with liquid crystal capacitance 120.In addition, the drain D of thin film transistor (TFT) 110 can be electrically connected with static RAM 140 by memorizer control circuit 130, so that the picture signal that inputs to liquid crystal capacitance 120 from data line DL can be stored in the static RAM 140 by memorizer control circuit 130.
Under the situation that shows still image, because static RAM 140 can be kept the voltage difference of liquid crystal capacitance 120, and need not continue to do the work that data are upgraded, so power consumption can reduce significantly.Yet, general static RAM 140 is made of four thin film transistor (TFT) T1, and memorizer control circuit 130 is made of two thin film transistor (TFT) T2, these thin film transistor (TFT)s T1, T2 will make the circuit layout in the dot structure 100 become very crowded, and these thin film transistor (TFT)s T1, T2 has for the aperture opening ratio (aperture ratio) of dot structure 100 and seriously influences, therefore dot structure 100 can only be applied in the reflecting type liquid crystal display panel (reflective LCD panel) usually, and can't be applied in penetrate through type liquid crystal display board (transmissive LCD panel).
Summary of the invention
In view of this, the purpose of this invention is to provide a kind of storage unit that can be integrated in the low-temperature polysilicon film transistor (LTPS-TFT).
Another object of the present invention provides the very low dot structure of a kind of power consumption.
A further object of the present invention provides a kind of manufacture method of the storage unit that can integrate with low-temperature polysilicon film transistor technology (LTPS-TFT manufacturing process).
For reaching above-mentioned or other purposes, the present invention proposes a kind of storage unit, and this storage unit is suitable for being arranged on the substrate, and this storage unit comprises island polysilicon layer (poly-island), first dielectric layer, capture layer, second dielectric layer and control grid.Wherein, the island polysilicon layer is arranged on the substrate, and the island polysilicon layer comprises source doping region, drain doping region and the channel region between source doping region and drain doping region, and has a plurality of tips on the surface of channel region.First dielectric layer is arranged on the island polysilicon layer, capture layer is arranged on first dielectric layer, and second dielectric layer is arranged on the capture layer, and the control grid is arranged on second dielectric layer, and above-mentioned these are most advanced and sophisticated along being parallel to the bearing of trend of this control grid and being arranged at least one row.
For reaching above-mentioned or other purposes, the present invention proposes a kind of dot structure, this dot structure is suitable for being electrically connected with sweep trace and data line, and this dot structure comprises active member, pixel electrode, control circuit and one or more said memory cells (as single memory cell or memory cell array).Wherein, pixel electrode is electrically connected with sweep trace and data line by active member, and storage unit is electrically connected between control circuit and the pixel electrode.From the above, active member for example is a thin film transistor (TFT).In addition, control circuit for example is by one or a plurality of thin film transistor (TFT) is constituted.
In an embodiment of the present invention, the material of first dielectric layer can be silicon dioxide, and the material of capture layer can be silicon nitride, and the material of second dielectric layer can be silicon dioxide.
In an embodiment of the present invention, the control grid can be positioned at the top of channel region.And in another embodiment of the present invention, the control grid can be positioned at the top of the subregion of the subregion of channel region, source doping region and drain doping region.
In an embodiment of the present invention, the island polysilicon layer can comprise further that the electric charge between channel region and drain doping region brings out doped region (charge induced doped region), and this electric charge brings out doped region and is positioned at control grid below.In addition, the width that electric charge brings out doped region for example is less than or equal to the width of channel region, and source doping region and drain doping region are N type doped region, and electric charge brings out doped region and for example is P type doped region.
In an embodiment of the present invention, storage unit can further comprise the cushion that is arranged between substrate and the island polysilicon layer.
In an embodiment of the present invention, storage unit can further comprise source electrode contacting metal and drain electrode contacting metal, and wherein the source electrode contacting metal is electrically connected with source doping region, and the drain electrode contacting metal is electrically connected with drain doping region.
In an embodiment of the present invention, above-mentioned tip can be parallel to the bearing of trend of controlling grid and be arranged in row.
In an embodiment of the present invention, above-mentioned tip comprises and a plurality ofly is parallel to the bearing of trend of controlling grid and is arranged in the first most advanced and sophisticated and a plurality ofly be parallel to the bearing of trend of control grid and be arranged in second tip that is listed as of row, wherein first tip is adjacent to source doping region, and second tip is adjacent to drain doping region.
For reaching above-mentioned or other purposes, the present invention proposes a kind of manufacture method of storage unit, and it comprises the following steps.At first, form the island polysilicon layer on substrate, wherein the island polysilicon layer comprises source doping region, drain doping region and the channel region between source doping region and drain doping region, and has a plurality of tips on the surface of channel region.Then, on the island polysilicon layer, form first dielectric layer, capture layer and second dielectric layer successively.Afterwards, form the control grid on second dielectric layer, above-mentioned these most advanced and sophisticated edges are parallel to the bearing of trend of this control grid and are arranged at least one row.
In an embodiment of the present invention, the formation method of island polysilicon layer comprises the following steps.At first, on substrate, form amorphous silicon layer, then by continuously lateral crystallization low temperature polycrystalline silicon technology (sequential laterally solidified low temperature poly-silicontechnology, SLS LTPS technology) make amorphous silicon layer crystallization again (re-crystallize) become to have the polysilicon layer at a plurality of tips, above-mentioned these most advanced and sophisticated edges are parallel to the bearing of trend of controlling grid and are arranged at least one row.Afterwards, the patterned polysilicon layer, and polysilicon layer mixed, to form source doping region, drain doping region and channel region.From the above, the formation method of source doping region and drain doping region for example is polysilicon layer to be carried out the N type mix.
In an embodiment of the present invention, we can further form electric charge and bring out doped region between this channel region and drain doping region, and wherein electric charge brings out doped region and is positioned at control grid below.
In an embodiment of the present invention, to bring out the formation method of doped region for example be polysilicon layer to be carried out the P type mix to electric charge.
In an embodiment of the present invention, we can further form cushion between substrate and island polysilicon layer.
In an embodiment of the present invention, we also can further form source electrode contacting metal and drain electrode contacting metal, and wherein the source electrode contacting metal is electrically connected with source doping region, and the drain electrode contacting metal is electrically connected with drain doping region.
State with other purposes, feature and advantage and can become apparent on the present invention for allowing, preferred embodiment cited below particularly, and conjunction with figs. are described in detail below.
Description of drawings
Fig. 1 is the circuit diagram of known pixel structure.
Fig. 2 is the circuit diagram of the present invention's dot structure.
Fig. 3 A and Fig. 3 B are the synoptic diagram of storage unit in the first embodiment of the invention.
Fig. 4 A to Fig. 4 E is the manufacturing process synoptic diagram of the storage unit among Fig. 3 A.
Fig. 5 A and Fig. 5 B are the synoptic diagram of storage unit in the second embodiment of the invention.
Fig. 6 A to Fig. 6 E is the manufacturing process synoptic diagram of the storage unit among Fig. 5 A.
Fig. 7 A, Fig. 7 B and Fig. 7 C are the synoptic diagram of storage unit in the third embodiment of the invention.
Fig. 8 A to Fig. 8 E is the manufacturing process synoptic diagram of the storage unit among Fig. 7 A.
Fig. 9 A and Fig. 9 B are the synoptic diagram of storage unit in the fourth embodiment of the invention.
Figure 10 A and Figure 10 B are the synoptic diagram of storage unit in the fifth embodiment of the invention.
Figure 11 A, Figure 11 B and Figure 11 C are the synoptic diagram of storage unit in the sixth embodiment of the invention.
Figure 12 A and Figure 12 B are the FN programming characteristic of the present invention's storage unit and the FN characteristic of erasing.
Figure 13 A and Figure 13 B are the CHE programming characteristic of the present invention's storage unit and the BBHH characteristic of erasing.
The main element description of symbols
100: dot structure
110, T, T1, T2: thin film transistor (TFT)
120: liquid crystal capacitance
130: memorizer control circuit
140: static RAM
200: dot structure
210: active member
220: pixel electrode
230: control circuit
232,234: control line
240: storage unit
300,300 ', 300 ", 400,400 ', 400 ": storage unit
310: the island polysilicon layer
312: the source dopant zone
314: the drain doping region territory
316: channel region
316a: tip
316a ': first tip
316a ": second tip
320: the first dielectric layers
330: capture layer
340: the second dielectric layers
350: the control grid
360: cushion
370: protective seam
380: the source electrode contacting metal
390: the drain electrode contacting metal
COM: common electrode
C
LC: liquid crystal capacitance
V
COM: voltage
V
DATA: view data
A: substrate
C1, C2: contact hole
SL: sweep trace
DL: data line
G: grid
S: source electrode
D: drain electrode
Embodiment
Fig. 2 is the circuit diagram of the present invention's dot structure.Please refer to Fig. 2, the present invention's dot structure 200 is suitable for being electrically connected with sweep trace SL and data line DL, and dot structure 200 comprises active member 210, pixel electrode 220, control circuit 230 and storage unit 240.Wherein, pixel electrode 220 is electrically connected with sweep trace SL and data line DL by active member 210, and storage unit 240 is electrically connected between control circuit 230 and the pixel electrode 220.In the present invention, active member 210 for example is a thin film transistor (TFT), control circuit 230 for example is by one or a plurality of thin film transistor (TFT) T is constituted, and storage unit 240 for example is single memory cell or the memory cell array of any kenel (memory cell array).
As shown in Figure 2, the pixel electrode 220 that is electrically connected with active member 210 can be arranged at the below of subtend substrate (as colored filter) usually, and liquid crystal layer can be filled between pixel electrode 220 and the common electrode COM, so that pixel electrode 220, be connected to voltage V
COMCommon electrode COM and the liquid crystal layer between the two constitute liquid crystal capacitance C
LC
Please refer to Fig. 2 equally, except thin film transistor (TFT) T, control circuit 230 also comprises control line 232 and control line 234, wherein control line 232 is electrically connected with the grid of thin film transistor (TFT) T, control line 234 is electrically connected with the source electrode of thin film transistor (TFT) T, and the drain electrode of thin film transistor (TFT) T then can be electrically connected with storage unit 240.
As shown in Figure 2, as a high voltage V
GHWhen putting on the sweep trace SL, active member 210 can present the state of unlatching, at this moment, and view data V
DATACan be written on the pixel electrode 220 by data line DL and active member 210.At view data V
DATAWhen being written to pixel electrode 220, by the control of control line 323, control line 324 and thin film transistor (TFT) T, storage unit 240 can be in the state that can be written into, so view data V
DATAAlso can be stored in the storage unit 240 by data line.On the other hand, when dot structure 200 when showing still image, the voltage level of its pixel electrode 220 can be by stored view data V in the storage unit 240
DATAKeep.In other words, by the control of control line 323, control line 324 and thin film transistor (TFT) T, the voltage level of pixel electrode 220 can with view data V
DATAIdentical, to avoid the image quality deterioration.Thus, the present invention does not just need to do Data Update by sweep trace SL and data line DL in each frame period (frame by frame).
The present invention will enumerate multiple storage unit, and describe as follows with embodiment, because storage unit of the present invention is that oxide-nitride thing-oxide structure (Oxide-Nitride-Oxide) is integrated in the low-temperature polysilicon film transistor, thus the multiple storage unit that the present invention enumerated all can with the process integration of existing low-temperature polysilicon film transistor.In other words, if the undertension that puts on the control grid is when carrying out " programming " or " erasing ", following memory cell structure still can be used to be used as the thin film transistor (TFT) use.
First embodiment
Fig. 3 A and Fig. 3 B are the synoptic diagram of storage unit in the first embodiment of the invention.Please refer to Fig. 3 A, the storage unit 300 of present embodiment is suitable for being arranged on the substrate A, and substrate A for example is glass substrate or other transparency carriers.The storage unit 300 of present embodiment comprises island polysilicon layer 310, first dielectric layer 320, capture layer 330, second dielectric layer 340 and control grid 350.Wherein, island polysilicon layer 310 is arranged on the substrate A, and island polysilicon layer 310 comprises source doping region 312, drain doping region 314 and the channel region 316 between source doping region 312 and drain doping region 314, and has the most advanced and sophisticated 316a that a plurality of rules are arranged on the surface of channel region 316.First dielectric layer 320 is arranged on the island polysilicon layer 310, and capture layer 330 is arranged on first dielectric layer 320, and second dielectric layer 340 is arranged on the capture layer 330, and control grid 350 is arranged on second dielectric layer 340.Below will be described in detail at each member in the storage unit 300 respectively.
In the present embodiment, source doping region 312 in the island polysilicon layer 310 and drain doping region 314 are the higher N type doped region (N+) of doping content, and the lower N type doped region (N-) that is doping content of the channel region 316 in the island polysilicon layer 310.Can store one storage unit 300 is example, and most advanced and sophisticated 316a is parallel to the bearing of trend of controlling grid 350 and is arranged in row (being illustrated in Fig. 3 B).By Fig. 3 B as can be known, most advanced and sophisticated 316a fitly is arranged between source doping region 312 and the drain doping region 314, and keeps about equally distance (L/2) with source doping region 312 and drain doping region 314 respectively.In a preferred embodiment of the present invention, the height of most advanced and sophisticated 316a for example is between 50 nanometer to 80 nanometers.It should be noted that above-mentioned altitude range is not in order to restriction the present invention, any person of ordinary skill in the field adjusts the height of most advanced and sophisticated 316a when the optical pickups design requirement.
In the present embodiment, first dielectric layer 320 can be regarded as electric charge tunnel layer (chargetunneling layer), and the material of first dielectric layer 320 for example is the dielectric material that silicon dioxide or other can be crossed by the electric charge tunnelling, and its thickness for example is the 150 Izod right sides.Capture layer 330 can be regarded as electric charge storage layer (charge storage layer), and the material of capture layer 330 film that for example to be silicon nitride or other have the floating capacitation power of electric charge, and its thickness for example is the 250 Izod right sides.In addition, second dielectric layer 340 can be regarded as electric charge barrier layer (chargeblocking layer), and the material of second dielectric layer 340 for example to be silicon dioxide or other can prevent the dielectric material that electric charge injects, and its thickness for example is the 300 Izod right sides.
As shown in Figure 3A, the impurity (impurities) in substrate A diffuses in the island polysilicon layer 310, and the storage unit 300 of present embodiment can further comprise the cushion 360 that is arranged between substrate A and the island polysilicon layer 310.In order to stop the impurity that comes among the substrate A effectively, cushion 360 can be a silicon nitride film or other have the film of impurity resistance barrier effect.
Please refer to Fig. 3 A; in order to improve the component reliability of storage unit 300; the storage unit 300 of present embodiment can further comprise protective seam 370, to cover island polysilicon layer 310, first dielectric layer 320, capture layer 330, second dielectric layer 340 and control grid 350.From the above, the material of protective seam 370 for example is monox, silicon nitride, or the combination of above-mentioned these materials.
It should be noted that, in order successfully to apply a voltage to source doping region 312 and drain doping region 314, the storage unit 300 of present embodiment can further comprise source electrode contacting metal 380 and drain electrode contacting metal 390, wherein source electrode contacting metal 380 is electrically connected with source doping region 312, and drain electrode contacting metal 390 is electrically connected with drain doping region 316.Particularly, have contact hole C1 and contact hole C2 in first dielectric layer 320, capture layer 330, second dielectric layer 340 and the protective seam 370.Therefore, source electrode contacting metal 380 can be electrically connected with source doping region 312 by contact hole C1, and drain electrode contacting metal 390 can be electrically connected with drain doping region 316 by contact hole C2.
Can know by Fig. 3 A and Fig. 3 B and to learn that in the storage unit 300 of present embodiment, control grid 350 is positioned at the top of channel region 316, and control grid 350 not with source doping region 312 and drain doping region 316 overlapping (overlap).In other words, the width W 1 of the control grid 350 of present embodiment equals the length L of channel region 316.
It should be noted that; above-mentioned island polysilicon layer 310, first dielectric layer 320, capture layer 330, second dielectric layer 340 and control grid 350 have constituted the storage unit that can operate (workable memory cell); and cushion 360, protective seam 370, source electrode contacting metal 380 and drain electrode contacting metal 390 all belong to optionally member; the person of ordinary skill in the field is after reference content of the present invention; when can doing suitable additions and deletions and change, but these additions and deletions must belong to the scope that the present invention is contained with changing.
When storage unit 300 when carrying out programming operation (program action), control electrode 350 can be subjected to a high voltage (as 40 volts), can draw the electronics (electron) that comes from the channel region 316 and have high-tension control grid 350, make electron tunneling cross first dielectric layer 320, and then obtained in capture layer 330 by floating.On the other hand, when storage unit 300 when carrying out erase operation for use (erase action), control electrode 350 can be subjected to a low-voltage (as-20 volts), and the control grid 350 with low-voltage can be released electronics by repulsion from capture layer 330, or traction comes from the hole (hole) in the channel region 316, make tunneled holes cross first dielectric layer 320, so with originally combined (recombine) again by the floating electronics that obtains in capture layer 330.It should be noted that owing to having the most advanced and sophisticated 316a that a plurality of rules are arranged on the surface of channel region 316, so storage unit 300 required operating voltage when carrying out programming operation and erase operation for use can be lowered effectively.In addition, the operating frequency of storage unit 300 of the present invention can obtain further raising.
Fig. 4 A to Fig. 4 E is the manufacturing process synoptic diagram of the storage unit among Fig. 3 A.Please refer to Fig. 4 A, substrate A is provided, and on substrate A, form amorphous silicon layer 310a.In the present embodiment, amorphous silicon layer 310a forms by chemical vapor deposition (CVD).It should be noted that present embodiment before forming amorphous silicon layer 310a, optionally forms the cushion (not shown), to stop the impurity that comes from substrate A.
Please refer to Fig. 4 B, after forming amorphous silicon layer 310a, then utilize continuously lateral crystallization low temperature polycrystalline silicon technology (SLS LTPS technology) to make amorphous silicon layer 310a fusion on the substrate A, and recrystallize into polysilicon layer 310b with most advanced and sophisticated 316a that a plurality of rules arrange.
Please refer to Fig. 4 C, after forming polysilicon layer 310b, follow patterned polysilicon layer 310b, and the polysilicon layer 310b after the patterning is mixed, have the island polysilicon layer 310 of source doping region 312, drain doping region 314 and channel region 316 with formation.
Please refer to Fig. 4 D, after forming island polysilicon layer 310, then on island polysilicon layer 310, form first dielectric layer 320, capture layer 330 and second dielectric layer 340 successively.In the present embodiment, first dielectric layer 320, capture layer 330 and second dielectric layer 340 for example are to form by chemical vapor deposition.
Please refer to Fig. 4 E, after forming second dielectric layer 340, then on this second dielectric layer 340, form control grid 350.Afterwards, patterning first dielectric layer 320, capture layer 330 and second dielectric layer 340 are so that the source doping region 312 of part comes out with drain doping region 314.At last, on source doping region 312 that exposes and drain doping region 314, form source electrode contacting metal 380 and drain electrode contacting metal 390 respectively.
It should be noted that present embodiment can form the protective seam (not shown) earlier before patterning first dielectric layer 320, capture layer 330 and second dielectric layer 340, to cover control grid 350.
Second embodiment
Fig. 5 A and Fig. 5 B are the synoptic diagram of storage unit in the second embodiment of the invention.Please be simultaneously with reference to Fig. 5 A and Fig. 5 B, the storage unit 300 ' of present embodiment and first embodiment are similar, but the main difference of the two is: the control grid 350 ' of present embodiment is the subregion that is positioned at source doping region 312, the subregion of drain doping region 314 and the top of channel region 316.In other words, the width W 2 of the control grid 350 ' of present embodiment can be greater than the length L of channel region 316.
Storage unit 300 ' at present embodiment, because control grid 350 ' can partially overlap on source doping region 312 and the drain doping region 314, and admixture (dopant) the concentration ratio channel region 316 in source doping region 312 and the drain doping region 314 is high, therefore compare with first embodiment, the storage unit 300 ' of present embodiment has preferable programming and erases ability.
Fig. 6 A to Fig. 6 E is the manufacturing process synoptic diagram of the storage unit among Fig. 5 A.Please refer to Fig. 6 A to Fig. 6 E, the manufacturing process of the storage unit 300 ' of present embodiment is similar to first embodiment, but the two main difference is: the control grid 350 ' that present embodiment manufactures (shown in Fig. 6 E), its width W 2 can be greater than the length L of channel region 316.
The 3rd embodiment
Fig. 7 A, Fig. 7 B and Fig. 7 C are the synoptic diagram of storage unit in the third embodiment of the invention.Please be simultaneously with reference to Fig. 7 A, Fig. 7 B and Fig. 7 C, the storage unit 300 of present embodiment " similar with first embodiment; and but the main difference of the two is: the island polysilicon layer 310 of present embodiment comprises that also the electric charge between channel region 316 and drain doping region 314 brings out doped region 318, and this electric charge brings out doped region 318 and is positioned at below the control grid 350 '.
By Fig. 7 B and Fig. 7 C as can be known, electric charge brings out the width W 4 (Fig. 7 B shown in) of the width W 3 of doped region 318 less than channel region 316, or equals the width W 4 (shown in Fig. 7 C) of channel region 316, and electric charge brings out doped region 318 and for example is P type doped region.It should be noted that, be N type doped region because electric charge brings out doped region 318 for P type doped region drain doping region 314, so electric charge brings out doped region 318 and engages the storage unit 300 that (P-N junction) can make present embodiment with P-N between the drain doping region 314 " have preferable programming and the ability of erasing.
Fig. 8 A to Fig. 8 E is the manufacturing process synoptic diagram of the storage unit among Fig. 7 A.Please refer to Fig. 8 A to Fig. 8 E, the storage unit 300 of present embodiment " manufacturing process similar to second embodiment, but the two main difference is: present embodiment can further produce electric charge and bring out doped region 318 (shown in Fig. 8 E) between channel region 316 and drain doping region 314.
The 4th embodiment
Fig. 9 A and Fig. 9 B are the synoptic diagram of storage unit in the fourth embodiment of the invention.Please refer to Fig. 9 A and Fig. 9 B, the storage unit 400 and first embodiment of present embodiment are similar, but the main difference of the two is: in the storage unit 400 of present embodiment, have on the surface of channel region 316 and a plurality ofly be parallel to the bearing of trend of controlling grid 350 and be arranged in the first most advanced and sophisticated 316a ' of row and a plurality ofly be parallel to the bearing of trend of control grid 350 and be arranged in second tip 316 that is listed as "; wherein first tip 316 ' is adjacent to source doping region 312, and second tip 316 " be adjacent to drain doping region 314.From the above, the storage unit 400 of present embodiment is a kind of storage unit that can store two bit data, and it can be respectively by the first most advanced and sophisticated 316a ' and second tip 316 " carry out first and deputy programming and erase operation for use.
The 5th embodiment
Figure 10 A and Figure 10 B are the synoptic diagram of storage unit in the fifth embodiment of the invention.Please refer to Figure 10 A and Figure 10 B, the storage unit 400 ' of present embodiment and second embodiment are similar, but the main difference of the two is: in the storage unit 400 ' of present embodiment, have on the surface of channel region 316 and a plurality ofly be parallel to the bearing of trend of controlling grid 350 and be arranged in the first most advanced and sophisticated 316a ' of row and a plurality ofly be parallel to the bearing of trend of control grid 350 and be arranged in second tip 316 that is listed as "; wherein first tip 316 ' is adjacent to source doping region 312; and second tip 316 " be adjacent to drain doping region 314, to carry out first and deputy programming and erase operation for use in the storage unit 400 ' respectively.
The 6th embodiment
Figure 11 A, Figure 11 B and Figure 11 C are the synoptic diagram of storage unit in the sixth embodiment of the invention.Please refer to Figure 11 A, Figure 11 B and Figure 11 C, the storage unit 400 of present embodiment " similar with the 3rd embodiment; but the main difference of the two is: in the storage unit 400 ' of present embodiment; have on the surface of channel region 316 a plurality ofly be parallel to the bearing of trend of control grid 350 and be arranged in the first most advanced and sophisticated 316a ' of row and a plurality ofly be parallel to the bearing of trend of controlling grid 350 and be arranged in second tip 316 that is listed as ", wherein first tip 316 ' is adjacent to source doping region 312, and second tip 316 " be adjacent to drain doping region 314, to carry out storage unit 400 respectively " in first and deputy programming action and erase operation for use.
Experimental example
Be to adopt continuously lateral crystallization low temperature polycrystalline silicon technology to carry out the manufacturing of polysilicon layer on glass substrate among the present invention, after the polysilicon layer manufacturing was finished, the tip can be formed on grain boundary (grain boundary) and locate.Because continuously lateral crystallization low temperature polycrystalline silicon technology can be controlled most advanced and sophisticated formation position effectively, so the tip on the polysilicon layer can aim at other members in the storage unit easily, and is unlikely the problem of generation mis-alignment (mis-alignment).
In the present invention, the crystallite dimension of polysilicon layer (grain size) is about 3.5 microns, and the height that is formed on the tip at grain boundary place is about 80 nanometers; First dielectric layer is the silicon oxide layer of thickness 150 nanometers, and capture layer is the silicon nitride layer of thickness 250 nanometers, and second dielectric layer is the silicon oxide layer of thickness 300 nanometers; Source electrode is the arsenic doping district; Control gate is the molybdenum tungsten layer (sputter forms) of thickness 300 nanometers very.In addition, the length of channel region is 3 microns, and the width of channel region is 3.5 microns, and source electrode and about 1 micron of gate overlap of control.
Figure 12 A and Figure 12 B are the FN programming characteristic of storage unit of the present invention and the FN characteristic of erasing.Please refer to Figure 12 A, in known storage unit (not having the silicon tip end), when we apply 30 volts voltage on the control grid when carrying out fowler-Nordheim (FN) programming operation, the storage unit that does not have the silicon tip end does not almost have the problem of threshold voltage shift (threatholdvoltage shift), but its program speed is very slow.By Figure 12 A as can be known, though we apply 40 volts voltage on the control grid to carry out the FN programming operation, the program speed of storage unit that does not have the silicon tip end is still very slow.Otherwise the threshold voltage shift (threathold voltage shift) with storage unit of silicon tip end is about 2V, and its program speed has improvement.
Then please refer to Figure 12 B, in storage unit of the present invention (having the silicon tip end), when carrying out the FN erase operation for use, storage unit of the present invention can be finished the FN erase operation for use to the voltage that applies-30 volts or-40 volts when us in the time of about 100ms on the control grid.Hence one can see that, the FN that the silicon tip end can the be promoted storage unit effectively characteristic of programming/erase.
In order further to reduce the operating voltage of storage unit, storage unit of the present invention can adopt channel hot electron (channel hot electron, the operation of CHE) programming, and adopts band is to being with hot hole (band-to-band hot hole, the operation of BBHH) erasing.
Figure 13 A and Figure 13 B are the CHE programming characteristic of storage unit of the present invention and the BBHH characteristic of erasing.Please refer to Figure 13 A, when the voltage that puts on the control grid is 18 volts, and when putting on voltage in the drain electrode and being 12 volts (the programming time is 10ms), the programmed threshold voltage nargin of storage unit (programming threathold voltage window) is 2.22 volts.Hence one can see that, and the silicon tip end in the storage unit of the present invention can improve thermionic input rate effectively, and the silicon tip end can quicken the program speed of storage unit effectively.
Then please refer to Figure 13 B, when the voltage that puts on the control grid is 8 volts, and when putting on voltage in the drain electrode and being 20 volts (the programming time is 10ms), the threshold voltage nargin of erasing (erased threathold voltagewindow) of the storage unit of operating by the BBHH mode is 2.44 volts.On the other hand, when putting on the voltage of control on the grid and be 30 volts, the threshold voltage nargin of erasing of the storage unit of operating by the FN mode is 0.56 volt.Hence one can see that, compares with the storage unit of operating by the FN mode, and the storage unit of operating by the BBHH mode can have the speed of erasing faster, bigger erase threshold voltage nargin and lower operating voltage.
In sum, have following advantage at least in the present invention:
1. the present invention can be integrated in the technology of low temperature polycrystalline silicon display panels, have embedded storage unit the to produce dot structure of (embedded memory cell).
2. storage unit of the present invention can have in the low temperature polycrystalline silicon display panels of the penetration of being applied to, reflective and semi-penetration, semi-reflective, does not have the low problem of aperture opening ratio.
3. the present invention can significantly reduce thin film transistor (TFT) quantity required in the dot structure, with the further aperture opening ratio that improves panel.
4. dot structure of the present invention is suitable for showing still image, and during showing still image, its power consumption is very low.
5. in the storage unit of the present invention, owing to have the tip on the channel region surface, so storage unit can have lower operating voltage and higher operating frequency.
Though the present invention discloses as above with preferred embodiment; right its is not in order to limit the present invention; any person of ordinary skill in the field; without departing from the spirit and scope of the invention; when can doing a little change and improvement, so the present invention's protection domain is as the criterion when looking the claim person of defining.
Claims (31)
1. a storage unit is suitable for being arranged on the substrate, it is characterized in that this storage unit comprises:
The island polysilicon layer is arranged on this substrate, and wherein this island polysilicon layer comprises source doping region, drain doping region and the channel region between this source doping region and this drain doping region, and has a plurality of tips on the surface of this channel region;
First dielectric layer is arranged on this island polysilicon layer;
Capture layer is arranged on this first dielectric layer;
Second dielectric layer is arranged on this capture layer; And
The control grid is arranged on this second dielectric layer, and above-mentioned these most advanced and sophisticated edges are parallel to the bearing of trend of this control grid and are arranged at least one row.
2. storage unit according to claim 1, the material that it is characterized in that this first dielectric layer is a silicon dioxide, the material of this capture layer is a silicon nitride, and the material of this second dielectric layer is a silicon dioxide.
3. storage unit according to claim 1 is characterized in that this control grid is positioned at the top of this channel region.
4. storage unit according to claim 1 is characterized in that this control grid is positioned at the top of the subregion of the subregion of this channel region, this source doping region and this drain doping region.
5. storage unit according to claim 1 is characterized in that this island polysilicon layer comprises that also the electric charge between this channel region and this drain doping region brings out doped region, and this electric charge brings out doped region and is positioned at this control grid below.
6. storage unit according to claim 5 is characterized in that width that this electric charge brings out doped region is less than or equal to the width of this channel region.
7. storage unit according to claim 5 is characterized in that this source doping region and this drain doping region are N type doped region, is P type doped region and this electric charge brings out doped region.
8. storage unit according to claim 1 is characterized in that also comprising cushion, is arranged between this substrate and this island polysilicon layer.
9. storage unit according to claim 1 is characterized in that also comprising:
The source electrode contacting metal is electrically connected with this source doping region; And
The drain electrode contacting metal is electrically connected with this drain doping region.
10. storage unit according to claim 1 is characterized in that above-mentioned these tips are parallel to the bearing of trend of this control grid and are arranged in row.
11. storage unit according to claim 1 is characterized in that above-mentioned these tips comprise:
A plurality of first tips are parallel to the bearing of trend of this control grid and are arranged in row; And
A plurality of second tips are parallel to the bearing of trend of this control grid and are arranged in row, and wherein above-mentioned these first tips are adjacent to this source doping region, and above-mentioned these second tips are adjacent to this drain doping region.
12. a dot structure is suitable for being electrically connected with sweep trace and data line, it is characterized in that this dot structure comprises:
Active member;
Pixel electrode is electrically connected in this sweep trace and this data line by this active member;
Control circuit;
Storage unit is electrically connected between this control circuit and this pixel electrode, and wherein this storage unit comprises:
The island polysilicon layer is arranged on this substrate, and wherein this island polysilicon comprises
Source doping region, drain doping region and be positioned at this source doping region and this drain electrode is mixed
Channel region between the district, and have a plurality of tips on the surface of this channel region;
First dielectric layer is arranged on this island polysilicon layer;
Capture layer is arranged on this first dielectric layer;
Second dielectric layer is arranged on this capture layer; And
The control grid is arranged on this second dielectric layer, and above-mentioned these tips are along parallel
In the bearing of trend of this control grid and be arranged at least one row.
13. dot structure according to claim 12 is characterized in that this active member comprises thin film transistor (TFT).
14. dot structure according to claim 12 is characterized in that this control circuit comprises thin film transistor (TFT).
15. dot structure according to claim 12, the material that it is characterized in that this first dielectric layer is a silicon dioxide, and the material of this capture layer is a silicon nitride, and the material of this second dielectric layer is a silicon dioxide.
16. dot structure according to claim 12 is characterized in that this control grid is positioned at the top of this channel region.
17. dot structure according to claim 12 is characterized in that this control grid is positioned at the top of the subregion of the subregion of this channel region, this source doping region and this drain doping region.
18. dot structure according to claim 12 is characterized in that this island polysilicon layer comprises that also the electric charge between this channel region and this drain doping region brings out doped region, and this electric charge brings out doped region and is positioned at this control grid below.
19. dot structure according to claim 18 is characterized in that width that this electric charge brings out doped region is less than or equal to the width of this channel region.
20. dot structure according to claim 18 is characterized in that this source doping region and this drain doping region are N type doped region, it is P type doped region that this electric charge brings out doped region.
21. dot structure according to claim 12 is characterized in that also comprising cushion, is arranged between this substrate and this island polysilicon layer.
22. dot structure according to claim 12 is characterized in that also comprising:
The source electrode contacting metal is electrically connected with this source doping region; And
The drain electrode contacting metal is electrically connected with this drain doping region.
23. dot structure according to claim 12 is characterized in that above-mentioned these tips are parallel to the bearing of trend of this control grid and are arranged in row.
24. dot structure according to claim 12 is characterized in that above-mentioned these tips comprise:
A plurality of first tips are parallel to the bearing of trend of this control grid and are arranged in row; And
A plurality of second tips are parallel to the bearing of trend of this control grid and are arranged in row, and wherein above-mentioned these first tips are adjacent to this source doping region, and above-mentioned these second tips are adjacent to this drain doping region.
25. the manufacture method of a storage unit is characterized in that comprising:
Form the island polysilicon layer on substrate, wherein this island polysilicon layer comprises source doping region, drain doping region and the channel region between this source doping region and this drain doping region, and has a plurality of tips on the surface of this channel region;
On this island polysilicon layer, form first dielectric layer, capture layer and second dielectric layer successively; And
Form the control grid on this second dielectric layer, above-mentioned these most advanced and sophisticated edges are parallel to the bearing of trend of this control grid and are arranged at least one row.
26. the manufacture method of storage unit according to claim 25 is characterized in that the formation method of this island polysilicon layer comprises:
On this substrate, form amorphous silicon layer;
This amorphous silicon layer is recrystallized into have the polysilicon layer at the tip that above-mentioned these rules arrange by continuously lateral crystallization low temperature polycrystalline silicon technology;
This polysilicon layer of patterning; And
This polysilicon layer is mixed, to form this source doping region, this drain doping region and this channel region.
27. the manufacture method of storage unit according to claim 25 is characterized in that the formation method of this source doping region and this drain doping region comprises that this polysilicon layer is carried out the N type to mix.
28. the manufacture method of storage unit according to claim 25 is characterized in that also being included between this channel region and this drain doping region and to form electric charge and bring out doped region, wherein this electric charge brings out doped region and is positioned at below this control grid.
29. the manufacture method of storage unit according to claim 28 is characterized in that the formation method that this electric charge brings out doped region comprises that this polysilicon layer is carried out the P type to mix.
30. the manufacture method of storage unit according to claim 25 is characterized in that also being included between this substrate and this island polysilicon layer and forms cushion.
31. the manufacture method of storage unit according to claim 25 is characterized in that also comprising:
Form source electrode contacting metal and drain electrode contacting metal, wherein this source electrode contacting metal is electrically connected with this source doping region, and should be electrically connected with this drain doping region by the drain electrode contacting metal.
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| CNB2005101232331A CN100451792C (en) | 2005-11-15 | 2005-11-15 | Storage cell, pixel structure and manufacturing method of storage cell |
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| CNB2005101232331A CN100451792C (en) | 2005-11-15 | 2005-11-15 | Storage cell, pixel structure and manufacturing method of storage cell |
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| CN100451792C true CN100451792C (en) | 2009-01-14 |
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Citations (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US5278440A (en) * | 1991-07-08 | 1994-01-11 | Noriyuki Shimoji | Semiconductor memory device with improved tunneling characteristics |
| US6005270A (en) * | 1997-11-10 | 1999-12-21 | Sony Corporation | Semiconductor nonvolatile memory device and method of production of same |
| US6348387B1 (en) * | 2000-07-10 | 2002-02-19 | Advanced Micro Devices, Inc. | Field effect transistor with electrically induced drain and source extensions |
| US20030071302A1 (en) * | 1997-04-25 | 2003-04-17 | Nippon Steel Corporation | Multi-level type nonvolatile semiconductor memory device |
-
2005
- 2005-11-15 CN CNB2005101232331A patent/CN100451792C/en not_active Expired - Fee Related
Patent Citations (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US5278440A (en) * | 1991-07-08 | 1994-01-11 | Noriyuki Shimoji | Semiconductor memory device with improved tunneling characteristics |
| US20030071302A1 (en) * | 1997-04-25 | 2003-04-17 | Nippon Steel Corporation | Multi-level type nonvolatile semiconductor memory device |
| US6005270A (en) * | 1997-11-10 | 1999-12-21 | Sony Corporation | Semiconductor nonvolatile memory device and method of production of same |
| US6348387B1 (en) * | 2000-07-10 | 2002-02-19 | Advanced Micro Devices, Inc. | Field effect transistor with electrically induced drain and source extensions |
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| CN1967362A (en) | 2007-05-23 |
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