CN100524769C - Semiconductor storage device, manufacturing method thereof and portable electronic equipment - Google Patents

Semiconductor storage device, manufacturing method thereof and portable electronic equipment Download PDF

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CN100524769C
CN100524769C CNB2005100878252A CN200510087825A CN100524769C CN 100524769 C CN100524769 C CN 100524769C CN B2005100878252 A CNB2005100878252 A CN B2005100878252A CN 200510087825 A CN200510087825 A CN 200510087825A CN 100524769 C CN100524769 C CN 100524769C
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mentioned
zone
gate electrode
function body
forms
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CN1707800A (en
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岩田浩
柴田晃秀
片冈耕太郎
中野雅行
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Sharp Corp
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Sharp Corp
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Abstract

A semiconductor storage device has a single gate electrode formed on a semiconductor substrate through a gate insulation film. First and second memory function bodies formed on both sides of the gate electrode. A P-type channel region is formed in a surface of the substrate on the side of the gate electrode. N-type first and second diffusion regions are formed on both sides of the channel region. The channel region is composed of an offset region located under the first and second memory function bodies and a gate electrode beneath region located under the gate electrode. The concentration of a dopant which imparts a P-type conductivity to the offset region is effectively lower than the concentration of a dopant which imparts the P-type conductivity to the gate electrode beneath region. This makes it possible to provide the semiconductor storage device which is easily shrunk in scale.

Description

Semiconductor storage and manufacture method thereof and portable electric appts
Technical field
The present invention relates to semiconductor storage and manufacture method thereof and portable electric appts.Specifically, the present invention relates to semiconductor storage and manufacture method thereof that the field-effect transistor by the memory function body with the function that keeps electric charge or polarization constitutes and the portable electric appts that possesses this semiconductor storage.
Background technology
As the representative of existing nonvolatile memory, be example below, illustrated with the flash memory.Figure 32 is a kind of broad cross-section map (for example opening flat 5-304277 communique with reference to the spy) of flash memory one example.Among Figure 32, the 901st, Semiconductor substrate, the 902nd, floating gate, the 903rd, word line, the 904th, source electrode line, the 905th, bit line, the 906th, element separated region, the 907th, dielectric film.
Above-mentioned flash memory keeps what the storage as the quantity of electric charge in the floating gate 902.In the memory cell array that this flash memory arrange is constituted as memory cell, select specific word line, bit line and apply decide voltage, can carry out desired memory cell rewriting, read action.
Figure 33 is that drain current (Id) when the quantity of electric charge changes in the floating gate 902 of the above-mentioned flash memory of expression is to the ideograph of grid voltage (Vg) characteristic.When the negative charge amount in the above-mentioned floating gate 902 increased, threshold value increased, parallel the moving of direction (direction of arrow among Figure 33) that the Id-Vg curve roughly increases at Vg.
Yet, the flash memory of above-mentioned prior art, between word line (gate electrode) and channel region, floating gate is arranged, in order to prevent charge leakage from floating gate 902, be difficult to make the thickness attenuation of the dielectric film 907 of isolating floating gate 902 and word line 903, and the thickness attenuation that is difficult to make the gate insulating film (the floating gate part of dielectric film 907) of isolating floating gate 902 and channel region 909.Its result, effectively gate insulating film is difficult to filming, has hindered becoming more meticulous of flash memory.
Summary of the invention
Problem of the present invention provides the semiconductor storage that becomes more meticulous easily.
In order to solve above-mentioned problem, the semiconductor storage of the 1st invention is characterized in that having:
Semiconductor layer;
The gate insulating film that on above-mentioned semiconductor layer, forms;
The single gate electrode that on above-mentioned gate insulating film, forms;
The memory function body that forms in above-mentioned gate electrode both sides, have maintenance electric charge function;
The 1st conductive type of channel zone that forms in the above-mentioned gate electrode side surface portion of above-mentioned semiconductor layer;
The 2nd conductivity type diffusion zone that forms in above-mentioned channel region both sides;
In the 1st conductivity type the 1st zone that the above-mentioned channel region of the near interface of above-mentioned channel region and above-mentioned memory function body forms;
In the 1st conductivity type the 2nd zone that the above-mentioned channel region of the near interface of above-mentioned channel region and above-mentioned gate insulating film forms,
The impurity concentration of giving above-mentioned the 1st zone the 1st conductivity type is leaner than the impurity concentration of giving above-mentioned the 2nd zone the 1st conductivity type effectively.
If use the semiconductor storage of above-mentioned formation,, form memory function body with maintenance electric charge function in the both sides of above-mentioned gate electrode.This memory function body separates with gate insulating film.Just, above-mentioned memory function body and gate insulating film independently form.Therefore, can make above-mentioned gate insulator filming, suppress short-channel effect.So, above-mentioned semiconductor storage can be become more meticulous.
And owing to form the memory function body in above-mentioned gate electrode both sides, then each memory function body can self contained function, so 2 bit motions are possible.
Equally, because an above-mentioned memory function body is separated by gate electrode with another above-mentioned memory function body, the interference when then rewriteeing between the memory function body can suppress effectively.
In addition,, compare, effectively weaken, then can suppress to rewrite the minimizing of the memory window (memorywindow) that causes with the impurity concentration of giving the 2nd zone the 1st conductivity type owing to make the concentration of the impurity of giving above-mentioned the 1st zone the 1st conductivity type.Therefore, can improve reading speed, increase the possible number of times that rewrites.
Equally,, compare, effectively weaken, then can suppress the characteristic deviation that the deviation of manufacture process is brought, improve rate of finished products with the impurity concentration of giving the 2nd zone the 1st conductivity type owing to make the impurity concentration of giving above-mentioned the 1st zone the 1st conductivity type.
The semiconductor storage of the 2nd invention is characterized in that having:
Semiconductor layer;
The gate insulating film that on above-mentioned semiconductor layer, forms;
The single gate electrode that on above-mentioned gate insulating film, forms;
The memory function body that forms in above-mentioned gate electrode both sides, have maintenance electric charge function,
The 1st conductive type of channel zone that forms in the above-mentioned gate electrode side surface portion of above-mentioned semiconductor layer,
The 2nd conductivity type diffusion zone that forms in above-mentioned channel region both sides,
Give the impurity concentration of above-mentioned channel region the 1st conductivity type, along with from the PN junction of above-mentioned channel region and above-mentioned diffusion zone near the zone under the above-mentioned gate insulating film, effectively thicken.
If use the semiconductor storage of above-mentioned formation,, form memory function body with maintenance electric charge function in the both sides of above-mentioned gate electrode.This memory function body separates with gate insulating film.Just, above-mentioned memory function body and gate insulating film independently form.Therefore, can make above-mentioned gate insulator filming, suppress short-channel effect.So, above-mentioned semiconductor storage is become more meticulous.
And owing to form the memory function body in above-mentioned gate electrode both sides, then each memory function body can self contained function, so 2 bit motions are possible.
Equally, because an above-mentioned memory function body is separated by gate electrode with another memory function body, the interference when then rewriteeing between the memory function body can suppress effectively.
In addition owing to make the impurity concentration of giving above-mentioned channel region the 1st conductivity type, along with from the PN junction of channel region and diffusion zone near the zone under the gate insulating film, effectively thicken, then can suppress to rewrite the minimizing of the memory window that causes.Therefore, can improve reading speed, increase the possible number of times that rewrites.
Equally, owing to make the impurity concentration of giving above-mentioned channel region the 1st conductivity type, along with from the PN junction of channel region and diffusion zone near the zone under the gate insulating film, effectively denseer, then can suppress the characteristic deviation that the deviation of manufacture process is brought, improve rate of finished products.
The semiconductor storage of the 3rd invention is characterized in that having:
Semiconductor layer;
The gate insulating film that on above-mentioned semiconductor layer, forms;
The single gate electrode that on above-mentioned gate insulating film, forms;
The memory function body that forms in above-mentioned gate electrode both sides, have maintenance electric charge function;
The 1st conductive type of channel zone that forms in the above-mentioned gate electrode side surface portion of above-mentioned semiconductor layer,
The 2nd conductivity type diffusion zone that forms in above-mentioned channel region both sides,
When the current potential that makes above-mentioned gate electrode equates with the current potential of above-mentioned diffusion zone, depletion layer that forms at the PN junction of above-mentioned channel region and above-mentioned diffusion zone and the depletion layer that forms under above-mentioned gate electrode are connected at the near interface of above-mentioned channel region with above-mentioned memory function body.
If use the semiconductor storage of above-mentioned formation,, form memory function body with maintenance electric charge function in the both sides of above-mentioned gate electrode.This memory function body separates with gate insulator.Just, above-mentioned memory function body and gate insulating film independently form.Therefore, can make above-mentioned gate insulator filming, suppress short-channel effect.So, above-mentioned semiconductor storage is become more meticulous.
And owing to form the memory function body in above-mentioned gate electrode both sides, then each memory function body can self contained function, so 2 bit motions are possible.
Equally, because an above-mentioned memory function body is separated by gate electrode with another memory function body, the interference when then rewriteeing between the memory function body can suppress effectively.
In addition, when the current potential that makes above-mentioned gate electrode equates with the current potential of diffusion zone, because at the depletion layer of the PN junction of channel region and diffusion zone formation and the depletion layer that under gate electrode, forms, be connected at the near interface of channel region, then can suppress to rewrite the minimizing of the memory window that causes with the memory function body.Therefore, can improve reading speed, increase the possible number of times that rewrites.
Equally, when the current potential that makes above-mentioned gate electrode equates with the current potential of diffusion zone, because at the depletion layer of the PN junction of channel region and diffusion zone formation and the depletion layer that under gate electrode, forms, be connected at the near interface of channel region with the memory function body, then can suppress the characteristic deviation that the deviation of manufacture process is brought, improve rate of finished products.
A kind of semiconductor storage of execution mode, has under above-mentioned the 1st zone the 3rd zone that forms, is connected with above-mentioned the 1st zone, give the impurity concentration of above-mentioned the 3rd zone the 1st conductivity type, compare, effectively thicken with the impurity concentration of giving above-mentioned the 2nd zone the 1st conductivity type.
If use the semiconductor storage of above-mentioned execution mode, owing to make the impurity concentration of giving the 3rd zone the 1st conductivity type that is connected with the above-mentioned the 1st regional bottom, compare with the impurity concentration of giving the 2nd zone the 1st conductivity type, effectively thicken the hot carrier luminous efficiency in the time of then rewrite action can being improved.Therefore, can suppress the deterioration that rewrite action repeats to cause, and, can carry out rewrite action at a high speed.
A kind of semiconductor storage of execution mode, the impurity concentration of giving degree of depth 10nm～80nm part the 1st conductivity type in above-mentioned the 3rd zone is compared with the impurity concentration of other part the 1st conductivity types of giving above-mentioned the 3rd zone, effectively thickens.
If use the semiconductor storage of above-mentioned execution mode, owing to make the impurity concentration of degree of depth 10nm～80nm part the 1st conductivity type of giving above-mentioned the 3rd zone, compare with the impurity concentration of other part the 1st conductivity types of giving the 3rd zone, effectively thicken, then can make near the impurity concentration of the channel region of semiconductor layer and memory function body interface very thin, and, can expeditiously the hot carrier that takes place be injected into the memory function body.Therefore, therefore, the deterioration that rewrite action repeats to cause can be suppressed reliably, and rewrite action can be carried out reliably at a high speed.
A kind of semiconductor storage of execution mode, has under above-mentioned diffusion zone the 4th zone that forms, is connected with above-mentioned diffusion zone, give the impurity concentration of above-mentioned the 4th zone the 1st conductivity type, compare, effectively weaken with the impurity concentration of giving above-mentioned the 2nd zone the 1st conductivity type.
If use the semiconductor storage of above-mentioned execution mode, owing to make the impurity concentration of giving the 4th zone the 1st conductivity type that is connected with above-mentioned diffusion zone bottom, compare with the impurity concentration of giving the 2nd zone the 1st conductivity type, effectively weaken, then can reduce the junction capacitance of relevant the 2nd conductivity type diffusion zone significantly, so can read action at a high speed.Therefore, the deterioration that rewrite action repeats to cause can be suppressed, and rewrite action can be carried out at a high speed.
A kind of semiconductor storage of execution mode, above-mentioned gate insulating film comprises the dielectric film that has greater than the conductivity of silicon oxide layer conductivity.
If use the semiconductor storage of above-mentioned execution mode,, then as the physics thickness is still thicker, can make the equivalent thickness of oxidation film attenuation of gate insulating film by above-mentioned gate insulating film being comprised have dielectric film greater than the conductivity of silicon oxide layer conductivity.Just, can not make the electrical characteristics deterioration of above-mentioned gate insulating film, can be with as the attenuation of gate insulator effective film.
Therefore, can still keep the withstand voltage of above-mentioned gate insulating film, make the equivalent thickness of oxidation film attenuation of gate insulating film, further suppress short-channel effect.Its result compares with the conventional semiconductor storage device, and the semiconductor storage of the present invention that becomes more meticulous is easily further become more meticulous.
A kind of semiconductor storage of execution mode, above-mentioned dielectric film is made of hafnium compound.
If use the semiconductor storage of above-mentioned execution mode,,, also can keep higher conductivity even then semiconductor device becomes more meticulous owing to constitute above-mentioned dielectric film with hafnium compound.Therefore,, also can increase read current, make and read the action high speed even above-mentioned semiconductor storage is become more meticulous.
And because the thermal stability of above-mentioned hafnium compound is higher, higher with the compatibility of silicon processing, then manufacturing process is easy.
The semiconductor storage of the 4th invention is characterized in that having:
Semiconductor layer;
The single gate insulating film that on above-mentioned semiconductor layer, forms;
The single gate electrode that on above-mentioned gate insulating film, forms;
Form, have the memory function body that keeps the electric charge function in above-mentioned gate electrode both sides;
The 1st conductive type of channel zone that forms in the above-mentioned gate electrode side surface portion of above-mentioned semiconductor layer;
The 2nd conductivity type diffusion zone that forms in above-mentioned channel region both sides,
Above-mentioned gate insulating film comprises the 1st dielectric film, and the conductivity that forms on above-mentioned the 1st dielectric film is higher than the 2nd dielectric film of the 1st dielectric film conductivity.
If use the semiconductor storage of above-mentioned formation,, form memory function body with maintenance electric charge function in the both sides of above-mentioned gate electrode.This memory function body separates with gate insulating film.Just, above-mentioned memory function body and gate insulating film independently form.Therefore, can make above-mentioned gate insulator filming, suppress short-channel effect.So above-mentioned semiconductor storage is become more meticulous.
And, owing to form the memory function body in above-mentioned gate electrode both sides, but each memory function body self contained function then, so 2 bit motions are possible.
Because an above-mentioned memory function body is separated by gate electrode with another above-mentioned memory function body, the interference when then rewriteeing between the memory function body can suppress effectively.
In addition, by making above-mentioned gate insulating film comprise the 1st dielectric film, and the conductivity that forms on the 1st dielectric film is higher than the 2nd dielectric film of the 1st dielectric film conductivity, though then make the equivalent thickness of oxidation film of gate insulating film thinner, still the interface of gate insulating film and semiconductor layer can be remained high-grade.Just, 2nd dielectric film and the semiconductor layer direct-connected situation higher with conductivity compare, between higher the 2nd dielectric film of conductivity and semiconductor layer, form the situation of the 1st lower dielectric film of conductivity, can improve the movement of electric charges degree, suppress the deterioration at interface.Therefore, can improve the responsiveness of reading of above-mentioned semiconductor storage, improve reliability.
The semiconductor storage manufacture method of the 5th invention is the manufacture method of the semiconductor storage of above-mentioned the 1st invention, it is characterized in that: after forming above-mentioned gate electrode, after the impurity of giving the 2nd conductivity type is injected into above-mentioned semiconductor layer, form above-mentioned memory function body.
If use the semiconductor storage manufacture method of above-mentioned formation, before forming above-mentioned memory function body, be injected into semiconductor layer by the impurity that will give the 2nd conductivity type, can form above-mentioned the 1st, the 2nd zone from coupling ground.Therefore, can form reading speed height, number of rewrites semiconductor storage how easily.
The semiconductor storage manufacture method of the 6th invention is the manufacture method of the semiconductor storage of above-mentioned the 1st invention, after forming above-mentioned gate electrode, the impurity of giving the 1st conductivity type is injected into above-mentioned semiconductor layer, simultaneously, after the impurity of giving the 2nd conductivity type is injected into above-mentioned semiconductor layer, form above-mentioned memory function body, to be shallower than the impurity of giving above-mentioned the 1st conductivity type.
If use the semiconductor storage manufacture method of above-mentioned formation, before forming above-mentioned memory function body, the impurity of giving the 1st conductivity type is injected into above-mentioned semiconductor layer, simultaneously, the impurity of the impurity by will giving the 2nd conductivity type is injected into above-mentioned semiconductor layer, can form above-mentioned the 1st～the 3rd zone from coupling ground, to be shallower than the impurity of giving the 1st conductivity type.Therefore, can suppress the deterioration that rewrite action repeats to cause, and, the semiconductor storage that can carry out rewrite action at a high speed can be formed easily.
A kind of semiconductor storage manufacture method of execution mode, the impurity of giving above-mentioned the 2nd conductivity type is antimony.
If use the semiconductor storage manufacture method of above-mentioned execution mode, be antimony owing to give the impurity of above-mentioned the 2nd conductivity type, then can suppress the deterioration that rewrite action repeats to cause better, and, can carry out rewrite action more at high speed.
The portable electric appts of the 7th invention is characterized in that: the semiconductor storage with arbitrary record of above-mentioned the 1st～the 3rd invention.
If use the portable electric appts of above-mentioned formation, by having the semiconductor storage of the above-mentioned the 1st～the 3rd any record of inventing, the manufacturing cost that then for example can cut down control circuit.Therefore, can cut down the cost of portable electric appts itself.Perhaps, with for example nonvolatile memory high capacity that above-mentioned control circuit contains, can make the function High Level of portable electric appts.
The semiconductor storage of the 1st invention by memory function body and gate insulating film are independently formed, then can make the gate insulator filming, suppresses short-channel effect, so semiconductor storage is become more meticulous.
And, by forming above-mentioned memory function body in the gate electrode both sides, but each memory function body self contained function then, so 2 bit motions are possible.
Equally, because an above-mentioned memory function body is separated by gate electrode with another memory function body, the interference when then rewriteeing between the memory function body can suppress effectively.
In addition, owing to make the impurity concentration in the 1st zone of the 1st conductivity type that the channel region at the near interface of above-mentioned memory function body and channel region forms, the impurity concentration in the 2nd zone of the 1st conductivity type that forms with channel region at the near interface of gate insulating film and channel region is compared, effectively weaken, then can suppress to rewrite the minimizing of the memory window that causes.Therefore, can improve reading speed, increase the possible number of times that rewrites.
Equally, owing to make the impurity concentration in the 1st zone of the 1st conductivity type that the channel region at the near interface of above-mentioned memory function body and channel region forms, the impurity concentration in the 2nd zone of the 1st conductivity type that forms with channel region at the near interface of gate insulating film and channel region is compared, effectively weaken, then can suppress the characteristic deviation that the deviation of manufacture process is brought, improve rate of finished products.
The semiconductor storage of the 2nd invention independently forms by making memory function body and gate insulating film, then the gate insulator filming can be suppressed short-channel effect, and semiconductor storage is become more meticulous.
And owing to form above-mentioned memory function body in the gate electrode both sides, then each memory function body can self contained function, so 2 bit motions are possible.
Equally, because an above-mentioned memory function body is separated by gate electrode with another memory function body, the interference when then rewriteeing between the memory function body can suppress effectively.
In addition, by giving the impurity concentration of channel region the 1st conductivity type, along with from the PN junction of channel region and diffusion zone near the zone under the gate insulating film, effectively thicken, then can suppress to rewrite the minimizing of the memory window that causes.Therefore, can improve reading speed, increase the possible number of times that rewrites.
Equally, by giving the impurity concentration of above-mentioned channel region the 1st conductivity type, along with from the PN junction of channel region and diffusion zone near the zone under the gate insulating film, actual effect thickens, and then can suppress the characteristic deviation that the deviation of manufacture process is brought, and improves rate of finished products.
The semiconductor storage of the 3rd invention independently forms by making memory function body and gate insulating film, then can make the gate insulator filming, suppresses short-channel effect, so semiconductor storage is become more meticulous.
And, owing to form above-mentioned memory function body in the gate electrode both sides, but each memory function body self contained function then, so 2 bit motions are possible.
Equally, because an above-mentioned memory function body is separated by gate electrode with another memory function body, the interference when then rewriteeing between the memory function body can suppress effectively.
In addition, when the current potential that makes above-mentioned gate electrode equates with the current potential of diffusion zone, because PN junction depletion layer that forms and the depletion layer that under gate electrode, forms at channel region and diffusion zone, be connected at the near interface of channel region, then can suppress to rewrite the minimizing of the memory window that causes with the memory function body.Therefore, can improve reading speed, increase the possible number of times that rewrites.
Equally, when the current potential that makes above-mentioned gate electrode equates with the current potential of diffusion zone, because PN junction depletion layer that forms and the depletion layer that under gate electrode, forms at channel region and diffusion zone, be connected at the near interface of channel region with the memory function body, then can suppress the characteristic deviation that the deviation of manufacture process is brought, improve rate of finished products.
The semiconductor storage of the 4th invention independently forms by making memory function body and gate insulating film, then can make the gate insulator filming, suppresses short-channel effect, so semiconductor storage is become more meticulous.
And owing to form above-mentioned memory function body in the gate electrode both sides, then each memory function body can self contained function, so 2 bit motions are possible.
Equally, because an above-mentioned memory function body is separated by gate electrode with another memory function body, the interference when then rewriteeing between the memory function body can suppress effectively.
In addition, by making above-mentioned gate insulating film comprise the 1st dielectric film, and on the 1st dielectric film, form, the 2nd dielectric film that its conductivity is higher than the 1st dielectric film conductivity, though then make the equivalent thickness of oxidation film of gate insulating film thinner, but the interface of gate insulating film and semiconductor layer can be remained high-grade, therefore, can improve the responsiveness of reading of semiconductor storage, improve reliability.
Description of drawings
The present invention can understand fully according to following detailed description and accompanying drawing, but detailed description and accompanying drawing only provide illustration, can not limit the present invention.
Fig. 1 is the broad cross-section map of memory element of the semiconductor storage of the present invention's the 1st reference example.
Fig. 2 is the broad cross-section map of above-mentioned memory element variation.
Fig. 3 is the write activity key diagram of above-mentioned memory element variation.
Fig. 4 is the write activity key diagram of above-mentioned memory element variation.
Fig. 5 is the cancellation action specification figure of above-mentioned memory element variation.
Fig. 6 is the cancellation action specification figure of above-mentioned memory element variation.
Fig. 7 be above-mentioned memory element variation read action specification figure.
Fig. 8 is the broad cross-section map of memory element of the semiconductor storage of the present invention's the 2nd reference example.
Fig. 9 is the summary part sectional drawing of the memory element of above-mentioned the 2nd reference example semiconductor storage.
Figure 10 is the summary part sectional drawing of the memory element variation of above-mentioned the 2nd reference example semiconductor storage.
Figure 11 is the chart of the memory element electrical characteristics of above-mentioned the 2nd reference example semiconductor storage of expression.
Figure 12 is the summary part sectional drawing of the memory element variation of above-mentioned the 2nd reference example semiconductor storage.
Figure 13 is the broad cross-section map of memory element of the semiconductor storage of the present invention's the 3rd reference example.
Figure 14 is the broad cross-section map of memory element of the semiconductor storage of the present invention's the 4th reference example.
Figure 15 is the broad cross-section map of memory element of the semiconductor storage of the present invention's the 5th reference example.
Figure 16 is the broad cross-section map of memory element of the semiconductor storage of the present invention's the 6th reference example.
Figure 17 is the broad cross-section map of memory element of the semiconductor storage of the present invention's the 7th reference example.
Figure 18 is the broad cross-section map of memory element of the semiconductor storage of the present invention's the 8th reference example.
Figure 19 is the chart of the memory element electrical characteristics of expression the present invention the 9th reference example semiconductor storage.
Figure 20 is the broad cross-section map of the memory element of the present invention's the 1st execution mode.
Figure 21 is the drain current of above-mentioned the 2nd reference example memory element of expression and the chart of number of rewrites relation.
Figure 22 is the drain current of above-mentioned the 1st execution mode memory element of expression and the chart of number of rewrites relation.
Figure 23 is the chart of example of a valid density profile analog result that is illustrated in the A-A line of Figure 20.
Figure 24 is the chart of example of a valid density profile analog result that is illustrated in the B-B line of Figure 20.
Figure 25 is the broad cross-section map of the memory element of the present invention's the 2nd execution mode.
Figure 26 is the chart of an actual effect concentration profile analog result that is illustrated in the C-C line of Figure 25.
Figure 27 A is the key diagram of the memory element formation method of above-mentioned the 2nd execution mode.
Figure 27 B is the key diagram of the memory element formation method of above-mentioned the 2nd execution mode.
Figure 28 is the broad cross-section map of the present invention's the 3rd execution mode memory element.
Figure 29 is the broad cross-section map of the present invention's the 4th execution mode memory element.
Figure 30 is the broad cross-section map of the present invention's the 5th execution mode memory element.
Figure 31 is the summary module map of the present invention's the 6th execution mode portable phone.
Figure 32 is the broad cross-section map of existing flash memory.
Figure 33 is the chart of the above-mentioned existing flash memory electrical characteristics of expression.
Embodiment
At first, the memory element of following diagrammatic illustration semiconductor storage use of the present invention.
The memory element that is used for semiconductor storage of the present invention is mainly by constituting as the 1st conductive area, the 2nd conductive area of diffusion zone, the charge accumulation region that strides across the border configuration of the 1st and the 2nd conductive area, the gate electrode (or word line) that is provided with by gate insulating film; Perhaps, mainly by semiconductor layer, gate insulating film, the gate electrode (or word line) that on gate insulating film, forms, the memory function body that forms in gate electrode (or word line) both sides, channel region, in the diffusion zone formation of channel region both sides configuration.Here, above-mentioned channel region, the zone of the conductivity type identical with semiconductor layer normally is meant the zone under the gate electrode (or word line), diffusion zone is meant the zone with the channel region opposite conductivity type.
This memory element, store 2 systems or the information more than it by 1 charge holding film, memory element performance function as storage 4 systems or its above information, and, by the variable resistor effect of memory function body, as having the memory cell performance function of selecting transistor and memory transistor function concurrently.Yet this memory element needn't necessarily be stored 4 systems or its above information performance function, for example also can store 2 system performance functions.
Semiconductor storage of the present invention wishes to form on the Semiconductor substrate as semiconductor layer, forms on the well area of the 1st conductivity type that preferably forms in Semiconductor substrate.
Semiconductor substrate, get final product so long as be used for semiconductor device, there is no particular limitation, for example by the elemental semiconductor of silicon, germanium etc., and the big volume substrate (bulk substrate) that forms by the compound semiconductor of SiGe, GaAs, InGaAs, ZnSe, GaN etc.The substrate that has semiconductor layer from the teeth outwards has: various substrates such as SOI (Silicon on Insulator) substrate, SOS (Silicon on Sapphire) substrate or multilayer SOI substrate, also can adopt the substrate that has semiconductor layer on glass and plastic lining base plate.Wherein, silicon substrate or SOI substrate of forming silicon layer from the teeth outwards etc. are best.Semiconductor substrate or semiconductor layer produce a little and flow through the inner magnitude of current, and monocrystalline (for example by epitaxial growth, epitaxial growth), polycrystalline or amorphous can.
In this semiconductor layer, be preferably formed as the element separated region, circuit, semiconductor device and the interlayer dielectric that elements such as transistor, capacitor, resistance, these elements are constituted combines again, also can be formed by single or multi-ply construction.The element separated region is formed by various element isolation film such as LOCOS (Local Qxidation of Silicon) film, groove oxide-film, STI (Shallow Trench Isolation) films.Semiconductor layer can have P type or N type conductivity type, in the semiconductor layer, is preferably formed as at least 1 the 1st conductivity type (P type or N type) well area.The impurity concentration of semiconductor layer and well area can be used the concentration in this known scope in field.When adopting the SOI substrate, also can form well area, but also can under channel region, have body region at surperficial semiconductor layer as semiconductor layer.
Gate insulating film or dielectric film get final product so long as be used for semiconductor device, and there is no particular limitation, for example can use dielectric films such as silicon oxide layer, silicon nitride film; The monofilm or the stack membrane of high dielectric films such as pellumina, oxidation titanium film, tantalum-oxide film, hafnium oxide film.Wherein, silicon oxide layer is best.Gate insulating film is 1～20nm thickness for example, but 1～6nm thickness is the most suitable.Gate insulating film can only form under gate electrode, also can be to form than gate electrode big (wide cut).
Gate electrode or word line, the shape to use at semiconductor device usually perhaps is formed on the gate insulating film with the shape that has recess in the bottom.So-called single gate electrode means that can't help the single or multiple lift conducting film separates, as a whole the gate electrode that forms of shape.Just, so-called single gate electrode is meant the individual layer conducting film, perhaps the multilayer conductive film that does not form as a whole discretely.And gate electrode also can have side wall insulating film at sidewall.Gate electrode is so long as be used for semiconductor storage and get final product, and there is no particular limitation, conducting film, and for example poly-silicon: metals such as copper, aluminium: refractory metals such as tungsten, titanium, tantalum: and the monofilm or the stack membrane of the silicide of refractory metal etc.The thickness of gate electrode, for example the thickness formation with 50～400nm is suitable.Under gate electrode, form channel region.
The memory function body has the function (" electric charge maintenance function ") that keeps electric charge at least.In other words, the memory function body comprises film or the zone that has accumulation, keeps electric charge, catches electric charge, keeps the function of charge polarization state.What reach these functions can be: silicon nitride; Silicon; The silicate glass that contains impurity such as phosphorus, boron; Silicon carbide; Aluminium oxide; High dielectrics such as hafnium oxide, Zirconium oxide, tantalum pentoxide; Zinc oxide; Strong dielectric; Metal etc.The memory function body is formed by the individual layer or the stromatolithic structure that contain following dielectric film etc., contains the insulator film of silicon nitride film that is:; The insulator film of conducting film or semiconductor layer is contained in inside; The insulator film that contains 1 above electric conductor or semiconductor point; By the electric field polarization internal charge, and keep the strong dielectric film of its state.Wherein, silicon nitride film is owing to exist a plurality of energy levels of catching electric charge can obtain big hysteresis characteristic, and, because charge retention time is long, the charge leakage problem that leakage path produces can not appear, so retention performance is good, in LSI processing, preferably use the very material of standard.
Keep the dielectric film of the insulator of function to use owing to will contain the electric charge that possesses silicon nitride film etc., then can improve the reliability that keeps about storage as the memory function body in inside.Because silicon nitride film is an insulator, then when its part produced charge leakage, whole electric charges of silicon nitride film can not lose immediately yet.When configuration during a plurality of memory element, even shorten distance between memory element, adjacent memory function body contact can not lose each memory function body canned data yet as the situation that the memory function body is made of electric conductor.In addition, owing to contact bolt (contact plug) and memory function body closer can be disposed, also can according to circumstances dispose, so can realize becoming more meticulous of memory element easily with the memory function body weight is folded.
To keep relevant reliability in order improving with storage, to have the insulator that keeps the electric charge function, needn't be membranaceous, has to keep the insulator of electric charge function also can be present in the dielectric film discretely.Specifically, be difficult to keep the material of electric charge, for example in Si oxide, the insulator point-like can be disperseed also to be fine.
And, use as the memory function body owing to inside is contained the insulator film of conducting film or semiconductor layer, then can freely control the injection rate of electric charge in electric conductor or semiconductor, have the effect that is easy to many-valuedization.
Because the insulator film that will contain 1 above electric conductor or semiconductor point, then carries out the cancellation that writes according to the direct tunnel effect of electric charge easily as the use of memory function body, has the effect of low consumption electrification.
As the memory function body, also can use strong dielectric film by PZT (lead zirconate titanate, lead zirconate titanate), the PLZT (lanthanumdoped lead zirconate-lead titanate, lead lanthanum zirconate titanate) etc. of electric field change polarised direction.At this moment, produced electric charge in fact owing to be polarized in the surface of strong dielectric film, and remained on this state.Therefore, outside film, supply with electric charge with memory function, can obtain and catch the same hysteresis characteristic of film of electric charge, and, the electric charge of strong dielectric film keeps, unnecessary from the outer electric charge injection of film, only because the charge polarization in the film can obtain hysteresis characteristic, so have the effect that writes cancellation at a high speed.
Just, the memory function body preferably contains and makes the zone that electric charge is difficult to escape or have the film that makes the function that electric charge is difficult to escape.As bringing into play the film that makes the function that electric charge is difficult to escape, for example be silicon oxide layer etc.
The charge holding film that the memory function body contains, directly or be formed at the both sides of gate electrode by dielectric film, and, be configured on the semiconductor layer (Semiconductor substrate, well area, body region or regions and source or diffusion zone) by gate insulating film or dielectric film.The charge holding film of gate electrode both sides preferably directly or by dielectric film forms with all or part of of covering grid electrode sidewall.As application examples, when gate electrode has recess in the bottom, also can directly or by dielectric film form to imbed the part of recess or recess fully.
Gate electrode preferably only forms at the sidewall of memory function body, perhaps the top of overlaying memory functive not.According to such configuration, owing to contact bolt can closer dispose with gate electrode, so be easy to realize becoming more meticulous of memory element.And the memory element with this easy configuration is made easily, can improve rate of finished products.
When adopting conducting film or semiconductor layer as charge holding film, preferably be configured so that charge holding film does not directly contact with semiconductor layer (Semiconductor substrate, well area, body region or regions and source or diffusion zone) or gate electrode by dielectric film.For example can be: the stromatolithic structure of conducting film and dielectric film; The structure that in dielectric film, the conducting film point-like is disperseed; The structure that a part in the side wall insulating film that gate lateral wall forms is configured etc.
Diffusion zone can have the function of regions and source, has the contrary conductivity type with semiconductor layer or well area.The knot of diffusion zone and semiconductor layer or well area, the preferably impurity concentration sudden turn of events.Hot electron and hot hole high efficiency under low-voltage produces, and is because the action of available more low voltage, high-speed.The junction depth of diffusion zone, there is no particular limitation, can be according to the performance of the semiconductor storage that will obtain etc., suitably adjust.When adopting the SOI substrate as Semiconductor substrate, diffusion zone can have the junction depth less than surperficial semiconductor layer thickness, but also can have and the roughly the same junction depth of surperficial semiconductor layer thickness.
Diffusion zone can with gate electrode end overlay configuration, also can dispose with the gate electrode end is consistent, can also be with respect to gate electrode end offset configuration.Particularly under drift condition, when applying voltage on gate electrode, the offset area under the charge holding film is easy to counter-rotating, and the quantity of electric charge tired according to the memory function volume carries out big variation, the storage effect increases, so and to cause the attenuating of short-channel effect be desirable.But, when too being offset, because the drive current between diffusion zone (source drain) significantly diminishes, compare with thickness, wish that side-play amount is just shorter to the distance of approaching diffusion zone from a gate electrode end of grid length direction with respect to the charge holding film of grid length direction parallel direction.Particularly importantly, have at least a portion in the film or the zone, particularly charge accumulation region of electric charge maintenance function in the memory function body, overlapping with the part of diffusion zone.The essence that is used for the memory element of semiconductor storage of the present invention is that according to gate electrode that exists only in memory function body sidewall portion and the voltage difference between diffusion zone, the electric field of memory function body is crossed in utilization, and storage is rewritten.
When diffusion zone when gate terminal begins to carry out offset configuration, only one of 2 diffusion zones skew, but wish that the diffusion zone both sides are offset.
When the diffusion zone both sides were offset, 1 memory element can be stored 2 information.And because the diffusion zone both sides are offset, then the situation than only one of diffusion zone skew can suppress short-channel effect very effectively.In addition, the operation of necessity does not need the additional necessary enough and to spare of above-mentioned operation yet when having cut down only side's diffusion zone skew.As seen from above-mentioned, both sides are offset by diffusion zone, are easy to becoming more meticulous of memory element and memory cell array, can realize more highly integratedly, cut down manufacturing cost.
Diffusion zone, its part can extend the more high position below the channel region surface promptly is higher than gate insulating film.At this moment, on the diffusion zone that forms in Semiconductor substrate, it is suitable constituting with the incorporate conducting film lamination of this diffusion zone.Conducting film can be: semiconductor, silicide, above-mentioned metal, refractory metals etc. such as poly-silicon, amorphous silicon.Wherein, poly-silicon is best.Poly-silicon because diffusion of impurities speed greatly in Semiconductor substrate, then easily makes the junction depth of regions and source in the Semiconductor substrate more shallow, suppresses short-channel effect easily.At this moment, the part of this diffusion zone preferably is configured at least a portion of clamping memory function body with gate electrode.
The memory element that is used for semiconductor storage of the present invention can adopt common semiconductor machining operation to form, and for example, adopts the same method formation of method that forms the side wall spacer of individual layer or stromatolithic structure with the sidewall at gate electrode or word line.Specifically, these methods are: after forming gate electrode or word line, formation comprises the monofilm or the stack membrane of the charge holding film of charge holding film, charge holding film/dielectric film, dielectric film/charge holding film, dielectric film/charge holding film/dielectric film etc., carry out etch-back (etchingback) under proper condition, make these films keep the method for side wall spacer shape; Form dielectric film or charge holding film, carry out etch-back under proper condition, keep the side wall spacer shape, form charge holding film or dielectric film again, similarly carry out etch-back, keep the method for side wall spacer shape; Keep the insulating film material of dispersion of materials to apply or be deposited on the Semiconductor substrate that contains gate electrode the graininess electric charge, carry out etch-back under proper condition, make insulating film material keep the method for side wall spacer shape; After forming gate electrode, form above-mentioned monofilm or stack membrane, the use mask carries out the method for pattern formation etc.In addition, before forming gate electrode or electrode, form charge holding film, charge holding film/dielectric film, dielectric film/charge holding film, dielectric film/charge holding film/dielectric film etc., form opening in zone as the channel region of these films, on its whole, form the gate material film, according to comprising the big shape of opening and ratio open, this gate material film is carried out the method that pattern forms.
Below, an example of above-mentioned memory element formation method is described.
At first, according to known program, on Semiconductor substrate, form gate insulating film and gate electrode.Then, on whole above-mentioned Semiconductor substrate, form or with CVD (Chemical VaporDeposition) method accumulation thickness 0.8～20nm, the silicon oxide layer of thickness 3～10nm preferably with thermal oxidation method.Then, on whole above-mentioned silicon oxide layer, pile up thickness 2～15nm, the silicon nitride film of 3～10nm preferably with the CVD method.On whole above-mentioned silicon nitride film, pile up the silicon oxide layer of 20～70nm with the CVD method again.
Then, adopt anisotropic etching, silicon oxide layer/silicon nitride film/silicon oxide layer is carried out etch-back, in gate electrode sidewall the most suitable memory storing functive is formed the side wall spacer shape thus.
After this, the memory function body of above-mentioned gate electrode and side wall spacer shape is carried out ion as mask inject, form diffusion layer region (regions and source) thus.Then, according to known program evolution silicide operation and top distribution operation.
When arrangement was used for the memory element formation memory cell array of semiconductor storage of the present invention, the best form of memory element was to satisfy following necessary condition (1)～(10) fully.
(1) gate electrode of a plurality of memory elements is an one, has the function of word line.
(2), form the memory function body that extends continuously along this word line respectively in the both sides of above-mentioned word line.
(3) having the stored charge materials with function in the memory function body is insulator, particularly silicon nitride film.
(4) the memory function body is made of ONO (Oxide Nitride Oxide) film, and silicon nitride film has the surface with the surperficial almost parallel of gate insulating film.
(5) silicon nitride film in the memory function body is isolated with silicon oxide layer with word line and channel region.
(6) zone (for example zone that is made of silicon nitride film) that has the stored charge function in the memory function body is overlapping with diffusion layer.
(7) isolate and to have and the silicon nitride film on the surface of gate insulating film surface almost parallel and the insulator film thickness of channel region or semiconductor layer, be different from the thickness of gate insulating film.
Write and the cancellation action of (8) 1 memory elements are undertaken by single word line.
(9) do not have on the memory function body the auxiliary electrode (word line) that writes with the cancellation holding function.
(10) part that is connected with diffusion zone under the memory function body has the denseer zone of impurity concentration with the conductivity type opposite conductivity type of diffusion zone.
The memory element that is used for semiconductor storage of the present invention also not necessarily satisfies necessary condition (1)～(10) certainly fully, and one of them is also passable to satisfy necessary condition (1)～(10).
In satisfying above-mentioned necessary condition (1)～(10), during a plurality of necessary condition, there is special Ideal Match.For example, be necessary that having the stored charge materials with function in condition (3) the memory function body is insulator, particularly silicon nitride film, necessary condition (9) does not have assists the electrode (word line) that writes with the cancellation holding function on the memory function body, necessary condition (6) has the zone (for example zone that is made of silicon nitride film) and the overlapping situation of diffusion layer of stored charge function in the memory function body.Just, be used for the memory element of semiconductor storage of the present invention, the situation that satisfies necessary condition (3), (9) and (6) is desirable especially.
When satisfying above-mentioned necessary condition (3) and necessary condition (9), can obtain following very large effect.At first, the memory function body of bit line contact and sidewalls of wordlines closer can be disposed, even the distance perhaps between memory element is approaching, a plurality of memory function bodies also can not keep stored information intrusively, then are easy to becoming more meticulous of memory element.When the electric charge holding region territory in the memory function body is conductor, because capacitive coupling, interference will appear in approaching along with between memory element between the electric charge holding region territory, can not keep stored information.
When the electric charge holding region territory in the memory function body is insulator (for example silicon nitride film), needn't make the memory function body independent in each memory cell.For example,, needn't separate by each memory cell along the memory function body that word line forms continuously in the both sides of 1 total word line of a plurality of memory cell, a plurality of memory cell of total word line can have the memory function body that forms 1 word line both sides.Therefore, do not need photoengraving, the etching work procedure of split memory functive, manufacturing process has simplified.And, owing to do not need the contraposition enough and to spare of photoengraving, do not need etched film to reduce enough and to spare yet, then can dwindle the enough and to spare between memory cell.Therefore, with electric charge holding region territory in the memory function body be electric conductor (for example polysilicon film) situation relatively, promptly use same retrofit level to form, the effect that the memory cell occupied area is become more meticulous is also arranged.When the electric charge holding region territory in the memory function body was electric conductor, the photoengraving, the etching work procedure that separate the memory function body by each memory cell were essential, and it also is necessary that the contraposition enough and to spare of photograph, etched film reduce enough and to spare.
Because it is simple not possessing the auxiliary component construction that writes with the electrode of cancellation holding function on the memory function body, then can reduce process number, improves rate of finished products, realizes easily carrying with transistorized the mixing that constitutes logical circuit and analog circuit.
In addition, as very important design item, when satisfying necessary condition (3) and (9), when satisfying necessary condition (6) again, we find to write with low-down voltage, cancellation.Specifically, affirmation can write with cancellation with 5V or following low-voltage and move.This acts on has very big effect on the circuit design.Just, in chip, needn't form the such high voltage of flash memory, therefore omit the charging suction circuit that very big occupied area must be arranged, perhaps can reduce scale.Particularly, when the memory of capacity on a small scale as adjust with in when being loaded on logic LSI, the occupied area of memory section and memory cell are relatively, the occupied area that drives the peripheral circuit of memory cell has dominating role, therefore, omit the memory cell voltage booster, its scale is reduced, the most effective to dwindling chip size.
According to the above, be used for the memory element of semiconductor storage of the present invention, satisfy necessary condition (3), (9) and (6) are desirable especially.
On the other hand, when not satisfying necessary condition (3), just in the memory function body, keep electric charge be electric conductor the time; Do not satisfy necessary condition (6),, can carry out write activity yet even when electric conductor just in the memory function body and diffusion zone are not overlapping.This is because the electric conductor utilization in the memory function body and the capacitive coupling of gate electrode (writing electrode) write auxiliary.
When not satisfying necessary condition (9), just have when on the memory function body, possessing the auxiliary electrode that writes with the cancellation holding function; Do not satisfy necessary condition (6), when just insulator in the memory function body and diffusion zone are not overlapping, can carry out write activity yet.
Under the situation with the memory cell array of a plurality of arrangements of memory element, respectively in the both sides of single word line, the memory function body that formation is made of a kind or above insulating material by total this word line of a plurality of memory elements and 2 memory function bodies forming in each side of this word line, is desirable." single word line " described as defined above.
When adopting this formation, satisfied above-mentioned necessary condition (3), (9) and (6) in fact, therefore under situation, also had above-mentioned effect the memory cell array of a plurality of arrangements of memory element.The word line of selecting when carrying out the information rewriting of above-mentioned memory element, if when only being above-mentioned single word line, the word line number minimum that storage action is needed is so can make the memory cell array high density integrated.
Semiconductor storage of the present invention, make up with logic element or logical circuit etc., can use as follows thus widely: data handling systems such as personal computer, notebook, laptop computer, individual assisting/transmitter, minicom, work station, main frame, multi-processor computer or other various computer systems; The electronic component of data handling systems such as CPU, memory, composition data storage device; Personal handyphone system), communicating machine such as modulator-demodulator, router phone, PHs (Personal Handy-phone System:; Image diplay such as display panel, projector; Business machines such as inker, scanner, photocopier; Gamma camera such as TV camera, digital camera; Entertainment machine such as game machine, music phonograph; Pagers such as portable data assistance, clock and watch, e-dictionary; Vehicle-mounted machine devices such as car steering guidance system, automobile audio; AV (Audio Visual) machine of information such as record, regeneration animation, static picture, music; Electronic products such as washing machine, microwave oven, refrigerator, electric cooker, dish cleaning machine, dust catcher, air conditioner; Health control machines such as massager, batheroom scale, sphygmomanometer; E-machines such as portable recorder such as IC-card, storage card.Particularly be effectively applied to: portable electronic machines such as portable phone, portable data assistance, IC-card, storage card, portable computer, portable game machine, digital camera, portable animation player, portable music phonograph, e-dictionary, clock and watch.Semiconductor storage of the present invention, interior at least dress e-machine control circuit or data storage circuitry get a part of, perhaps can load and unload as required.
Below, before the execution mode that describes semiconductor storage of the present invention and portable electronic machine with reference to the accompanying drawings in detail, for easy to understand the present invention, description references example at first.
The 1st reference example
The present invention's the 1st reference example partly lead storage device, as shown in Figure 1, have the memory element 1 of non-volatile memory device.This memory element 1 forms single gate electrode 104 by gate insulating film 103 on the P type well area 102 of Semiconductor substrate 101 surface formation.
Top and the side of gate electrode 104 is covered by the silicon nitride film 109 as the charge holding film with the trap level that keeps electric charge.The part of these silicon nitride film 109 contact gate electrodes 104 sides, just the two side part of silicon nitride film 109 has constituted the memory function body 105a, the 105b that accumulate the maintenance electric charge in fact respectively.In gate electrode 104 both sides, in the P type well area 102, form N type diffusion zone 107a, 107b respectively with source region or drain region function. Diffusion zone 107a, 107b have offset configuration.Just, diffusion zone 107a, 107b can not arrive gate electrode lower area 121.Just, diffusion zone 107a, 107b do not arrive gate electrode lower area 121, and the offset area 120,120 of isolate gate electrode lower area 121 and diffusion zone 107a, 107b is positioned at the below of memory function body 105a, 105b.Give the impurity concentration of offset area 120,120P type, compare, effectively weaken with the impurity concentration of giving gate electrode lower area 121P type.Above-mentioned gate electrode lower area 121 and offset area 120,120 constitute channel region 122.
Keep the memory function body 105a of electric charge, the both sides that 105b is positioned at gate electrode 104 in fact.Therefore, can only form silicon nitride film in the both sides of gate electrode 104.Just, the part on the gate electrode 104 of above-mentioned silicon nitride film 109 can not have.
In gate electrode 104 both sides, can form dielectric film as the memory function body.At this moment, to have the Particle Distribution that electric conductor or semiconductor by nano-scale constitute be to scatter the structure of shape to above-mentioned dielectric film.When the not enough 1nm of above-mentioned particulate, because the quantum effect is excessive, electric charge is difficult to tunnel on point, when surpassing 10nm, can not occur significant quantum effect under the room temperature.Therefore, the diameter of the above-mentioned particulate scope of 1nm～10nm preferably.
As the silicon nitride film 109 of charge holding film, also can form the side wall spacer shape in the side of gate electrode.
Above-mentioned semiconductor storage can have memory element 2 shown in Figure 2.Not being both of the memory element 1 of this memory element 2 and Fig. 1: 1st, the 2nd memory function body 131a, 131b have the trap level that keeps electric charge respectively, have structure by silicon oxide layer 111,112 clampings as the silicon nitride film 113 of charge holding film.As shown in Figure 2, because silicon nitride film 113 becomes the structure by silicon oxide layer 111 and silicon oxide layer 112 clampings, the electric charge injection efficiency in the time of then can improving rewrite action, more high speed motion.
Among Fig. 2, also silicon nitride film 113 can be replaced into strong dielectric.
Below, utilize Fig. 3 and Fig. 4 that the write activity principle of above-mentioned memory element 2 is described.Here, have for the 1st ｀ the 2nd memory function body 131a, 131b and keep the situation of electric charge function to be illustrated.Omission is described, but above-mentioned operating principle also is the same for memory element 1.
Here, what is called writes and is meant that memory element 2 is under the N channel-type situation, is injected into the 1st, the 2nd memory function body 131a, 131b with electronics.After, memory element describes as the N channel-type.
For electronics is injected (writing) to the 2nd memory function body 131b, as shown in Figure 3, gate electrode 104 is connected to word line WL, simultaneously the 1st, the 2nd diffusion zone 107a, 107b are connected to the 1st, the 2nd bit line BL1, BL2, N type the 1st diffusion zone 107a as the source region, N type the 2nd diffusion zone 107b as the drain region.For example, apply OV, apply+5V, apply+5V at gate electrode 104 at the 2nd diffusion zone 107b at the 1st diffusion zone 107a and P type well area 102.Such when applying voltage when carrying out, inversion layer 226 extends from the 1st diffusion zone 107a (source region), but pinch-off point (pinch point) takes place no show the 2nd diffusion zone 107b (drain region).Electronics is quickened by high electric field from pinch-off point to the 2 diffusion zone 107b (drain region), forms so-called hot electron (high energy conduction electron).Utilizing this hot electron to be injected into the 2nd memory function body 131b writes.Near the 1st memory function body 131a,, then do not write because hot electron does not take place.
On the other hand, for electronics is injected (writing) to the 1st memory function body 131a, as shown in Figure 4, with the 2nd diffusion zone 107b as the source region, with the 1st diffusion zone 107a as the drain region.For example, apply OV, apply+5V, apply+5V at gate electrode 104 at the 1st diffusion zone 107a at the 2nd diffusion zone 107b and P type well area 102.Like this, when the 2nd memory function body 131b injects electronics,, electronics is injected into the 1st memory function body 131a, can writes by conversion source region and drain region.
Below, utilize Fig. 5 and Fig. 6 that the cancellation operating principle of memory element 2 is described.
Cancellation is at the 1st elimination method of the 1st memory function body 131a canned data, as shown in Figure 5, (for example+5V) apply positive voltage at the 1st diffusion zone 107a, apply OV at P type well area 102, PN junction at the 1st diffusion zone 107a and P type well area 102 applies bias voltage in the other direction, (for example-5V) applies negative voltage at gate electrode 104 again.At this moment, near the gate electrode 104 in above-mentioned PN junction,, produce steeper current potential gradient owing to applied the influence of the gate electrode 104 of negative voltage.Therefore, owing to can produce hot hole (high energy holes) in the P of PN junction type well area 102 sides in the interband tunnel.This hot hole is introduced in grid 104 directions with negative potential, and the result can carry out the hole at the 1st memory function body 131a and inject.Like this, realized the cancellation of the 1st memory function body 131a.At this moment, the 2nd diffusion zone 107b can apply OV.
When cancellation the 2nd memory function body 131b canned data, in above-mentioned the 1st elimination method, can change the current potential of the 1st diffusion zone 107a and the 2nd diffusion zone 107b.For example, can apply positive voltage at the 2nd diffusion zone 107b (for example+5V), applies OV at the 1st diffusion zone 107a and P type well area 102, (for example-5V) applies negative voltage at gate electrode 104.
In the 2nd elimination method of cancellation the 1st memory function body 131a canned data, as shown in Figure 6, (for example+4V) apply positive voltage at the 1st diffusion zone 107a, apply OV at the 2nd diffusion zone 107b, apply negative voltage at gate electrode 104 and (for example-4V), (for example+0.8V) apply positive voltage at P type well area 102.At this moment, apply forward voltage (forward voltage) between P type well area 102 and the 2nd diffusion zone 107b, electronics is injected into P type well area 102.Injected electrons is diffused into the PN junction of P type well area 102 and the 1st diffusion zone 107a, is quickened by highfield there, forms hot electron.This hot electron produces electron hole pair at PN junction.Just, by apply forward voltage between P type well area 102 and the 2nd diffusion zone 107b, the electronics that is injected into P type well area 102 becomes trigger, at the PN junction generation hot hole of the 1st diffusion zone 107a and P type well area 10.The hot hole that produces at this PN junction is introduced in gate electrode 104 directions with negative potential, and the result carries out the hole at the 1st memory function body 131a and injects.
According to the 2nd elimination method, at the PN junction of P type well area 102 and the 1st diffusion zone 107a, only apply be not enough to by can interband tunnel when producing the voltage of hot hole, from the 2nd diffusion zone 107b injected electrons, form the trigger that electron hole pair produces at PN junction, can produce hot hole.Therefore, the voltage in the time of can reducing the cancellation action.When particularly having offset area 120 (with reference to Fig. 1), owing to applied the gate electrode 104 of negative potential, the effect of PN junction sudden change is less.Therefore, can be difficult to produce hot hole in the interband tunnel, and the 2nd elimination method has compensated this shortcoming, can enough low-voltages realize the cancellation action.
When cancellation the 1st memory function body 131a canned data, use the 1st elimination method, must apply+5V at the 1st diffusion zone 107a, and use the 2nd elimination method, only apply+4V at the 1st diffusion zone 107a.Like this, above-mentioned the 2nd elimination method, voltage in the time of can reducing cancellation so reduce power consumption, suppresses the memory element deterioration that hot carrier causes.
In any of above-mentioned the 1st elimination method and the 2nd elimination method, the cancellation of crossing of memory element all is difficult to take place.Here what is called is crossed cancellation, is the increase along with the tired hole amount of memory function volume, the phenomenon that undersaturated threshold value reduces.This cancellation excessively, for EEPROM (the Electrically Erasable Programmable Read-only Memory: be big problem electric cancellation programmable read only memory) that with the flash memory is representative, particularly in threshold value when negative, it is bad that the fatal action that so-called memory cell can not select can take place.On the other hand, even above-mentioned memory element 1,2 when the memory function volume has tired out a large amount of hole, owing to only bring out electronics under the memory function body, therefore, influences the current potential in gate insulating film lower channel zone hardly.Because the threshold value during cancellation then is difficult to cause cancellation by the decision of the current potential under the gate insulating film.
Below, utilize Fig. 7 that the operating principle of reading of memory element 2 is described.
When reading the 1st memory function body 131a canned data, as the source region, as the drain region, make memory element 2 the 2nd diffusion zone 107b the 1st diffusion zone 107a as transistor action.For example, apply OV, apply+1.8V, apply+2V at gate electrode 104 at the 2nd diffusion zone 107b at the 1st diffusion zone 107a and P type well area 102.At this moment, when the 1st memory function body 131a did not accumulate electronics, drain current flow through easily.On the other hand, when the 1st memory function body 131a accumulation electronics, owing to be difficult to form inversion layer near the 1st memory function body 131a, then drain current is difficult to flow through.Therefore, by detecting drain current, can read the stored information of the 1st memory function body 131a.Particularly move (pinch off) when voltage is read when applying pinch off, the electric charge accumulated state of the 1st memory function body 131a, the electric charge that can not be subjected to the 2nd memory function body 131b accumulates the influence that has or not, and can carry out more high-precision judgement.
When reading the 2nd memory function body 131b canned data, as the source region, as the drain region, make memory element 2 the 1st diffusion zone 107a the 2nd diffusion zone 107b as transistor action.Not shown, for example, apply OV at the 2nd diffusion zone 107b and P type well area 102, apply+1.8V at the 1st diffusion zone 107a, apply+2V at gate electrode 104.Like this, with respect to the situation of reading the 1st memory function body 131a canned data,, then can carry out reading of the 2nd memory function body 131b canned data by having changed regions and source.
When leaving the unlapped channel region 122 of gate electrode 104, when just having offset area 120, at offset area 120, according to having or not of the 1st, the 2nd memory function body 131a, 131b residual charge, inversion layer disappears, and perhaps, inversion layer forms.Its result has obtained big magnetic hysteresis (variation of threshold value).But when the width of offset area 120 was excessive, drain current significantly reduced, and reading speed is slack-off significantly.Therefore, preferably according to obtaining enough magnetic hysteresis and reading speed, the width of decision offset area 120.
As the 1st, the 2nd diffusion zone 107a, when 107b reaches gate electrode 104 ends, just, when 1st, the 2nd diffusion zone 107a, 107b and gate electrode 104 are overlapping, write activity can change the threshold value of memory element 2 hardly, but the dead resistance in source/drain terminal alters a great deal, and drain current reduces a lot (more than 1).Therefore, utilize detecting of drain current, can read, obtain function as memory.But when the bigger memory hysteresis effect of needs, best the 1st, the 2nd diffusion zone 107a, 107b and gate electrode 104 are not overlapping.Just, at this moment wish to exist offset area 120.
According to above principle, per 1 transistor can be selected 2 write, cancellation and read.Arrange a plurality of memory elements 2, respectively word line WL is connected to gate electrode 104, the 1st bit line BL1 is connected to the 1st diffusion zone 107a, the 2nd bit line BL2 is connected to the 2nd diffusion zone 107b, can constitute memory cell array thus.
In the above-mentioned method of operating,, carry out 2 writing and cancellation at 1 memory element 2 by conversion source region and drain region, but fixedly source region and drain region, can be with 1 memory element 2 as 1 bit memory work.At this moment, can the number of bit that be connected to regions and source can be reduced by half with one of regions and source as common fixed voltage.
As seen from the above description, the memory element of partly leading storage device of this reference example, memory function body and gate insulating film independently form, and are formed at the both sides of gate electrode, then can 2 bit motions.And, because each memory function body and function gate electrode separates the interference when then having suppressed effectively to rewrite.Because gate insulating film separates with the memory function body, but then filming suppresses short-channel effect.Therefore, realize memory element easily, and then the becoming more meticulous of semiconductor storage.
Among Fig. 3～Fig. 7, omitted the diagram of offset area 120.
In the record of accompanying drawing, for the part of using same material and material, attached and same-sign, but might not represent identical shaped.
Accompanying drawing is an ideograph, and thickness is all different with reality with relation, each layer and each thickness of planar dimension and the ratio of size etc., should note.Therefore, concrete thickness and size dimension should be taken into account that following explanation is judged.Mutual at accompanying drawing, comprise the mutual size relationship part different certainly with ratio.
Each layer and each thickness and size of the present invention's record when not specifying, are the sizes at the net shape of having finished the semiconductor storage formation stage.Thereby with the size comparison behind firm formation film and the extrinsic region, the size of net shape, because the hot resume of later operation etc. will have slight variations, this should note.
The 2nd reference example
The memory element of the semiconductor storage of the present invention's the 2nd reference example, as shown in Figure 8, except the 1st, the 2nd memory function body 261,262 (is the zone of stored charge by the zone that keeps electric charge, also can be to have the film that keeps the electric charge function) and make beyond the formation of the zone that electric charge is difficult to escape (also can be to have the film that makes the function that electric charge is difficult to escape), come down to the formation same with the memory element of Fig. 1.
1st, the 2nd memory function body 261,262 has charge holding film and the dielectric film that keeps the electric charge function from improving the viewpoint of memory retention performance, preferably comprising.Above-mentioned memory element adopts to have the example of the silicon nitride film 242 of the energy level of catching electric charge as charge holding film, and employing has the example of the silicon oxide layer 241,243 of the charge dissipation effect that prevents the charge holding film accumulation as dielectric film.Contain charge holding film and dielectric film by the 1st, the 2nd memory function body 261,262, then can prevent charge dissipation, improve retention performance.And, when the 1st, the 2nd memory function body 261,262 contains charge holding film and dielectric film, only compare with the 1st, the 2nd memory function body 261,262 by the situation that charge holding film constitutes, can appropriate reduce the volume of charge holding film, electric charge in the restriction charge holding film moves, and can suppress electric charge in storage keeps and move the characteristic variations that causes.In addition and since be silicon nitride film 242 by the structure of silicon oxide layer 241,243 clampings, ONO structure just, the electric charge injection efficiency in the time of then can improving rewrite action, action more at high speed.In this memory element, also can replace silicon nitride film 242 with strong dielectric.
The silicon nitride film 242 that keeps the electric charge of the 1st, the 2nd memory function body 261,262, overlapping with the 1st, the 2nd diffusion zone 212,213 respectively.Here, so-called overlapping, mean at least a portion zone of the 1st, the 2nd diffusion zone 212,213, there is at least a portion that keeps charge area (silicon nitride film 242).
Among Fig. 8, the 211st, P type semiconductor substrate, the 214th, gate insulating film, the 217th, gate electrode, the 212nd, N type the 1st diffusion zone, the 213rd, N type the 2nd diffusion zone, the 270th, gate electrode lower area, the 271st, offset area, the 272nd, channel region, the 281st, the horizontal zone of silicon nitride film 242.This offset area 271 is offset areas of gate electrode 217 and the 1st, the 2nd diffusion zone 212,213.Gate electrode lower area 270 and offset area 271 constitute channel region 272.Channel region 272 is present between the 1st diffusion zone 212 and the 2nd diffusion zone 213.Just, form the 1st diffusion zone 212, form the 2nd diffusion zone 213 in the opposing party side of above-mentioned channel region in a side's of above-mentioned channel region side.1st, the 2nd memory function body 261,262 is in horizontal zone 281 stored informations of silicon nitride film 242.This horizontal zone 281 is in the zone of silicon nitride film 242 with respect to the surperficial almost parallel extension of Semiconductor substrate 211.
Carry out overlapping effect for silicon nitride film 242 and the 1st, the 2nd diffusion zone 212,213, illustrated as the zone that keeps the 1st, the 2nd memory function body 261,262 electric charges.
Fig. 9 is the expanded view of the 2nd memory function body 262 peripheries.As shown in Figure 9, at the 2nd memory function body 262 peripheries, the side-play amount of setting gate electrode 217 and the 2nd diffusion zone 213 is W1, the width of the 2nd memory function body 262 that is set in raceway groove length direction (left and right directions among the figure) section of gate electrode 217 is W2, and then the lap of the 2nd memory function body 262 and the 2nd diffusion zone 213 is represented with W2-W1.Here the 2nd memory function body 262 that importantly is made of silicon nitride film 242 in the 2nd memory function body 262 is overlapping with the 2nd diffusion zone 213, just satisfies W2〉relation of W1.
In the 2nd memory function body 262 of Fig. 9, leave an end of gate electrode 217 sides of silicon nitride film 242, consistent with an end of the 2nd memory function body 262 that leaves gate electrode 217 sides, so the width of the 2nd memory function body 262 is defined as W2.
As shown in figure 10, when constituting the 2nd memory function body 1262 by silicon nitride film 1242 and silicon oxide layer 1241,1243, the end that the gate electrode 217 of the 2nd memory function body 1262 is opposed side opposes that with the gate electrode 217 of silicon nitride film 1242a an end of side is inconsistent.Just, among the figure of the 2nd memory function body 1262 among the figure of an end on right side and silicon nitride film 1242 end on right side inconsistent.At this moment, from an end of gate electrode 217 sides of the 2nd memory function body 1262, the end up to the opposition side of the gate electrode 217 of silicon nitride film 1242 can be defined as W2.
Figure 11 is in the structure of the memory element of Fig. 9, and expression is fixed as 100nm with W2, the variation of the drain current Id when changing W1.Here, the method for asking of drain current Id is: the 2nd memory function body 262 is set at erased condition (accumulation hole), establishes the 1st diffusion zone 212 and be the source region, establish the 2nd diffusion zone 213 and be the drain region, the use device simulation is obtained.
From Figure 11 as seen, when W1 is 100nm or when above, just, when not overlapping, drain current Id sharply reduces silicon nitride film 242 with diffusion zone 213.Because the drain current value with to read responsiveness roughly proportional, is then established W1 and is 100nm or when above, the performance of memory element is deterioration rapidly.On the other hand, in the overlapping scope of silicon nitride film 242 and diffusion zone 213, the minimizing of drain current Id is slow.Therefore, when in a large amount of the manufacturing, considering deviation,, then in fact be difficult to obtain memory function if not overlapping as at least a portion and the regions and source (the 1st, the 2nd diffusion zone 211,213) of silicon nitride film 242 with the film that keeps the electric charge function.
According to the said apparatus Simulation result, W2 is fixed as 100nm, W1 is set at 60nm and 100nm as design load, make memory cell array.When W1 was 60nm, silicon nitride film 142 and the 1st, the 2nd diffusion zone 212,213 were undertaken overlapping by design load 40nm; When W1 is 100nm, not overlapping as design load.Measure the readout time of these memory cell arrays, its result compares according to the worst case of considering deviation, is that the situation of 100nm is compared with the W1 design load, and when the W1 design load was 60nm, read access time was 100 times of high speeds.In the practicality, preferably per 1 100 nanosecond or following of read access time, but work as W1=W2, can not finish this condition.When considering manufacture deviation, preferably (W2-W1)〉10nm.
As shown in Figure 9, reading of horizontal zone 281 canned datas of the 1st memory function body 261, the same with above-mentioned the 1st reference example, preferably with the 1st diffusion zone 212 as the source region, as the drain region, drain region one side forms pinch-off point (pinchoff point) near channel region 272 with the 2nd diffusion zone 213.Just, when reading one of the 1st, the 2nd memory function body 261,262 canned data, be preferably in the channel region 272,, form pinch-off point near another the zone in the 1st, the 2nd memory function body 261,262.Like this, no matter what the memory state of another in the 1st, the 2nd memory function body 261,262 adds, can detect the stored information of one of the 1st, the 2nd memory function body 261,262 in high sensitivity.Therefore, when reading one of the 1st, the 2nd memory function device 261,262 canned data, in channel region 272, form pinch-off point near another the zone in the 1st, the 2nd memory function body 261,262, this is the key element that can carry out 2 bit motions.
On the other hand, when only when one of the 1st, the 2nd memory function body 261,262 stored information is used, perhaps, when making the 1st memory function body 261 and the 2nd memory function body 262 be in identical store status to use, then when reading, information can not necessarily form pinch-off point.
Not shown among Fig. 8, but wish to form well area (being P type trap during the N channel element) on the surface of Semiconductor substrate 211.By forming above-mentioned well area, make the impurity concentration of channel region be suitable for memory action (rewrite action and read action) most, and control other electrical characteristics (withstand voltage, junction capacitance, short-channel effect) easily.
The memory function body preferably contains the charge holding film with respect to the almost parallel configuration of gate insulating film surface.In other words, above the charge holding film of memory function body, preferably be configured in from semiconductor substrate surface distance about equally.As an example that has with respect to the top charge holding film of semiconductor substrate surface almost parallel, be the silicon nitride film 2242 of the 2nd memory function body 2262 shown in Figure 12.The 2nd memory function body 2262 is made of silicon nitride film 2242 and silicon oxide layer 2444, and silicon nitride film 2242 has the face with respect to gate insulating film 214 surperficial almost parallels.In other words, whole silicon nitride film 2242 is that benchmark is positioned at roughly the same height with the surface of gate insulating film 214.
In the 2nd memory function body 2262, by the silicon nitride film 2242 of existence with gate insulating film 214 surperficial almost parallels, what then can control the formation easness of the inversion layer of offset area 271 effectively, and then increase the storage effect according to the electric charge of silicon nitride film 2242 accumulation.And, be roughly parallel to the surface of gate insulating film 214 by making silicon nitride film 2242, even then in side-play amount (W1) when deviation occurring, the variation that also can keep storing effect is less, can suppress to store the deviation of effect.And, also can suppress electric charge and move to silicon nitride film 2242 upper direction, be suppressed in the storage maintenance and move the characteristic variations that causes because of electric charge.
The 2nd memory function body 2262 preferably contains the dielectric film (for example part on the offset area 271 in the silicon oxide layer 244) of will isolate with the silicon nitride film 2242 and the channel region (perhaps well area) of the surperficial almost parallel of gate insulating film 214.Utilize this dielectric film, can suppress the dissipation of the electric charge of charge holding film accumulation, the memory element that the characteristic that is maintained is good.
Thickness by control silicon nitride film 2242, and be certain with the film thickness monitoring of the dielectric film under the silicon nitride film 2242 (part in the silicon oxide layer 2244 on the offset area 271), the distance of the electric charge that accumulates from the surface of Semiconductor substrate 211 to charge holding film roughly can be remained necessarily.Just, can be with the distance of the electric charge that accumulates from the surface of Semiconductor substrate 211 to charge holding film, be controlled at the minimum thickness value of the dielectric film under the silicon nitride film 2242, the maximum ga(u)ge value of the dielectric film under the silicon nitride film 2242 and the maximum film thickness value of silicon nitride film 2242 and between.Like this, can roughly control because the power line density of the charge generation of silicon nitride film 2242 accumulation, make the size deviation of storage effect of memory element very little.
Also can as silicon nitride film 2242, form the horizontal zone 281 of above-mentioned the 1st, the 2nd memory function body 261,262.
The 3rd reference example
The memory function body 262 of the semiconductor storage of the present invention's the 3rd reference example, silicon nitride film 242 as charge holding film, as shown in figure 13, it is roughly uniform thickness, have horizontal zone 281 with respect to the surperficial almost parallel configuration of gate insulating film 214, and with respect to the vertical area 282 of the side almost parallel configuration of gate electrode 217.
When gate electrode 217 applied positive voltage, the power line in the memory function body 262 was shown in arrow 283, and 2 times by silicon nitride film 242.Specifically, above-mentioned power line passes through the horizontal zone 281 of silicon nitride film 242 again by after the vertical area 282 of silicon nitride film 242.When applying negative voltage on gate electrode 217, the direction of power line is an opposite side (with arrow 283 opposite directions).Here, the conductivity of silicon nitride film 242 is about 6, and the conductivity of silicon oxide layer 241,243 is about 4.Therefore, compare, when vertical area 282 and horizontal zone 281 all exist, become big, can make the potential difference at power line two ends littler in the actual conductivity of the memory function body 262 of power line (arrow 283) direction with the situation that only has horizontal zone 281.Just in order to strengthen the electric field of offset area 271, use on gate electrode 217, apply voltage than many parts.
During rewrite action, it is because the electric field of offset area 271 is introduced the electric charge that takes place that electric charge is injected into silicon nitride film 242.Thereby, comprising vertical area 282 by silicon nitride film 242, the electric charge that then is injected into memory function body 262 during rewrite action increases, and overwrite speed strengthens.
When the part of silicon oxide layer 243 also was silicon nitride film, just, charge holding film was when unequal with the surperficial corresponding height of gate insulating film 214, and electric charge moves significantly to the last direction of silicon nitride film, and retention performance worsens.
Charge holding film, the substituted for silicon nitride film is preferably formed by high dielectrics such as the very large hafnium oxide of conductivity.
The memory function body preferably also contains isolation and is roughly parallel to the charge holding film on gate insulating film surface and the dielectric film (part in the silicon oxide layer 241 on the offset area 271) of channel region (perhaps well area).Utilize this dielectric film, can suppress the dissipation of the electric charge of charge holding film accumulation, further improve retention performance.
The memory function body preferably also contains the dielectric film (part that is connected with gate electrode 217 in the silicon oxide layer 241) of isolate gate electrode and the charge holding film that extends in the direction that is roughly parallel to the gate electrode side.Utilize this dielectric film, prevent electrical property change to the charge holding film iunjected charge, can improve the reliability of memory element from gate electrode.
The same with above-mentioned the 2nd reference example, preferably with the film thickness monitoring of the dielectric film under the silicon nitride film 242 (part in the silicon oxide layer 241 on the offset area 271) for roughly certain, the film thickness monitoring that will be configured in the dielectric film (part that is connected with gate electrode 217 in the silicon oxide layer 241) on the gate electrode side is for certain.Like this, can roughly control the density of the power line of the electric charge generation that accumulates by silicon nitride film 242, prevent charge leakage.
The 4th reference example
The 4th reference example of the present invention, the optimization for distance between gate electrode, memory function body and the regions and source of the memory element of semiconductor storage is illustrated.
As shown in figure 14, A is long at the gate electrode of raceway groove length direction section, B is the distance (raceway groove is long) between regions and source, C is the distance from memory function body one end to another memory function body one end, just, from a end with functional membrane of electric charge in the memory function body that remains on raceway groove length direction section (side of leaving with gate electrode) to distance with the end that keeps the functional membrane of electric charge in another memory function body (side of leaving with gate electrode).
This memory element, preferably A＜C.By satisfying this relation, then in channel region, there is offset area 271 between the gate electrode lower area and the 1st under the gate electrode 217, the 2nd diffusion zone 212,213.Like this, utilize the electric charge in silicon nitride film 242 accumulation of the 1st, the 2nd memory function body 261,262, at whole offset area 271, the counter-rotating easiness effectively changes.Therefore, the storage effect increases, and has particularly realized reading the high speed of action.
When gate electrode 217 and the 1st, 212,213 skews of the 2nd diffusion zone, when just A＜B sets up, the counter-rotating easiness of the offset area when gate electrode 217 applies voltage, will be owing to the tired quantity of electric charge of memory function volume, alter a great deal, then store effect and increase, and can lower short-channel effect.
But, in the scope that the storage effect occurs, also can not necessarily have offset area 271.When not having offset area 271, thin if the impurity concentration of the 1st, the 2nd diffusion zone 212,213 enough weighs, at the silicon nitride film 242 of the 1st, the 2nd memory function body 261,262, also can find to store effect.
As shown in figure 11, if at least a portion of silicon nitride film 242 owing in fact be difficult to obtain memory function, is therefore wished B＜C not overlapping with regions and source (the 1st, the 2nd diffusion zone 212,213).
Thereby, A＜B＜C preferably.
The memory element of Figure 14 has the formation same with the memory element of above-mentioned the 2nd reference example in fact.
The 5th reference example
The memory element of the semiconductor storage of the present invention's the 5th reference example, as shown in figure 15, except with the Semiconductor substrate of above-mentioned the 2nd reference example as the SOI substrate, have same formation in fact.
This memory element forms on Semiconductor substrate 286 and imbeds oxide-film 288, and forms soi layer thereon.Form the 1st, the 2nd diffusion zone 212,213 in soi layer, the zone beyond it is a body region 287.
Utilize this memory element, also can bring into play the action effect same with the memory element of above-mentioned the 2nd reference example.And,, then can realize element high speed and low consumption electrification owing to can significantly reduce the junction capacitance of the 1st, the 2nd diffusion zone 212,213 and body region 287.
The 6th reference example
The memory element of the semiconductor storage of the present invention's the 6th reference example, as shown in figure 16, in abutting connection with the raceway groove side of N type the 1st, the 2nd diffusion zone 212,213, except appending P type area with high mercury 291, have the formation same in fact with the memory element of above-mentioned the 2nd reference example.
Give impurity (for example boron) concentration of P type area with high mercury 291P type, be higher than and give gate electrode lower area 292P the impurity concentration of type.Give P type area with high mercury 291P the impurity concentration of type, for example 5 * 10 17～1 * 10 19Cm -3Be suitable.The impurity concentration of the P type of gate electrode lower area 292 for example can be 5 * 10 16～1 * 10 18Cm -3
Like this, by P type area with high mercury 291 is set, then the knot of the 1st, the 2nd diffusion zone 212,213 and Semiconductor substrate 211 suddenlys change under the 1st, the 2nd memory function body 261,262.Therefore, be easy to take place hot carrier writing when moving, can reduce the voltage of write activity and cancellation action, perhaps make write activity and cancellation action high-speed with cancellation.And because the impurity concentration of gate electrode lower area 292 is comparatively thin, then the threshold value of memory when erased condition is lower, and it is big that drain current becomes.Therefore, reading speed improves.Thereby rewriting voltage is lower or overwrite speed is higher, and can obtain the higher memory element of reading speed.
Among Figure 16, near the regions and source (the 1st, the 2nd diffusion zone 212,213), at the 1st, the 2nd memory function body 261,262 times (not under the gate electrode 217),, then significantly rise as all threshold values of memory element by P type area with high mercury 291 is set.This rising degree is compared with the situation of P type area with high mercury 291 under gate electrode 217, enlarges markedly.When accumulating, its difference is bigger when the electric charge that writes at the 1st, the 2nd memory function body 261,262 (being electronics when memory element is the N channel-type).On the other hand, when when the 1st, the 2nd memory function body 261,262 accumulates enough cancellation electric charges (being the hole) when memory element is the N channel-type, as all threshold values of memory element, be reduced to threshold value by the impurity concentration decision of the zone under the gate electrode 217 of channel region (gate electrode lower area 292).Just, the threshold value during cancellation does not exist with ... the impurity concentration of P type area with high mercury 291, writes fashionable threshold value on the other hand and is subjected to very large influence.Thereby, by P type area with high mercury 291 being configured near the regions and source under the memory function body (the 1st, the 2nd diffusion zone 212,213), then only write fashionable threshold value and change very bigly, can enlarge markedly storage effect (threshold value when writing fashionable and cancellation poor).
The 7th reference example
The memory element of the semiconductor storage of the present invention's the 7th reference example, as shown in figure 17, except isolating dielectric film as the channel region of the silicon nitride film 242 of charge holding film and P type semiconductor substrate 211 or well area (for silicon oxide layer 241, the part that is connected with Semiconductor substrate 211) thickness T 1 than the thickness T 2 of gate insulating film 214 thinner outside, have in fact and the same formation of above-mentioned the 2nd reference example.
Above-mentioned gate insulating film 214, the requirement of withstand voltage during according to the memory element rewrite action, there is lower limit in the thickness T 2 of gate insulating film 214.Yet the thickness T 1 of above-mentioned dielectric film is not considered requirement of withstand voltage, can be thinner than the thickness T 2 of gate insulating film 214.
This memory element, higher for the design freedom of the thickness T 1 of dielectric film, it be the reasons are as follows.
If according to this memory element, isolate the channel region of above-mentioned silicon nitride film 242 and Semiconductor substrate 211 or the dielectric film of well area, not by the channel region of gate electrode 217 and Semiconductor substrate 211 or well area clamping.Therefore, on the dielectric film of channel region of isolating above-mentioned silicon nitride film 242 and Semiconductor substrate 211 or well area, the high electric field that works between the channel region of gate electrode 217 and Semiconductor substrate 211 or well area is directly effect not, but from gate electrode 217 working than weak electric field in the transverse direction expansion.Its result can not consider the requirement of withstand voltage of above-mentioned dielectric film (at silicon oxide layer 214, the part that is connected with Semiconductor substrate 211) can make thickness T 1 thinner than thickness T 2.By making thickness T 1 thinner, then the electric charge to the 1st, the 2nd memory function body 261,262 injects easily, can reduce the voltage of write activity and cancellation action, perhaps, can carry out write activity and cancellation action at a high speed, and, when silicon nitride film 242 stored charges, owing to increase at the channel region of Semiconductor substrate 211 or the quantity of electric charge of well area induction, then can strengthen the storage effect.
Yet the power line in the 2nd memory function body 262 shown in the arrow 284 of Figure 13, is the short power line that does not pass through silicon nitride film 242.Because electric field strength is bigger on so short power line, then has great role when the rewrite action along the electric field of this power line.By making thickness T 1 thinner, silicon nitride film 242 moves to the downside of figure, and the power line of arrow 284 directions passes through silicon nitride film.Therefore, become big, can make the potential difference at power line two ends littler along the actual effect conductivity in the 2nd memory function body 212 of arrow 284 direction power lines.Thereby, in order to strengthen the electric field of offset area, use on gate electrode 217, apply voltage than many parts, realized the high-speed of write activity and cancellation action.Omission is described, but in the 1st memory function body 261, power line is the same with Figure 13.
To this, for example,, isolate the dielectric film of floating gate and channel region or well area, because by gate electrode (control grid) and channel region or well area clamping, then the high electric field from gate electrode can directly act on as the EEPROM of flash memory representative.Therefore, for EEPROM, the insulator film thickness of isolating floating gate and channel region or well area is restricted, and has hindered the optimization of memory element function.
From as seen above-mentioned, by making T1＜T2, can not reduce the withstand voltage properties of memory element, reduce the voltage of write activity and cancellation action, perhaps make write activity and cancellation action high-speed, further increase the storage effect.The thickness T 1 of above-mentioned dielectric film, the uniformity in making processing and membranously can keep certain level, and, as the retention performance extreme limit of deterioration not, preferably 0.8nm or more than.
Specifically, for example when high high withstand voltage of design rule is necessary liquid crystal driver LSI, in order to drive liquid crystal panel TFT (thin-film transistor), voltage that must maximum 15～18V.Therefore, can not make grid oxidation film 214 filmings usually.Among the liquid crystal driver LSI, when the conduct image was adjusted the nonvolatile memory of using mixed year this reference example, the memory element of this reference example can be independent of gate insulation film thicknesses, and thickness T 1 is carried out optimal design.For example, be the memory cell of 250nm for gate electrode long (word line is wide), can set T1=20nm respectively, T2=10nm, realization writes the memory cell of excellent in efficiency.
Even the thickness T of above-mentioned dielectric film 1 short-channel effect can not take place than common logic transistor is thick yet, its reason is because source drain zone (the 1st, the 2nd diffusion zone 212,213) is offset with respect to gate electrode 217.
The 8th reference example
The memory element of the semiconductor storage of the present invention's the 8th reference example, as shown in figure 18, except isolating dielectric film as the channel region of the silicon nitride film 242 of charge holding film and P type semiconductor substrate 211 or well area (in the silicon oxide layer 241, the part that is connected with Semiconductor substrate 211) thickness T 1 than the thickness T 2 of gate insulating film 2214 thicker outside, have essence and the same formation of above-mentioned the 2nd reference example.
According to the requirement that prevents above-mentioned memory element short-channel effect, there is higher limit in the thickness T 2 of gate insulating film 214.Yet the thickness T 1 of above-mentioned dielectric film does not consider to prevent the requirement of short-channel effect, can be thicker than the thickness T 2 of gate insulating film 214.Just, when becoming more meticulous calibration (scaling) progress (when the filming of gate insulating film 214 is carried out), owing to can be independent of the gate insulator thickness insulator film thickness T1 that isolates silicon nitride film 242 and channel region or well area is carried out optimal design, then the 1st, the 2nd memory function body 261,262 has the effect of not calibrating obstacle.
In above-mentioned memory element, higher to the design freedom of thickness T 1 as described above reason.As previously mentioned, promptly isolate the channel region of silicon nitride film 242 and P type semiconductor substrate 211 or the dielectric film of well area, not by gate electrode 217 and channel region or well area clamping.Its result, the requirement that can prevent regardless of short-channel effect with respect to gate insulating film 214, it is thicker than thickness T 2 to set thickness T 1.
By making thickness T 1 thicker, then can prevent the charge dissipation of the 1st, the 2nd memory function body 261,262 accumulation, improve the retention performance of memory.
Therefore, by setting T1〉T2, then can improve the retention performance that the short-channel effect that do not make memory element worsens.
The thickness T 1 of above-mentioned dielectric film is considered the reduction of overwrite speed, preferably 20nm or following.
As the existing nonvolatile memory of flash memory representative, select gate electrode to constitute and write the cancellation gate electrode, write gate insulating film (interior bag floating gate) the dual-purpose electric charge accumulation film of cancellation gate electrode corresponding to this.Therefore, owing to become more meticulous (in order to suppress short-channel effect, must filming) requirement with guarantee that reliability is (in order to suppress to keep sewing of electric charge, isolate the insulator film thickness of floating gate and channel region or well area can not filming to 7nm or following) requirement be opposite, be difficult to become more meticulous.In fact, according to ITRS (International Technology Roadmap for Semiconductors), that the physics grid is not long meticulous turning to below 0.2 micron as target.
To this, the memory element of this reference example as mentioned above, by distinguishing design thickness T1 and thickness T 2, is then compared with nonvolatile memory, can become more meticulous.
For example, for the memory cell of long (word line the is wide) 45nm of gate electrode, set T2=4nm respectively, T1=7nm can realize not taking place the memory element of short-channel effect.Even it is thicker than common logic transistor to set T2, the also impossible reason of short-channel effect is: with respect to gate electrode 217, regions and source (the 1st, the 2nd diffusion zone 212,213) is offset.
The memory element of this reference example is because with respect to gate electrode 217, regions and source is offset, then with common logic transistor comparison, easier becoming more meticulous.
Just, since do not exist on the top of the 1st, the 2nd memory function body 261,262 auxiliaryly write, the electrode of cancellation, then on the dielectric film of channel region of isolating silicon nitride film 242 and P type semiconductor substrate 211 or well area, can directly not act at the high electric field that auxiliary writes, work between the electrode of cancellation and channel region or the well area, only be from gate electrode 217 working than weak electric field in the transverse direction expansion.Therefore, for identical machining accuracy, can realize possessing the memory element of growing with the grid that becomes more meticulous more than the degree with the grid appearance of logic transistor.
The 9th reference example
The 9th reference example of the present invention, the electrical property change when relating to the memory element rewriting of carrying out semiconductor storage.
Figure 19 represents that drain current Id is to the characteristic (measured value) of grid voltage Vg when the quantity of electric charge in the memory function body of N channel-type memory element changes.Among Figure 19, solid line is represented the relation of the drain current Id and the grid voltage Vg of erased condition, and dotted line is represented the relation of the drain current Id and the grid voltage Vg of write state.
From Figure 19 as seen, when the erased condition shown in the solid line was carried out write activity, not only threshold value simply rose, and particularly significantly reduces in sub-threshold region figure gradient.Therefore, though at grid voltage Vg than higher zone, it is big that the drain current of erased condition and write state becomes.For example, even at Vg=2.5V, current ratio keeps more than 2.The situation of this characteristic and flash memory shown in Figure 32 differs widely.
The appearance of this characteristic is because the skew of gate electrode and diffusion zone, and the grid electric field is difficult to reach offset area and the endemism that causes.Memory element is when write state, even apply positive voltage at gate electrode, the offset area under the memory function body, inversion layer are also extremely difficult to be formed.The little reason of Id-Vg slope of curve of sub-threshold region that Here it is under write state.
In addition, memory element is responded to highdensity electronics at offset area when erased condition.When gate electrode applies OV (when just blocking state), the raceway groove under gate electrode can not responded to electronics (so cut-off current is little).It is big that the Id-Vg slope of curve of sub-threshold region that Here it is under erased condition becomes, and the regional current increasing rate (electricity is led) more than threshold value also becomes big reason.
From as seen above-mentioned, the memory element of above-mentioned the 1st reference example～the 9th reference example, the drain current in the time of can making when writing with cancellation is bigger than especially.
The 1st execution mode
Figure 20 represents the broad cross-section map of the memory element of the present invention's the 1st execution mode.Among Figure 20, the component part identical with the component part of the 2nd reference example shown in Figure 8, attached and identical with the component part of Fig. 8 cross reference number omits explanation, perhaps simple declaration.
The memory element of the present invention's the 1st execution mode as shown in figure 20, has: Semiconductor substrate 211; The gate insulating film 214 that on Semiconductor substrate 211, forms; On gate insulating film 214, form single gate electrode 217; The 1st memory function body 261 that forms in a side of gate electrode 217; The 2nd memory function body 262 that forms in another side of gate electrode 217; The P type channel region 472 that forms at the surface element of gate electrode 217 sides of Semiconductor substrate 211; N type the 1st diffusion zone 212 that forms in a side of channel region 472; N type the 2nd diffusion zone 213 that forms in another side of channel region 472.
Above-mentioned the 1st, the 2nd memory function body 261,262 has respectively: the silicon nitride film 242 that possesses the energy level of catching electric charge; Clamping silicon nitride film 242 and silicon oxide layer 241,243 with ability of the charge dissipation that prevents the charge holding film accumulation.Just, above-mentioned the 1st, the 2nd memory function body 261,262 all has the function that keeps electric charge.
Above-mentioned channel region 472 is by the offset area 401 that is positioned under the 1st, the 2nd memory function body 261,262, and the gate electrode lower area 402 that is positioned under the gate electrode 217 constitutes.Offset area 401 is formed at gate electrode lower area 402 both sides.In more detail, offset area 401 is formed at the channel region 472 of the near interface of channel region 472 and the 1st, the 2nd memory function body 261,262.On the other hand, gate electrode lower area 402 is formed at the channel region 472 of the near interface of channel region 472 and gate insulating film 214.Give the impurity concentration of offset area 401P type conductivity type, compare, effectively weaken with the impurity concentration of giving gate electrode lower area 402P type conductivity type.
In the present embodiment, Semiconductor substrate 211 is examples of semiconductor layer, and offset area 401 is examples in the 1st zone, and gate electrode lower area 402 is examples in the 2nd zone.
Like this, the difference of the memory element of the memory element of present embodiment and Fig. 8 the 2nd reference example is to have channel region 472.In more detail, the difference of the memory element of the memory element of present embodiment and Fig. 8 the 2nd reference example is: form offset area 401 261,262 times at the 1st, the 2nd memory function body; Form gate electrode lower area 402 217 times at gate electrode; Give the impurity concentration of offset area 401P type conductivity type, compare, effectively weaken with the impurity concentration of giving gate electrode lower area 402P type conductivity type.In other words, the memory element of present embodiment replaces with channel region 472 with channel region 272 in above-mentioned the 2nd reference example.
When Figure 21 represents that the memory element of above-mentioned the 2nd reference example carries out write activity and cancellation action repeatedly, the drain current after the cancellation action and the relation of number of rewrites.
The memory element of above-mentioned the 2nd reference example is carrying out 10 5After the inferior a series of rewrite action that are made of write activity and cancellation action, the drain current after the cancellation action is about and carries out 1/10 before the rewrite action.Like this, when the drain current after the cancellation action reduced, memory window (memroy window, drain current after the cancellation action and the drain current behind the write activity poor) had also reduced.Therefore, along with the increase of number of rewrites, memory window reduces, and causes reading speed to reduce.Perhaps, the fixed reading speed in order to keep will limit number of rewrites.
The minimizing of the drain current that causes repeatedly of rewrite action shown in Figure 21, think because residual electronics etc. in the charge trap that takes place in the interface energy level that the interface of silicon oxide layer and Semiconductor substrate takes place, silicon oxide layer, silicon nitride film has caused the deterioration of sub-threshold value coefficient and the reduction of transconductance mutually.
When Figure 22 represents that the memory element of present embodiment carries out write activity and cancellation action repeatedly, the drain current after the cancellation action and the relation of number of rewrites.
The memory element of present embodiment carries out 10 5After the inferior a series of rewrite action that are made of write activity and cancellation action, the drain current after the cancellation action is about and carries out 75% before the rewrite action.Just, the memory element of present embodiment, the slip of the drain current after the cancellation action has improved about 25% significantly.
The memory element of present embodiment carries out the drain current value after the preceding cancellation of rewrite action is moved repeatedly, compares with the memory element of above-mentioned the 2nd reference example, increases considerably.Specifically, the memory element of above-mentioned the 2nd reference example, the drain current that carries out repeatedly after the preceding cancellation of rewrite action is moved is 48 μ A, to this, the memory element of present embodiment, the drain current that carries out repeatedly after the preceding cancellation of rewrite action is moved is 123 μ A.
From above result as seen, owing to be provided with channel region 472, suppressed to rewrite the minimizing of the memory window that causes, so reading speed improves, number of rewrites increases.
Owing to adopt structure shown in Figure 20, not only can suppress the deterioration that rewrite action causes repeatedly, the characteristic deviation that the side-play amount deviation that can also suppress to cause because of manufacturing process causes.Here, the side-play amount deviation that above-mentioned manufacturing process causes is because the deviation of gate electrode sidewall thickness, and the deviation of the diffusion of impurities that causes of the deviation of annealing conditions.And, above-mentioned characteristic deviation, the deviation of drain current (read current) when still reading action.Therefore, even when having the side-play amount deviation that above-mentioned manufacturing process deviation causes, also can the suppression characteristic deviation.Thereby, can improve the rate of finished products of semiconductor storage.
The so-called setting compared the thin offset area of impurity concentration 401 with gate electrode lower area 402, and the impurity concentration of the part under the impurity concentration that means the part under the memory function body that makes channel region and the gate electrode of channel region is compared, and is comparatively thin.In order to suppress the memory element deterioration that rewrite action causes repeatedly, and keep other characteristics of memory element good, importantly be not the thin zone of impurity concentration to be set at whole channel region, and roughly only the part under the memory function body of storage area the thin zone of impurity concentration is set.Just, the part that is preferably under the gate electrode of channel region has kept the thinless zone of impurity concentration.When thin regional of impurity concentration is set at whole channel region,, then turn-offs and leak (off-leakage) and increase because the threshold value of the memory element after the cancellation action is low excessively.When turn-off to leak increasing, when making the integrated realization memory cell array of memory element, the memory element quantity that is connected with bit line is restricted.And, because short-channel effect deterioration, the then difficulty that becomes more meticulous of memory element.Therefore, be the factor that has hindered the densification of semiconductor storage.So the thin zone of impurity concentration preferably only roughly is arranged on the part under the memory function body.
In the present embodiment, adopt the channel region 472 that constitutes by offset area 401 and gate electrode lower area 402, but also can adopt the channel region that increases gradually from the regional impurity concentration of zone under gate insulating film of diffusion zone side.Just, also can adopt the channel region that effectively thickens from the concentration of the regional p type impurity of PN junction under gate insulating film of channel region and diffusion zone.Even when adopting such channel region, also can obtain the effect same with the memory element of present embodiment.
Below, the situation for the channel region that increases gradually from the regional impurity concentration of zone under gate insulating film of diffusion zone side is set in the memory element of Figure 20 is illustrated.
Figure 23 is illustrated in the example of analog result of valid density profile diagram of the A-A line of Figure 20.Here, the so-called valid density impurity concentration of giving N type conductivity type in setting is N D, the impurity concentration of giving the P-type conduction type is N AThe time, be meant | N D-N A|.Among Figure 23, the position is corresponding to the position in the 1st diffusion zone 212 in the scope that arrow S represents.Among Figure 23, the position is corresponding to the position in the offset area in the scope that arrow O represents, the position is corresponding to the position in the gate electrode lower area in the scope that arrow G is represented.Just, among Figure 23, the zone that arrow O and arrow G are represented is corresponding to channel region.And among Figure 23, the longitudinal axis is represented effective impurity concentration, and the zone that arrow S represents is the N type, and the zone that arrow O and arrow G are represented is the P type.
As can be seen from Figure 23, give the impurity concentration N of channel region P-type conduction type A, thicken gradually from the zone of PN junction under gate insulating film 214 of channel region and the 1st diffusion zone 212.Do not give diagram, even but, give the impurity concentration N of channel region P-type conduction type from the zone of PN junction under gate insulating film 214 of channel region and the 2nd diffusion zone 213 AThicken gradually.
Figure 24 is illustrated in the example of analog result of valid density profile diagram of the B-B line of Figure 20.
As can be seen from Figure 24, give the impurity valid density of channel region P-type conduction type, thicken gradually with its degree of depth.Just, the part under the 2nd memory function body 262 of above-mentioned channel region, the most surperficial impurity concentration N of the 2nd memory function body 262 sides AEffectively become the thinnest.Do not give diagram, even but the part under the 1st memory function body 261 of above-mentioned channel region, the most surperficial impurity concentration N of the 1st memory function body 261 sides AEffectively become the thinnest.
The channel region impurities concentration distribution of memory element shown in Figure 20, when the current potential of the current potential and the 1st of gate electrode 217, the 2nd diffusion zone 212,213 equates, just when blocking state, preferably set the exhausting of part (offset area 401) under the 1st, the 2nd memory function body 261,262 of channel region 472 for.At this moment, the depletion layer that PN junction in Semiconductor substrate 211 and the 1st, the 2nd diffusion layer territory 212,213 forms, and, be connected by offset area 401 (zones of Semiconductor substrate 211 and the 1st, the 2nd memory function body 261,262 near interfaces) at the depletion layer that gate electrode forms for 217 times.The Impurity Distribution of this state is given the impurity concentration N of p type impurity concentration AWith the impurity concentration N that gives N type conductivity type DNear offset area 401, about equally the time (near offset area 401, effectively impurity concentration is compared thin with gate electrode lower area 402), can realize.Under such condition, the effect that the reading speed that can fully be improved, the number of rewrites that increases, rate of finished products improve.
The memory element setting of Figure 20 from the zone of diffusion zone side under the situation of the channel region that gate insulating film lower area impurity concentration increases gradually, when the impurities concentration distribution of channel region equates the current potential of current potential and the 1st, the 2nd diffusion zone 212,213 of gate electrode 217, preferably set the exhausting of at least a portion of the part (offset area 401) under the 1st, the 2nd memory function body of channel region for.
In the above-mentioned execution mode, can make the impurity concentration of the each several part P-type conduction type of giving offset area 401 roughly the same.And, also can make the impurity concentration of the each several part P-type conduction type of giving gate electrode lower area 402 roughly the same.
The 2nd execution mode
Figure 25 represents the memory element broad cross-section map of the present invention's the 2nd execution mode.Among Figure 25, the formation portion identical with the formation portion of the 1st execution mode shown in Figure 20, attached and identical with the formation portion of Figure 20 cross reference number omits explanation.
Not not being both of the memory element of the memory element of present embodiment and Figure 20 the 1st execution mode: p type island region territory 403 is set under offset area 401.Give the impurity concentration of regional 403P type conductivity type, compare, effectively thicken with the impurity concentration of giving gate electrode lower area 402P type conductivity type.In addition, zone 403 is connected in the bottom of offset area 401.This zone 403 is examples in the 3rd zone.
Figure 26 is illustrated in the example of valid density profile diagram analog result of the C-C line of Figure 25.
As can be seen from Figure 26, be positioned at the part of the 2nd diffusion zone 213 sides for 262 times at the 2nd memory function body, the most surperficial effective impurity concentration of the 2nd memory function body 262 sides of Semiconductor substrate 211 is the thinnest.And, in above-mentioned part, give the impurity valid density of P-type conduction type, increase gradually with the degree of depth, after becoming maximum near the degree of depth 0.05 μ m, slowly reduce.Near the degree of depth 0.05 μ m, the zone 403 under the 2nd memory function body 262 is set.Do not give diagram, but be positioned at the part of the 1st diffusion zone 212 sides for 261 times at the 1st memory function body, effectively impurity concentration shows and the same variation of Figure 26.Zone 403 under the 1st memory function body 261 also is arranged near the most surperficial degree of depth 0.05 μ m of the 2nd memory function body 262 sides of Semiconductor substrate 211.
By 261,262 times this zone 403 being set at the 1st, the 2nd memory function body, then relatively the current potential gradient of the PN junction of shallow portion is very steep in Semiconductor substrate 211, the luminous efficiency of hot carrier in the time of can improving rewrite action.Therefore, can make the inhibition and the high speed rewrite action of the deterioration that rewrite action causes repeatedly and depositing.
From the depth direction profile of Semiconductor substrate 211, the degree of depth corresponding with the peak value of effective impurity concentration is preferably apart from the interface 10nm～80nm (0.01 μ m～0.08 μ m) of Semiconductor substrate 211 with silicon oxide layer 241.
If during the degree of depth corresponding with effective impurity concentration peak value deficiency 10nm, then (the most surperficial) is difficult to make effective impurity concentration enough thin near raceway groove, can not fully suppress the deterioration that rewrite action causes repeatedly.
When if the degree of depth corresponding with effective impurity concentration peak value surpasses 80nm, near the hot carrier that the degree of depth corresponding, takes place then with effective impurity concentration peak value, at random before arriving silicon nitride film 242, the following general who has surrendered of overwrite speed is very important.
Therefore, the degree of depth corresponding with effective impurity concentration peak value is set in 10nm～80nm scope, can makes the inhibition of the deterioration that rewrite action causes repeatedly and high speed rewrite action fully and deposit.
Below, utilize Figure 27 A, B, the formation method of present embodiment memory element is described.Diagrammatic illustration the major part formation method of above-mentioned memory element, below main explanation form the program in offset area 401 and zone 403.
At first, utilize known method, shown in Figure 27 A, on P type semiconductor substrate 3211, form gate insulating film 214 and gate electrode 217.
Then,, inject the impurity 411 of giving N type conductivity type, and inject the impurity 412 of giving the P-type conduction type on the full surface of gate electrode 217 sides of Semiconductor substrate 3211.At this moment, give the impurity 411 of N type conductivity type, compare, inject more shallow with the impurity 412 of giving the P-type conduction type.
Give the impurity of N type conductivity type, for example be 75As + 75As +Can be that 1KeV～40KeV, injection rate are 5 * 10 by injecting energy 12～1 * 10 14Cm -2Condition, be injected in the Semiconductor substrate 3211.
Give the impurity of P-type conduction type, for example be 11B + 11B +Can be that 500eV～20KeV, injection rate are 5 * 10 by injecting energy 12～1 * 10 14Cm -2Condition, be injected in the Semiconductor substrate 3211.
Preferably will be as impurity one example of giving N type conductivity type 122Sb +(antimony) is injected in the Semiconductor substrate 3211.Because the quality of antimony is big, then diffusion length is little, is suitable for reducing effective impurity concentration of near surface of gate electrode 217 sides of Semiconductor substrate 3211.
And, pass through to adopt as an example of the impurity of giving N type conductivity type 122Sb +, then effectively the peak value of impurity concentration can produce in more shallow part.Its result, the deterioration and the high speed rewrite action both that cause repeatedly for the inhibition rewrite action can obtain special effect.Impurity in Semiconductor substrate 3211 injects, and gate electrode 217 only when gate electrode 217 does not exist, carries out injecting from coupling as mask.
Above-mentioned impurity injects, and can carry out before in formation gate electrode sidewall (the 1st, the 2nd memory function body 261,262) after forming gate electrode 217.Among Figure 27 A, after the full surface of gate electrode 217 sides of Semiconductor substrate 3211 forms silicon oxide layer 3241 and silicon nitride film 3242, carry out above-mentioned injection.
After forming gate electrode 217, inject if under the state that does not form silicon oxide layer 3241, carry out impurity, disperse owing to suppressed the depth direction of impurity, then help the inhibition and the high speed rewrite action of the deterioration that rewrite action causes repeatedly.
Shown in Figure 27 A, inject if after silicon nitride film 3242 forms, carry out impurity, owing to can prevent the pollution of silicon oxide layer 243 (with reference to Figure 25 or Figure 27 B), can suppress the dissipation of the electric charge of silicon nitride film 242 accumulation, improve the retention performance of memory element.
Then, shown in Figure 27 B, form gate electrode sidewall (the 1st, the 2nd memory function body 261,262) and the 1st, the 2nd diffusion zone 212,213.If through these PROCESS FOR TREATMENT, the impurity 412 of giving the impurity 411 of N type conductivity type and giving the P-type conduction type spreads and activates, forms offset area 401 and regional 403.
Give the impurity 411 of N type conductivity type, offset, effective impurity concentration is descended with giving the impurity that is present in the P-type conduction type in the Semiconductor substrate 3211 originally.
In the above-mentioned formation method,, can form the memory element of the 1st execution mode of Figure 20 when the impurity 411 that only will give N type conductivity type is injected into complete when surface of gate electrode 217 sides of Semiconductor substrate 3211.
The 3rd execution mode
Figure 28 represents the broad cross-section map of the memory element of the present invention's the 3rd execution mode.Among Figure 28, the formation portion identical with the formation portion of the 1st execution mode shown in Figure 20, attached with the identical cross reference number of formation portion of Figure 20, omit explanation.
The difference of the memory element of the 1st execution mode of the memory element of present embodiment and Figure 20: under offset area 401 and gate electrode lower area 402, p type island region territory 404 is set.Give the impurity concentration of regional 404P type conductivity type, compare, effectively thicken with the impurity concentration of giving gate electrode lower area 402P type conductivity type.Zone 404 is connected in the bottom of offset area 401 and gate electrode lower area 402.Part under the 1st, the 2nd memory function body 261,262 in this zone 404 is an example in the 3rd zone.
The device configuration of the memory element of present embodiment, the same with above-mentioned the 2nd execution mode, can realize simultaneously because the inhibition of the deterioration that causes repeatedly of rewrite action, and the high speed rewrite action.
And, owing to, suppressed short-channel effect effectively, so realize becoming more meticulous of memory element easily in offset area 401 and gate electrode lower area 402 setting areas 404.
The 4th execution mode
Figure 29 represents the broad cross-section map of the memory element of the present invention's the 4th execution mode.Among Figure 29, the formation portion identical with the formation portion of the 2nd execution mode shown in Figure 25, attached with the identical cross reference number of formation portion of Figure 25, omit explanation.
The difference of the memory element of the 2nd execution mode of the memory element of present embodiment and Figure 25: under the 1st, the 2nd diffusion zone 212,213, p type island region territory 405 is set.Give the impurity concentration of regional 405P type conductivity type, compare, effectively weaken with the impurity concentration of giving gate electrode lower area 402P type conductivity type.Zone 405 is connected in the bottom of the 1st, the 2nd diffusion zone 212,213.This zone 405 is examples in the 4th zone.
The memory element of present embodiment by adopting above-mentioned such device configuration, can reduce the junction capacitance relevant with the 1st, the 2nd diffusion zone 212,213, significantly so can read action at a high speed.Therefore, can realize the inhibition of the deterioration that rewrite action causes repeatedly, and high-speed rewrite action and read action.
The 5th execution mode
Figure 30 represents the broad cross-section map of the memory element of the present invention's the 5th execution mode.Among Figure 30, the formation portion identical with the formation portion of the 1st execution mode shown in Figure 20, attached with the identical cross reference number of formation portion of Figure 20, omit explanation.
The difference of the memory element of the 1st execution mode of the memory element of present embodiment and Figure 20 is: gate insulating film comprises high dielectric film (than the big dielectric film of silicon oxide layer conductivity).Therefore, the memory element of present embodiment is compared with the memory element of the 1st execution mode, and easier realization becomes more meticulous.Its reason below is described.
Semiconductor storage of the present invention, memory function body and gate insulating film independently form.Therefore, can make above-mentioned gate insulator filming, suppress short-channel effect,, become more meticulous easily so compare with the conventional semiconductor storage device.Yet, the voltage when living rewrite action owing to above-mentioned gate insulating film is necessary anti-, so there is lower limit in the thickness of gate insulating film.The lower limit of this gate insulating film thickness is stipulated the limit that becomes more meticulous of semiconductor storage of the present invention.
So, the memory element of present embodiment, gate insulating film 483 comprises high dielectric film 482.Therefore, can as the physics thickness is still thicker, make equivalent thickness of oxidation film (the silicon oxidation thickness when using silicon oxide layer the to realize same static capacity) attenuation of gate insulating film 483.
Therefore, make the withstand voltage equivalent thickness of oxidation film attenuation that still keeps above-mentioned gate insulating film 483, can suppress short-channel effect.Its result can make the semiconductor storage of the present invention that becomes more meticulous easily than conventional semiconductor storage device, further becomes more meticulous.
The memory element of present embodiment, by making gate insulating film 483 contain high dielectric film 482, the equivalent oxide thickness attenuation of gate insulating film 483 (just, the direct capacitance quantitative change of gate insulating film 483 is big), can make inversion layer charge density become big, so with the memory element of the 1st execution mode of Figure 20 relatively, can increase the drain current (read current) after the cancellation action significantly.Therefore, can improve present embodiment memory element read responsiveness.
Above-mentioned gate insulating film 483 can be made of the individual layer high dielectric film, but preferably is made of the stack membrane of interfacial migration layer (low dielectric plasma membrane) 481 and high dielectric film 482.This high dielectric film 482 can form with for example hafnium compound.Above-mentioned interfacial migration layer (low dielectric plasma membrane) 481 can adopt for example silicon oxide layer and silicon nitride film.
During as the material selection hafnium compound of above-mentioned gate insulating film 483,, memory element also can keep higher conductivity even becoming more meticulous.This point, hafnium compound is better than other materials.
As mentioned above, contain hafnium compound,, particularly can obtain higher drain current for meticulous memory element even then memory element becomes more meticulous and also can keep higher conductivity by making above-mentioned gate insulating film 483.This character is desirable especially for memory element.Its reason below is described.
Memory element, because the cancellation action has reduced the threshold value (channel resistance of offset area 401 parts descends) of offset area 401 parts, drain current increases.By increasing the time of above-mentioned cancellation action, can make the channel resistance of offset area 401 parts littler, but can not unrestrictedly strengthen drain current.Its reason is: along with the channel resistance of above-mentioned offset area 401 parts diminishes, the channel resistance of gate electrode lower area 402 parts is main resistance, has limited drain current.Just, in order to strengthen drain current, must reduce the channel resistance of gate electrode lower area 402 parts.Use hafnium compound can realize the attenuating of the channel resistance of these gate electrode lower area 402 parts.Just, when adopting hafnium compound,,, also can reduce the channel resistance of gate electrode lower area 402 parts because the inversion layer charge density of gate electrode lower area 402 becomes big even memory element becomes more meticulous as the material of above-mentioned gate insulating film 483.Therefore,, under memory element becomes more meticulous situation, also can increase read current, make and read the action high speed by with the material of hafnium compound as above-mentioned gate insulating film 483.
And, because above-mentioned hafnium compound thermal stability height is then higher with the compatibility of the technology that adopts polysilicon gate.Therefore, by using the material of hafnium compound as above-mentioned high dielectric film 482, manufacturing process is easier.
So-called above-mentioned hafnium compound can be: hafnium oxide (HfO 2), hafnium silicate (HfSiO, HfSiON), hafnium aluminum oxide (HfAlO).The ratio of each element can carry out optimization according to the characteristic that can obtain wishing.For example, when adopting hafnium oxide, can make the conductivity of gate insulating film 483 higher (conductivity that can make gate insulating film for example is 20), can enlarge the effect that read current increases as the material of gate insulating film 483.When adopting hafnium silicate as the material of gate insulating film 483, the reaction of the silicon atom of easier inhibition and Semiconductor substrate 211 can suppress leakage current.When adopting the hafnium aluminum oxide, because thermal stability is higher, then manufacturing process is more or less freely.
When above-mentioned gate insulating film 483 is made of the stack membrane of interfacial migration layer (low dielectric plasma membrane) 481 and high dielectric film 482, when the equivalent thickness of oxidation film that makes gate insulating film is thin, can remain on the interface of gate insulating film 483 and Semiconductor substrate 211 high-grade.Just, compare, improved the movement of electric charges degree, can suppress the deterioration at interface with the direct-connected situation of high dielectric and Semiconductor substrate.Therefore, can improve the responsiveness of reading of memory element, improve reliability.
Form above-mentioned high dielectric film 482 with hafnium oxide, interfacial migration layer 481 during as silicon oxide layer, for example, can be set high dielectric film 482 and is 10nm, interfacial migration layer 481 is 1nm, but thickness is not limited thereto.
In above-mentioned the 4th execution mode, interfacial migration layer 481 is examples of the 1st dielectric film, and high dielectric film 482 is examples of the 2nd dielectric film.
The 6th execution mode
Figure 31 represents the general block diagram as an example portable phone of portable electric appts device of the present invention.
Above-mentioned portable phone mainly has: control circuit 511, battery 512, RF (wireless frequency) circuit 513, display part 514, antenna 515, holding wire 516 and power line 517.In the control circuit 511, assembled the semiconductor storage of any memory element that contains above-mentioned the 1st～the 5th execution mode.Control circuit 511 preferably is also used as isomorphic element the integrated circuit of memory circuit element and logic circuit component.Like this, the manufacturing of integrated circuit is easier to, and can reduce the manufacturing cost of portable electronic machine especially.
Like this, by in portable electric appts, adopted storage part and logical circuit portion mix to carry technology simple and easy, become more meticulous easily and the semiconductor storage that can read at a high speed, the reliability and the responsiveness of portable electric appts have been improved, simultaneously can miniaturization, and can cut down manufacturing cost.
In above-mentioned the 1st～the 6th execution mode, used P type semiconductor substrate 211, but also can use the N type semiconductor substrate.When using the N type semiconductor substrate to form N channel-type memory element, can form P type well area at the surface element of the gate electrode side of N type semiconductor substrate, form channel region at this P type well area.
In above-mentioned the 1st～the 6th execution mode, N channel-type memory element has been described, but the present invention is not limited to N channel-type memory element.Just, memory element of the present invention also can be the P channel-type.For example, each the formation portion for the memory element of the 1st～the 6th execution mode can make conductivity type opposite, just, changes the P type into the N type, and, if when the N type changes the P type into, promptly form P channel-type memory element.P channel-type memory can be used for any of N type semiconductor substrate and P type semiconductor substrate at element.When using the P type semiconductor substrate to form P channel-type memory element, can form N type well area, form channel region at this N type well area at the surface element of the gate electrode side of P type semiconductor substrate.
Above-mentioned the 1st～the 9th reference example and above-mentioned the 1st～the 6th execution mode can be made up, as semiconductor storage of the present invention.For example, in the memory element of the 1st～the 9th reference example, offset area 401, gate electrode lower area 402 and zone 403～405 at least 1 is set, as an example of the present invention.And, also can in the 1st～the 6th execution mode, use service condition, design condition and the definition etc. of above-mentioned the 1st～the 9th reference example.
The present invention puts down in writing as above, but apparent the present invention can change with several different methods.The disengaging the spirit and scope of the present invention are not seen in this change as, and tangible to those skilled in the art improvement all is interpreted as and is included in the following claim scope.

Claims (19)

1. a semiconductor storage is characterized in that,
Have:
Semiconductor layer;
The gate insulating film that on above-mentioned semiconductor layer, forms,
The single gate electrode that on above-mentioned gate insulating film, forms,
The memory function body that forms, has the function that keeps electric charge in the both sides of above-mentioned gate electrode;
The 1st conductive type of channel zone that forms in the above-mentioned gate electrode side surface portion of above-mentioned semiconductor layer,
The 2nd conductivity type diffusion zone that forms in the both sides of above-mentioned channel region;
In the 1st conductivity type the 1st zone that the above-mentioned channel region of the near interface of above-mentioned channel region and above-mentioned memory function body forms;
In the 1st conductivity type the 2nd zone that the above-mentioned channel region of the near interface of above-mentioned channel region and above-mentioned gate insulating film forms,
The concentration of giving the impurity of above-mentioned the 1st zone the 1st conductivity type is leaner than the concentration of the impurity of giving above-mentioned the 2nd zone the 1st conductivity type effectively.
2. as the semiconductor storage of claim 1 record, it is characterized in that,
Have under above-mentioned the 1st zone the 3rd zone that forms, is connected with above-mentioned the 1st zone,
The concentration of giving the impurity of above-mentioned the 3rd zone the 1st conductivity type is richer than the impurity concentration of giving above-mentioned the 2nd zone the 1st conductivity type effectively.
3. as the semiconductor storage of claim 2 record, it is characterized in that,
The concentration of impurity of part the 1st conductivity type of giving the degree of depth 10nm～80nm in above-mentioned the 3rd zone is richer than the concentration of the impurity of giving above-mentioned the 3rd other part the 1st conductivity types of zone effectively.
4. as the semiconductor storage of claim 2 record, it is characterized in that,
Have under above-mentioned diffusion zone the 4th zone that forms, is connected with above-mentioned diffusion zone,
The concentration of giving the impurity of above-mentioned the 4th zone the 1st conductivity type is leaner than the concentration of the impurity of giving above-mentioned the 2nd zone the 1st conductivity type effectively.
5. as the semiconductor storage of claim 1 record, it is characterized in that,
Above-mentioned gate insulating film comprises the dielectric film with conductivity bigger than the conductivity of silicon oxide layer.
6. as the semiconductor storage of claim 5 record, it is characterized in that,
Above-mentioned dielectric film is made of hafnium compound.
7. the manufacture method as the semiconductor storage of claim 1 record is characterized in that,
After forming above-mentioned gate electrode, the impurity of giving the 2nd conductivity type is injected into above-mentioned semiconductor layer after, form above-mentioned memory function body.
8. the manufacture method as the semiconductor storage of claim 2 record is characterized in that,
After forming above-mentioned gate electrode, the impurity of giving the 1st conductivity type is injected into above-mentioned semiconductor layer, simultaneously, the impurity of giving the 2nd conductivity type is injected into above-mentioned semiconductor layer after, form above-mentioned memory function body, to be shallower than the impurity of giving above-mentioned the 1st conductivity type.
9. the manufacture method as the semiconductor storage of claim 7 record is characterized in that,
The impurity of giving above-mentioned the 2nd conductivity type is antimony.
10. the manufacture method as the semiconductor storage of claim 8 record is characterized in that,
The impurity of giving above-mentioned the 2nd conductivity type is antimony.
11. a semiconductor storage is characterized in that,
Have:
Semiconductor layer;
The gate insulating film that on above-mentioned semiconductor layer, forms;
The single gate electrode that on above-mentioned gate insulating film, forms;
The memory function body that forms, has the function that keeps electric charge in the both sides of above-mentioned gate electrode;
The 1st conductive type of channel zone that forms in the above-mentioned gate electrode side surface portion of above-mentioned semiconductor layer;
The diffusion zone of the 2nd conductivity type that forms in the both sides of above-mentioned channel region,
Give the impurity concentration of above-mentioned channel region the 1st conductivity type, near the zone under the above-mentioned gate insulating film, thicken effectively from the PN junction of above-mentioned channel region and above-mentioned diffusion zone.
12. the semiconductor storage as claim 11 record is characterized in that,
Above-mentioned gate insulating film comprises the dielectric film with conductivity bigger than the conductivity of silicon oxide layer.
13. a semiconductor storage is characterized in that,
Have:
Semiconductor layer;
The gate insulating film that on above-mentioned semiconductor layer, forms;
The single gate electrode that on above-mentioned gate insulating film, forms;
The memory function body that forms, has the function that keeps electric charge in the both sides of above-mentioned gate electrode;
The 1st conductive type of channel zone that forms in the above-mentioned gate electrode side surface portion of above-mentioned semiconductor layer;
The 2nd conductivity type diffusion zone that forms in the both sides of above-mentioned channel region,
When the current potential that makes above-mentioned gate electrode equates with the current potential of above-mentioned diffusion zone, depletion layer that forms at the PN junction of above-mentioned channel region and above-mentioned diffusion zone and the depletion layer that under above-mentioned gate electrode, forms, be connected at the near interface of above-mentioned channel region with above-mentioned memory function body
The concentration of giving the impurity of above-mentioned the 1st zone the 1st conductivity type is leaner than the concentration of the impurity of giving above-mentioned the 2nd zone the 1st conductivity type effectively.
14. the semiconductor storage as claim 13 record is characterized in that,
Above-mentioned gate insulating film comprises the dielectric film with conductivity bigger than the conductivity of silicon oxide layer.
15. a semiconductor storage is characterized in that,
Have:
Semiconductor layer;
The gate insulating film that on above-mentioned semiconductor layer, forms;
The single gate electrode that on above-mentioned gate insulating film, forms;
The memory function body that forms, has the function that keeps electric charge in the both sides of above-mentioned gate electrode;
The 1st conductive type of channel zone that forms in the above-mentioned gate electrode side surface portion of above-mentioned semiconductor layer;
The 2nd conductivity type diffusion zone that forms in the both sides of above-mentioned channel region,
Above-mentioned gate insulating film comprises the 1st dielectric film, and on above-mentioned the 1st dielectric film, form, the 2nd dielectric film of the conductivity higher than the conductivity of above-mentioned the 1st dielectric film,
The concentration of giving the impurity of above-mentioned the 1st zone the 1st conductivity type is leaner than the concentration of the impurity of giving above-mentioned the 2nd zone the 1st conductivity type effectively.
16. a portable electric appts is characterized in that, has the semiconductor storage of claim 1 record.
17. a portable electric appts is characterized in that, has the semiconductor storage of claim 11 record.
18. a portable electric appts is characterized in that, has the semiconductor storage of claim 13 record.
19. a portable electric appts is characterized in that, has the semiconductor storage of claim 15 record.
CNB2005100878252A 2004-06-03 2005-06-03 Semiconductor storage device, manufacturing method thereof and portable electronic equipment Expired - Fee Related CN100524769C (en)

Applications Claiming Priority (3)

Application Number Priority Date Filing Date Title
JP166359/04 2004-06-03
JP2004166359 2004-06-03
JP323842/04 2004-11-08

Publications (2)

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