CN100451592C - High accuracy number online dynamic balance detecting device based on FPGA - Google Patents
High accuracy number online dynamic balance detecting device based on FPGA Download PDFInfo
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- CN100451592C CN100451592C CNB2007100636426A CN200710063642A CN100451592C CN 100451592 C CN100451592 C CN 100451592C CN B2007100636426 A CNB2007100636426 A CN B2007100636426A CN 200710063642 A CN200710063642 A CN 200710063642A CN 100451592 C CN100451592 C CN 100451592C
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Abstract
The present invention provide an high-precision on-line dynamic balance detecting device based on FPGA and the device can perform an high-precision on-line detecting to the rotor of unbalance. The device generates a reference pulse by the photoelectric sensor when the rotor passes the reference position, and the pulse generates phase locking signals and frequency doubling signals through the FPGA chip. The frequency doubling signals springs the AD chip controlled by the FPGA to perform a sampling. Then, FPGA generates a sampling end signal and DSP responses to said signal, and the sampling value is read through the corresponding address unit. Then the amplitude value and phase of the unbalance is calculated according to a certain control arithmetic after that the sampling data of the whole circle is read. The device performs sampling and processing of signals in four circuits (the upper end X, the upper end Y, the lower end X and the lower end Y), and the unbalance of the rotor in the working rotating speed can be measured and the method has a great data processing ability and a quick response speed, thus, a higher balance precision can be achieved.
Description
Technical field
The present invention relates to a kind of high accuracy number online dynamic balance detecting device, be specially adapted to the online detection of high rotating speed rotor unbalancing value based on FPGA.
Background technology
The rotor quality imbalance is to cause the one of the main reasons of rotating machinery vibration.Because the working speed of magnetic levitation type rotor or some mechanical type rotor is than higher, the size of its unbalancing value directly influences the control accuracy of rotor, and then can influence the size of output disturbance moment.If amount of unbalance is bigger, then can influences its floating and raising speed to magnetic levitation type rotor, even when high rotating speed, cause the generation of unstable phenomenon; Then can increase its wearing and tearing to the mechanical type rotor, reduce serviceable life.
It is the main method of eliminating this nuisance vibration that rotor is carried out the transient equilibrium detection.Existing dynamic balance detecting device mostly is the off-line transient equilibrium and detects, and when higher rotation speed, windage is bigger to the influence of rotor, can't obtain accurate amount of unbalance, so accuracy of detection is not high.Simultaneously, offline inspection needs a whole set of balance detection equipment, and needs the dismounting rotor; Online detection does not then need the dismounting rotor.Therefore on-line dynamic balancing detects and has better dirigibility.
Chinese patent application number " 200610114361.4 "---" a kind of based on the phase-locked high precision magnetic suspension flying wheel on-line dynamic balancing pick-up unit of hardware " disclosed, as shown in Figure 1.In this patented claim, dsp chip 9 ' is by frequency-doubled signal control sampling process, and dsp chip 9 ' just can be handled and computing accordingly after the wait sampling was finished.Under this design, if will improve accuracy of detection, need to improve sample frequency, thereby the time that can cause DSP to wait for that sampling finishes is elongated, in time deal with data and computing can occur, and problem such as program fleet; Simultaneously, be subjected to the restriction of outside frequency dividing circuit, the frequency multiplication multiple mostly is 128 frequencys multiplication most, if will improve sample frequency, needs to change the bigger chip of frequency division ability, and wants corresponding adjustment external circuit.Therefore,, be easy to realize, exist and adjust shortcomings such as dumb, that structural design is restricted though this design is simple.
Summary of the invention
The technical matters that the present invention solves: it is not high to overcome existing off-line transient equilibrium accuracy of detection, existing on-line dynamic balancing detects the shortcoming that sample frequency is restricted, can't guarantee real-time, and a kind of high accuracy number online dynamic balance detecting device based on FPGA is provided.
Technical solution of the present invention: based on the high accuracy number online dynamic balance detecting device of FPGA, it is characterized in that: the sensor signal interface circuit: link to each other with the AD chip, be used for the signal of displacement or vibration transducer is amplified and bandpass filtering treatment, and deliver to the AD chip, wait for sampling; Fpga chip is realized numeral phase-locked and double frequency function and AD controlling of sampling function by programming: the reference pulse signal by pulse processing circuit shaping and amplitude limit is carried out phase-locked and frequency multiplication, and control AD chip is sampled.Sampling is deposited corresponding address location with sampled result after finishing, and generates a sampling simultaneously and finishes the external interrupt signal of pulse signal as DSP, and notice DSP extracts sampled result; Dsp chip: phase-locked pulse signal and sampling are finished pulse signal generation interruption, from the corresponding address location of FPGA, extract sampled value, carry out discrete Fourier transform (DFT) (DFT) after extracting the sampled value of a complete cycle, the go forward side by side algorithm calculation process of line correlation obtains the size and the phase place of amount of unbalance; Level transferring chip: join with fpga chip and AD chip, be used for transforming mutually between the 5V of the 3.3V of fpga chip and AD chip.
Principle of the present invention: the sensor signal interface circuit links to each other with the AD chip, is used for the signal of displacement (vibration) sensor is amplified and bandpass filtering treatment, and delivers to the AD conversion chip, waits for sampling.Optoelectronic switch produces a pulse signal when rotor turns over the reference position, this pulse signal generates a phase-locked pulse signal and a double frequency pulse signal through fpga chip.Phase-locked pulse signal triggers the external interrupt of DSP; The double frequency pulse signal starts the sampling of AD chip as enabling signal, generates one by fpga chip after the AD sampling finishes and finishes the external interrupt that pulse signal triggers DSP, and DSP extracts corresponding displacement in this external interrupt.DSP is correspondingly processed after getting the sampled value of complete cycle, thereby extract and the component of rotating speed with frequency, and carry out respective algorithms computing (adopting single face influence coefficient method or two-sided influence coefficient methods according to the rotor type difference in the present embodiment), draw the size and the phase place of corresponding amount of unbalance by these periodic sampling data.
The present invention compares with existing dynamic balance detecting device and has the following advantages:
(1) the present invention adopts on-line dynamic balancing to detect, than the off-line transient equilibrium detect have debugging flexibly, convenient, volume is little, do not need to add characteristics such as driving arrangement.It is the real work rotating speed that on-line dynamic balancing detects rotating speed, can truly reflect the amount of unbalance under the measured rotating speed.
(2) the present invention has adopted the AD chip controlling of sampling that fpga chip is realized, can save the working time of DSP, improves sample frequency largely, reaches sampling precision height, characteristics that the computing real-time is good, and then can improve the precision of balance detection.
(3) the present invention has adopted the digital phase-locked and double frequency function that fpga chip is realized, has flexible, the phase-locked precision height of control, is easy to integrated characteristics.
Description of drawings
Fig. 1 is the structure composition frame chart of Chinese patent application number " 200610114361.4 ";
Fig. 2 is a theory diagram of the present invention;
Fig. 3 is the phase-locked and frequency multiplication control principle figure of FPGA numeral of the present invention;
Fig. 4 is electrical level conversion chip of the present invention and FPGA and AD chip interface circuit figure;
Fig. 5 is FPGA control AD sampling principle figure of the present invention;
Fig. 6 is the sensor interface circuitry figure of single passage of the present invention;
Fig. 7 is pulse processing circuit figure of the present invention;
Fig. 8 is a DSP control flow chart of the present invention.
Embodiment
As shown in Figure 2, hardware of the present invention mainly is made up of optoelectronic switch 1, pulse processing circuit 2, fpga chip 3, dsp chip 4, electrical level conversion chip 5, AD chip 6, sensor signal interface circuit 7 and displacement or vibration transducer 8, wherein fpga chip 3 is realized numeral phase-locked and double frequency function and AD controlling of sampling function by programming, and dsp chip 4 adopts arithmetic speed can reach the TMS320VC33 of 150MFLOPS.Optoelectronic switch 1 produces a reference pulse signal when rotor turns over the reference position, send into fpga chip 3 behind this pulse signal process pulse processing circuit shaping and the amplitude limit.Fpga chip 3 produces a phase locking frequency multiplying pulse signal and a double frequency pulse signal by phase-locked with double frequency function.With the external interrupt INT0 of the triggering of the pulse signal after phase-locked DSP, in INT0, allow the INT1 of DSP to interrupt; With the startup sampled signal of the pulse signal after this frequency multiplication as AD chip 6, AD samples by FPGA control, sampling finishes the external interrupt INT1 of the sampling end trigger action DSP of back FPGA generation, and DSP reads sampled value from fpga chip 3 corresponding addresses in INT1.Rotor displacement that the displacement of rotor or vibration transducer 8 collect or vibration signal are delivered to AD chip 6 behind the sensor signal interface circuit, wait for sampling.After DSP makes discrete Fourier transform (DFT) DFT to each the integer-period sampled result who reads in the present embodiment, can call relevant algorithm, draw the size and the phase place of amount of unbalance in the present embodiment according to the type different mining of rotor with single face influence coefficient method or two-sided influence coefficient method.
In the single face influence coefficient method (following institute directed quantity is vector, promptly comprises size and phase place):
For the first time start rotor, under rated speed, recording single face maximum displacement or the vibratory output that amount of unbalance M causes is X0.Start rotor after adding test mass m on the one side of rotor, the displacement or the vibratory output that record single face are X1.Then amount of unbalance is: M=m*X0/ (X1-X0).
In two-sided influence coefficient method (following institute directed quantity is vector, promptly comprises size and phase place):
For the first time start rotor, under rated speed, record the amount of unbalance Ma of top and bottom, upper and lower side maximum displacement or the vibratory output that Mb causes is Xa, Xb;
Add test mass m1 in the upper end, for the second time start rotor, the maximum displacement or the vibratory output that record upper and lower side are Xa1, Xb1, and then the displacement or the vibration variation (influence coefficient) that cause of Shang Duan unit test mass is: A1=(Xa1-Xa)/m1; B1=(Xb1-Xb)/m1;
Remove upper end test mass m1, add test mass m2 in the lower end, start rotor for the third time, the maximum displacement or the vibratory output that record upper and lower side are Xa2, Xb2, and then the displacement that causes of the unit test mass of lower end or vibration change (influence coefficient) and be: A2=(Xa2-Xa)/m2; B2=(Xb2-Xb)/m2.
According to the physical meaning of influence coefficient, can get amount of unbalance and be:
Ma＝(Xa*B2-Xb*A2)/(A1*B2-A2*B1)；
Mb＝(Xb*A1-Xa*B1)/(A1*B2-A2*B1)。
As shown in Figure 3, provided the schematic diagram of the digital phase-locked and double frequency function of fpga chip realization.The basic pulse after the edge triggering phase detector comparison process and the phase differential of phase-locked pulse produce " counting direction pulse " signal, send into up-down counter.The clock CLK1 of up-down counter adopts the 50M of system clock to obtain through 8 frequency divisions, (default count value is a variable value to adjust current count value according to " counting direction pulse ", variable range: 8～131072, count value default in the present embodiment gets 65536): if " counting direction pulse " is that " height " then subtracts counting, when count value is 0, export " borrow pulse "; If " counting direction pulse " is that " low " then increases counting,, export " carry pulse " when count value is the count value that reaches default.The clock CLK2 of pulse add subtract control unit adopts the 50M of system clock to obtain through 32 frequency divisions in the present embodiment, it adjusts the frequency of output double frequency pulse signal according to increase or minimizing that " carry pulse " or " borrow pulse " counted: pulse add subtract control unit (when lockin signal and reference pulse signal locking) when not having " carry pulse " or " borrow pulse " carries out the output of 48 frequency divisions to the clock signal of input in the present embodiment; When " carry pulse " negative edge, controller increases an output clock period when output, and when " borrow pulse " negative edge, controller reduces by an output clock period when output.The pulse add subtract control unit is output as " double frequency pulse " signal.Frequency divider can be realized different double frequency functions by the setting of frequency division multiple, as 512 frequencys multiplication, 1024 frequencys multiplication, 2048 frequencys multiplication etc.What realize in the present embodiment is 512 frequencys multiplication, so frequency divider adopts 512 times of frequency divisions, its " double frequency pulse " signal that is input as pulse add subtract control unit output obtains behind 512 times of frequency divisions " lockin signal ", and sends into the edge and trigger phase detector and compare phase differential again with reference pulse signal.
As shown in Figure 4, provided the interface circuit figure of electrical level conversion chip and fpga chip and AD chip.Fpga chip in the present embodiment adopts XC3S200, and electrical level conversion chip adopts 74ALVC164245, and the AD chip adopts ADS7864.The sampling pattern of AD chip is selected position A2 in the present embodiment, A1, and A0 is preset 1,1,0, and promptly AD is operated under the pattern of circulation reading.Electrical level conversion chip is used for the mutual conversion between the 3.3V signal of the 5V signal of AD chip and fpga chip.
As shown in Figure 5, provided the AD chip sampling principle figure of fpga chip control.The double frequency pulse signal starts the AD chip by being provided with of state machine and transforms as the enabling signal of AD chip.Generally speaking, rotor dynamic balancing need be sampled to 4 radial direction displacements (or vibration) signal of rotor at most, and every road transformation time of ADS7864 needs 1.75 microseconds at least, adopt 2 road AD (4 passages: A0, A1, B0 and B1) that 4 tunnel sensor signals are sampled in the present embodiment, so the AD transformation time needs 3.5 microseconds at least.So starting the back, AD delays time by the 50M clock count, start after 4 microseconds of delaying time " reading 4 road AD result phase machines ", 4 road AD sampled result are read in the buffer memory of fpga chip, and after running through the four tunnel sampled result, producing a DSP look-at-me, notice DSP takes sampled result away from corresponding address location.
As shown in Figure 6, provided single sensor interface circuitry figure.Sensor interface circuitry is used for the signal of displacement or vibration transducer is amplified and bandpass filtering treatment, and delivers to the AD chip and wait for sampling.Adopted AD620 to carry out the amplification of displacement (or vibration) signal in the sensor interface circuitry, enlargement factor is determined by external potentiometer RG2; Adopted TL084 to design the second-order bandpass filter of displacement (or vibration) signal, the logical gain of the centre frequency of second-order bandpass filter and band can be adjusted peripheral resistance and the capacitance of TL084 according to the real work rotating speed of rotor.The real work speed-frequency is 66.67Hz (4000rpm) in the present embodiment, so the centre frequency of second-order bandpass filter is set to 66.67Hz (4000rpm), promptly when speed-frequency is 66.67Hz, pass through bandpass filter with rotating speed with displacement (vibration) signal frequently undampedly, the signal of other frequencies (high frequency or low frequency) is then decayed to some extent, reaches the purpose of filtering.
As shown in Figure 7, provided pulse processing circuit figure.Optoelectronic switch generates a reference pulse signal when rotor turns over the reference position, this signal carries out shaping pulse through 74LS14, and be 3V by two stabilivolts with the highest amplitude amplitude limit of shaped pulse signal, send into fpga chip through the reference pulse signal of shaping and amplitude limit and carry out phase-locked and process of frequency multiplication.
As shown in Figure 8, provided the DSP control flow in the present embodiment.Response external is interrupted 0 (INT0) when DSP detects phase-locked pulse signal, and the set of externally interrupting will " allowing the peek zone bit " among 0 (INT0) is read sampled value in order to allow DSP.Response external is interrupted 1 (INT1) when DSP detects the double frequency pulse signal, externally interrupt among 1 (INT1) if " allowing the peek zone bit " is " 1 ", then read sampled value from the corresponding address location of FPGA, after the sampled value of getting a complete cycle, incite somebody to action " allowing the peek zone bit " reset, integer-period sampled value is made discrete Fourier transform (DFT) (DFT), and call size and phase place that relevant transient equilibrium algorithm computation goes out amount of unbalance.
The present invention is the high accuracy number online dynamic balance detecting device based on FPGA, can adjust phase-locked centre frequency, phase-locked adjustment time and frequency (sample frequency) flexibly by the modification of VHDL language according to the actual requirements, and can realize the online detection of transient equilibrium under dissimilar rotors, the different operating state by the writing of different transient equilibrium control algolithms.
Claims (4)
1, a kind of high accuracy number online dynamic balance detecting device based on FPGA is characterized in that: comprising:
Fpga chip (3): link to each other with pulse processing circuit (2), dsp chip (4) and electrical level conversion chip (5), be used for the pulse signal that pulse processing circuit (2) is sent here is carried out phase-locked and frequency multiplication, and utilize double frequency pulse signal controlling AD chip (6) to sample, sampling finishes the post-sampling result and deposits corresponding address location, generate a sampling simultaneously and finish the external interrupt signal of pulse signal as DSP, notice DSP extracts sampled result;
Pulse processing circuit (2): link to each other with fpga chip (3) with optoelectronic switch (1), be used for the basic pulse that optoelectronic switch (1) produces is carried out shaping, and be 0～3V with the pulse amplitude amplitude limit, the pulse behind shaping and the amplitude limit is delivered in the fpga chip (3);
Sensor signal interface circuit (7): link to each other with AD chip (6), be used for the signal of displacement or vibration transducer (8) is amplified and bandpass filtering treatment, and deliver to AD chip (6) and wait for sampling;
Level transferring chip (5): link to each other with AD chip (6) with fpga chip (3), be used for the mutual conversion of corresponding voltage between the control signal of FPGA (3) and AD chip (6) output signal;
Dsp chip (4): link to each other with fpga chip (3), interrupt response is carried out in the phase-locked pulse of fpga chip (3) generation and the sampling end pulse of AD sampling end back generation, extract sampled value from the corresponding address location of FPGA (3), after extracting the sampled value of a complete cycle, sampled value to complete cycle is handled accordingly, thereby extract and the component of rotating speed, and, obtain the size and the phase place of amount of unbalance by corresponding amount of unbalance algorithm with frequency.
2, a kind of high accuracy number online dynamic balance detecting device according to claim 1 based on FPGA, it is characterized in that: described fpga chip (3) adopts the Spartan3 family chip of Xilinx company, realize function digital phase-locked and frequency multiplication, realize control simultaneously AD chip (6) high-speed sampling.
3, a kind of high accuracy number online dynamic balance detecting device based on FPGA according to claim 1 is characterized in that: described dsp chip (4) adopts the processor of TMS320VC3x series DSP as control algolithm.
4, a kind of high accuracy number online dynamic balance detecting device based on FPGA according to claim 1, it is characterized in that: described uneven algorithm is: single face influence coefficient method or two-sided influence coefficient method.
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| CN104819843A (en) * | 2015-05-17 | 2015-08-05 | 成都诚邦动力测试仪器有限公司 | Gearbox testing system of signal offset amplification type based on phase-locked loop control |
| CN106323548A (en) * | 2016-08-08 | 2017-01-11 | 浙江大学 | Double vibration sensor-based rotor imbalance vibration response identification method |
| CN110296729B (en) * | 2019-07-01 | 2020-10-30 | 哈尔滨理工大学 | Dynamic reliability detection equipment of groove type photoelectric sensor |
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| CN117484261B (en) * | 2023-12-29 | 2024-04-02 | 四川普什宁江机床有限公司 | Intelligent pre-balancing system for turntable of high-speed milling and turning composite machining center |
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| JPH10293060A (en) * | 1997-04-18 | 1998-11-04 | Ebara Corp | Vibration force monitoring system of rotating machine |
| CN2306502Y (en) * | 1997-08-06 | 1999-02-03 | 中国科学院长春光学精密机械研究所 | Dynamic balance driver |
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