CN100448002C - Method for producing stacked wafer - Google Patents
Method for producing stacked wafer Download PDFInfo
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- CN100448002C CN100448002C CNB2005101134517A CN200510113451A CN100448002C CN 100448002 C CN100448002 C CN 100448002C CN B2005101134517 A CNB2005101134517 A CN B2005101134517A CN 200510113451 A CN200510113451 A CN 200510113451A CN 100448002 C CN100448002 C CN 100448002C
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- chip
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- rerouting
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- pedestal
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
- H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L24/18—High density interconnect [HDI] connectors; Manufacturing methods related thereto
- H01L24/20—Structure, shape, material or disposition of high density interconnect preforms
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/02—Bonding areas; Manufacturing methods related thereto
- H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
- H01L2224/04105—Bonding areas formed on an encapsulation of the semiconductor or solid-state body, e.g. bonding areas on chip-scale packages
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/10—Bump connectors; Manufacturing methods related thereto
- H01L2224/15—Structure, shape, material or disposition of the bump connectors after the connecting process
- H01L2224/16—Structure, shape, material or disposition of the bump connectors after the connecting process of an individual bump connector
- H01L2224/161—Disposition
- H01L2224/16151—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
- H01L2224/16221—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
- H01L2224/16225—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
- H01L2224/16227—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation the bump connector connecting to a bond pad of the item
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/18—High density interconnect [HDI] connectors; Manufacturing methods related thereto
- H01L2224/19—Manufacturing methods of high density interconnect preforms
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/73—Means for bonding being of different types provided for in two or more of groups H01L2224/10, H01L2224/18, H01L2224/26, H01L2224/34, H01L2224/42, H01L2224/50, H01L2224/63, H01L2224/71
- H01L2224/732—Location after the connecting process
- H01L2224/73201—Location after the connecting process on the same surface
- H01L2224/73203—Bump and layer connectors
- H01L2224/73204—Bump and layer connectors the bump connector being embedded into the layer connector
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
- H01L2924/181—Encapsulation
- H01L2924/1815—Shape
- H01L2924/1816—Exposing the passive side of the semiconductor or solid-state body
- H01L2924/18162—Exposing the passive side of the semiconductor or solid-state body of a chip with build-up interconnect
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- Engineering & Computer Science (AREA)
- Computer Hardware Design (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Power Engineering (AREA)
- Lead Frames For Integrated Circuits (AREA)
- Wire Bonding (AREA)
Abstract
This invention relates to a manufacturing method for stacked chips, which first of all prepares a first wafer and a second wafer, after chips of the first wafer are cut, qualified chips are selected and put in a frame forming a base to let the chips combine with the base, then, designs multiple conduction holes on the base and multiple rearranged leads connecting to the contact points of the conduction holes and the chips, then designs the second wafer in the frame and a conductor is set between the second wafer and the frame, the contact points of the second wafer are connected to the contact points of the chips of the first wafer by a conductor to form multiple stacked chips, finally, eliminates the frame and separates said equal stacked chips.
Description
Technical field
The present invention is relevant with semiconductor chip, is meant a kind of method for making and structure of stacked chips especially.
Background technology
As shown in figure 10, structure for a kind of known stacked chips 80, include a substrate 81, one first chip 82 and one second chip 83, the area of first chip 82 is greater than the area of second chip 83, second chip 83 has a plurality of contacts 84, each contact 84 is located at substrate 81, the periphery of first chip 82 is provided with a plurality of soldered balls 85, first chip 82 is located at second chip, 83 tops, each soldered ball 85 of first chip 82 is located at substrate 81, and have a binder course 86 between first chip 82 and second chip 83, binder course 86 is in order to fix first chip 82 and second chip 83; Thus, first chip 82 and second chip 83 are and are located at substrate 81 with piling up shape mutually.
Yet, in the structure of above-mentioned stacked chips 80, first chip 82 is to coincide above second chip 83, make that the height of soldered ball 85 must be greater than the height of second chip 83, first chip 82 and second chip 83 could be stacked on the substrate 81, thereby make that the thickness of stacked chips 80 is thicker, also cause whole manufacturing cost higher simultaneously.
Summary of the invention
Main purpose of the present invention is to provide a kind of stacked chips.
Another object of the present invention is to provide a kind of method for making of stacked chips, it can improve the production yield of chip.
Another purpose of the present invention is to provide a kind of method for making of stacked chips, via the thinner thickness of the made chip of this method for making.
For achieving the above object, stacked chips provided by the invention includes:
One pedestal, this pedestal have a plurality of conductive holes and a plurality of rerouting lead, and respectively this rerouting lead electrical communication is in this conductive hole respectively;
One first chip, this first chip is located at this pedestal, and this first chip has a plurality of first contacts, respectively this first contact electrical communication this rerouting lead respectively;
One electric conductor, this electric conductor is located at this pedestal, makes respectively this rerouting lead electrical communication in this electric conductor; And
One second chip, this second chip has a plurality of second contacts, this second chip is located at this pedestal, make respectively this second contact by this electric conductor electrical communication in this first contact respectively.
Described stacked chips, wherein said rerouting lead is divided into the end face and the bottom surface of this pedestal, and each the rerouting lead that is positioned at this end face is electrically connected at respectively this first contact.
Described stacked chips, but wherein each rerouting lead of this base bottom surface has the contact of a tin ball or scolding tin.
Described stacked chips, wherein respectively this second chip has a plurality of rerouting leads, respectively this rerouting lead electrical communication of this second chip is in this second contact respectively, and the distributing position of the rerouting lead of this second chip is corresponding to the distributing position of the rerouting lead of this pedestal respectively.
Described stacked chips, wherein this electric conductor can be anisotropic conductive or tin ball.
Described stacked chips, wherein the end face of this first chip flushes the end face in this pedestal.
The method for making of stacked chips provided by the invention includes the following step:
A. prepare one first wafer and one second wafer, this first wafer has a plurality of first chips, and this second wafer has a plurality of second chips, and respectively this first chip has a plurality of first contacts, and respectively this second chip has a plurality of second contacts;
B. with described first chip after this first wafer cuts down, put again in a framework, and in this framework, form a pedestal, described first chip and this pedestal are mutually combined;
C. in this pedestal a plurality of conductive holes and a plurality of rerouting lead are set, respectively this rerouting lead difference electrical communication is in respectively this conductive hole and respectively this first contact;
D. an electric conductor is located at this pedestal, makes respectively this rerouting lead electrical communication in this electric conductor;
E. this second wafer is located at this framework, makes this electric conductor between this second wafer and this framework, respectively this second contact electrical communication is in first contact of this first chip respectively, to form a plurality of stacked chips; And
F. remove this framework, and separate described stacked chips.
The method for making of described stacked chips, in this step c, described rerouting lead is divided into the end face and the bottom surface of this pedestal, and each the rerouting lead that is positioned at this end face is electrically connected at respectively this first contact.
The method for making of described stacked chips when this step f, is provided with in addition a plurality of electrical communication in the rerouting lead of this conductive hole respectively in the bottom surface of this pedestal, but respectively this rerouting lead that is positioned at this bottom surface has the contact of a tin ball or scolding tin.
The method for making of described stacked chips, wherein respectively this second chip has a plurality of rerouting leads, respectively this rerouting lead electrical communication of this second chip is in this second contact respectively, and the distributing position of the rerouting lead of this second chip is corresponding to the distributing position of the rerouting lead of this pedestal respectively.
The method for making of described stacked chips, wherein this electric conductor can be anisotropic conductive or tin ball.
The method for making of described stacked chips, wherein the end face of this first chip flushes the end face in this pedestal.
The method for making of described stacked chips, wherein the area of this framework generally is same as the area of this second wafer.
The method for making of stacked chips provided by the invention can also include the following step:
A. prepare one first wafer and one second wafer, this first wafer has a plurality of first chips, and this second wafer has a plurality of second chips, and respectively this first chip has a plurality of first contacts, and respectively this second chip has a plurality of second contacts;
B. with described first chip after this first wafer cuts down, put respectively again in this second wafer, make second contact of each second chip be electrically connected at first contact of each first chip;
C. this second wafer is located at a pedestal, and in this pedestal a plurality of conductive holes and a plurality of rerouting lead is set, respectively this rerouting lead difference electrical communication is in each conductive hole and each first or second contact, to form a plurality of stacked chips; And
D. separate respectively this stacked chips.
Description of drawings
Fig. 1 is the method for making schematic diagram of a preferred embodiment of the present invention, mainly shows the state of first wafer;
Fig. 2 is the method for making schematic diagram of a preferred embodiment of the present invention, mainly shows the state of second wafer;
Fig. 3 is the method for making schematic diagram of a preferred embodiment of the present invention, shows that mainly first chip is located at the state in the framework;
Fig. 4 is the method for making schematic diagram of a preferred embodiment of the present invention, main display base and the state of first chips incorporate in framework;
Fig. 5 is the method for making schematic diagram of a preferred embodiment of the present invention, shows that mainly conductive hole forms in the state of pedestal;
Fig. 6 is the cutaway view of 6-6 hatching line among Fig. 5;
Fig. 7 is the method for making schematic diagram of a preferred embodiment of the present invention, shows that mainly the rerouting lead is located at the state of pedestal;
Fig. 8 is the method for making schematic diagram of a preferred embodiment of the present invention, shows that mainly second wafer is located at the state of framework;
Fig. 9 is the schematic diagram of a preferred embodiment of the present invention, mainly shows the structure of stacked chips; And
Figure 10 is known structural representation with stacked chips.
Embodiment
Following conjunction with figs. is enumerated a preferred embodiment, in order to method for making of the present invention and effect are elaborated.
The method for making of stacked chips that this preferred embodiment provides includes the following step:
Step 1, as shown in Figures 1 and 2, prepare one first wafer 10 and one second wafer 20, first wafer 10 forms a plurality of first chips 12 after cutting, second wafer 20 has a plurality of second chips 22, each first chip 12 has a plurality of first contacts 14, and each second chip 22 has a plurality of second contacts 24; First chip 12 can be dsp chip, and second chip 22 can be the CMOS or the video sensing chip of CCD form.
Step 2, is as shown in Figure 3 chosen the second best in quality first chip 12, more described first chip 12 is put in a framework 30, and the area of framework 30 generally is same as the area of second wafer 20.
Step 3, as shown in Figure 4 pours into colloid in framework 30, treat colloid solidify to form a pedestal 32 after, can make described first chip 12 be incorporated into framework 30 inside by pedestal 32.
Step 4, as Fig. 5 and shown in Figure 6, at pedestal 32 a plurality of conductive holes 34 are set, each conductive hole 34 is through the end face and the bottom surface of pedestal 32, described conductive hole 34 is evenly distributed in the periphery of each first chip 12.
Step 5, as shown in Figure 7 is provided with a plurality of rerouting leads 36 in the end face of pedestal 32, each rerouting lead 36 respectively electrical communication in first contact 14 and each conductive hole 34 of each first chip 12.
Step 6, is as shown in Figure 8 established an electric conductor 40 in pedestal 32 and each first chip, 12 end face, again second wafer 20 is attached at electric conductor 40; Electric conductor 40 can be anisotropic conductive or tin ball, and electric conductor 40 settings and electrical communication are in each rerouting lead 36, so that each rerouting lead 36 electrical communication is in each first contact 14 of first chip 12; The position of second contact 24 of second chip 22 is corresponding to the position of each rerouting lead 36, also can be used for the rerouting lead that second chip 22 is provided with a plurality of connection second contacts 24, the distributing position of rerouting lead that makes second chip 22 is corresponding to the distributing position of the rerouting lead 36 of each pedestal 32; When second wafer 20 is located at electric conductor 40, second contact 24 of each second chip 22 is by first contact 14 of electric conductor 40 electrical communication in each first chip 12, simultaneously, the structure that coincides mutually of respectively second chip 22 of each first chip 12 of second wafer 20 and first wafer 10 can form a plurality of stacked chips 50.
Step 7, framework 30 is located away from pedestal 32, then in pedestal 32 bottom surfaces the rerouting lead 38 of a plurality of electrical communication in conductive hole 34 is set again, each rerouting lead 38 is established a tin ball 39 in addition, makes each stacked chips 50 be the BGA pattern.
Step 8, the described stacked chips 50 of cutting can be finished method for making of the present invention; As shown in Figure 9, the structure of stacked chips 50 includes a pedestal 32, one first chip 12, one second chip 22, and a electric conductor 40 between first chip 12 and second chip 22; Pedestal 32 has a plurality of conductive holes 34, and a plurality of rerouting leads 36,38 that are divided into pedestal 32 end faces and bottom surface, each rerouting lead 36,38 electrical communication is in each conductive hole 34, but each rerouting lead 38 of pedestal 32 bottom surfaces is provided with the metallic contact of a tin ball 39 or scolding tin.
This first chip 12 is located in the pedestal 32, and the end face of first chip 12 flushes in pedestal 32 end faces, and first chip 12 has a plurality of first contacts 14, each rerouting lead 36 of each first contact, 14 electrical communication pedestals, 32 end face; This electric conductor 40 can be anisotropic conductive or tin ball, and this electric conductor 40 is located at the end face of pedestal 32, makes each rerouting lead 36 and electric conductor 40 mutual electrical communication.
The bottom surface of this second chip 22 has a plurality of second contacts 24, second contact 24 also can utilize the mode of rerouting to change distributing position, the distributing position of second contact 24 is corresponding to the position of each rerouting lead 36, second chip 22 coincides in the end face of pedestal 32, make each second contact 24 by electric conductor 40 electrical communication in each first contact 14.
Via above-mentioned explanation, because first chip 12 that is located in the framework 30 is to pick out the second best in quality assembly through in advance, just directly mutually combine by electric conductor 40 again, thereby make that the yield of the stacked chips 50 that this method for making of process is made is higher, and then reduce whole cost with second wafer 20; Simultaneously, if the overall dimension of first chip 12 is different from the overall dimension of second chip 22, first contact 14 of first chip 12 and second contact 24 of second chip 22 also can utilize the mode of rerouting to change distributing position, with so that the contact 14,24 of first and second chip 12,22 is corresponding mutually, two chips 12,22 still can utilize electric conductor 40 to pile up mutually, utilize electric conductor 40 to link first chip 12 and second chip 22, make the integral thickness of stacked chips 50 thinner.
Thus, the present invention can reach that production cost is lower, yield is higher, and the thin purpose of finished product thickness.
In addition, in the aforementioned method for making of the present invention, also can be when making first wafer, each first contact at each first chip carries out circuit layout re-layout simultaneously, and the distributing position of first contact that makes each first chip is corresponding to the distributing position of second contact of each second chip; Then, after again each first chip cutting being got off, select each second chip that the second best in quality first chip directly is incorporated into second wafer, second wafer that will have described first chip then is located at a pedestal, pedestal is provided with a plurality of conductive holes and a plurality of rerouting lead, and each rerouting lead electrical communication is in the contact of each conductive hole and each chip, thus, equally also can form a plurality of stacked chips structures, separate each stacked chips at last again and get final product.
Claims (8)
1. the method for making of a stacked chips includes the following step:
A. prepare one first wafer and one second wafer, this first wafer has a plurality of first chips, and this second wafer has a plurality of second chips, and respectively this first chip has a plurality of first contacts, and respectively this second chip has a plurality of second contacts;
B. with described first chip after this first wafer cuts down, put again in a framework, and in this framework, form a pedestal, make the inside of described first chips incorporate at pedestal;
C. a plurality of conductive holes are set and end face is provided with a plurality of rerouting leads in this pedestal, respectively this rerouting lead respectively electrical communication in this conductive hole respectively and this first contact respectively;
D. an electric conductor is located at this pedestal, makes respectively this rerouting lead electrical communication in this electric conductor;
E. this second wafer is located at this framework, makes this electric conductor between this second wafer and first chip, respectively this second contact electrical communication is in first contact of this first chip respectively, to form a plurality of stacked chips; And
F. remove this framework, and separate described stacked chips.
2. according to the method for making of the described stacked chips of claim 1, it is characterized in that in this step c, described rerouting lead is divided into the end face and the bottom surface of this pedestal, each the rerouting lead that is positioned at this end face is electrically connected at respectively this first contact.
3. according to the method for making of the described stacked chips of claim 1, it is characterized in that, when this step f, a plurality of electrical communication are set in addition in the rerouting lead of this conductive hole respectively in the bottom surface of this pedestal, but respectively this rerouting lead that is positioned at this bottom surface has the contact of a tin ball or scolding tin.
4. according to the method for making of the described stacked chips of claim 1, it is characterized in that, wherein respectively this second chip has a plurality of rerouting leads, respectively this rerouting lead electrical communication of this second chip is in this second contact respectively, and the distributing position of the rerouting lead of this second chip is corresponding to the distributing position of the rerouting lead of this pedestal respectively.
5. according to the method for making of the described stacked chips of claim 1, it is characterized in that wherein this electric conductor can be anisotropic conductive or tin ball.
6. according to the method for making of the described stacked chips of claim 1, it is characterized in that wherein the end face of this first chip flushes the end face in this pedestal.
7. according to the method for making of the described stacked chips of claim 1, it is characterized in that wherein the area of this framework generally is same as the area of this second wafer.
8. the method for making of a stacked chips includes the following step:
A. prepare one first wafer and one second wafer, this first wafer has a plurality of first chips, and this second wafer has a plurality of second chips, and respectively this first chip has a plurality of first contacts, and respectively this second chip has a plurality of second contacts;
B. with described first chip after this first wafer cuts down, put respectively again in this second wafer, make second contact of each second chip be electrically connected at first contact of each first chip;
C. this second wafer is located at a pedestal, and in this pedestal a plurality of conductive holes and a plurality of rerouting lead is set, respectively this rerouting lead difference electrical communication is in each conductive hole and each first or second contact, to form a plurality of stacked chips; And
D. separate respectively this stacked chips.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CNB2005101134517A CN100448002C (en) | 2005-10-09 | 2005-10-09 | Method for producing stacked wafer |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CNB2005101134517A CN100448002C (en) | 2005-10-09 | 2005-10-09 | Method for producing stacked wafer |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| CN1945828A CN1945828A (en) | 2007-04-11 |
| CN100448002C true CN100448002C (en) | 2008-12-31 |
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| Application Number | Title | Priority Date | Filing Date |
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| CNB2005101134517A Active CN100448002C (en) | 2005-10-09 | 2005-10-09 | Method for producing stacked wafer |
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Citations (5)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US6228682B1 (en) * | 1999-12-21 | 2001-05-08 | International Business Machines Corporation | Multi-cavity substrate structure for discrete devices |
| CN1484308A (en) * | 2002-09-17 | 2004-03-24 | ���˻�˹�����̩�˹ɷ�����˾ | Open type multi-chip stacking package unit |
| US6717253B2 (en) * | 2002-01-31 | 2004-04-06 | Advanced Semiconductor Engineering, Inc. | Assembly package with stacked dies and signal transmission plate |
| US20040217485A1 (en) * | 2003-05-02 | 2004-11-04 | Advanced Semiconductor Engineering Inc. | Stacked flip chip package |
| US20040251531A1 (en) * | 2002-01-25 | 2004-12-16 | Yang Chaur-Chin | Stack type flip-chip package |
-
2005
- 2005-10-09 CN CNB2005101134517A patent/CN100448002C/en active Active
Patent Citations (5)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US6228682B1 (en) * | 1999-12-21 | 2001-05-08 | International Business Machines Corporation | Multi-cavity substrate structure for discrete devices |
| US20040251531A1 (en) * | 2002-01-25 | 2004-12-16 | Yang Chaur-Chin | Stack type flip-chip package |
| US6717253B2 (en) * | 2002-01-31 | 2004-04-06 | Advanced Semiconductor Engineering, Inc. | Assembly package with stacked dies and signal transmission plate |
| CN1484308A (en) * | 2002-09-17 | 2004-03-24 | ���˻�˹�����̩�˹ɷ�����˾ | Open type multi-chip stacking package unit |
| US20040217485A1 (en) * | 2003-05-02 | 2004-11-04 | Advanced Semiconductor Engineering Inc. | Stacked flip chip package |
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| Publication number | Publication date |
|---|---|
| CN1945828A (en) | 2007-04-11 |
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