CN100447966C - Integrated ball and via package and formation process - Google Patents

Integrated ball and via package and formation process Download PDF

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Publication number
CN100447966C
CN100447966C CNB2005800147664A CN200580014766A CN100447966C CN 100447966 C CN100447966 C CN 100447966C CN B2005800147664 A CNB2005800147664 A CN B2005800147664A CN 200580014766 A CN200580014766 A CN 200580014766A CN 100447966 C CN100447966 C CN 100447966C
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Prior art keywords
semiconductor device
carrier structure
conductor
lead
free air
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CN1950934A (en
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戴维·T·贝特松
林智民
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Kulicke and Soffa Investments Inc
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Kulicke and Soffa Investments Inc
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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/4805—Shape
    • H01L2224/4809—Loop shape
    • H01L2224/48091—Arched
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/4805—Shape
    • H01L2224/4809—Loop shape
    • H01L2224/48095—Kinked
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/481—Disposition
    • H01L2224/48151—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/48221—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/48225—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
    • H01L2224/4824—Connecting between the body and an opposite side of the item with respect to the body
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/74—Apparatus for manufacturing arrangements for connecting or disconnecting semiconductor or solid-state bodies and for methods related thereto
    • H01L2224/78—Apparatus for connecting with wire connectors
    • H01L2224/7825—Means for applying energy, e.g. heating means
    • H01L2224/783—Means for applying energy, e.g. heating means by means of pressure
    • H01L2224/78301—Capillary
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    • H01—ELECTRIC ELEMENTS
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    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
    • H01L2224/85—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a wire connector
    • H01L2224/8512—Aligning
    • H01L2224/85148—Aligning involving movement of a part of the bonding apparatus
    • H01L2224/85169—Aligning involving movement of a part of the bonding apparatus being the upper part of the bonding apparatus, i.e. bonding head, e.g. capillary or wedge
    • H01L2224/8518—Translational movements
    • H01L2224/85181—Translational movements connecting first on the semiconductor or solid-state body, i.e. on-chip, regular stitch
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
    • H01L2224/85—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a wire connector
    • H01L2224/8512—Aligning
    • H01L2224/85148—Aligning involving movement of a part of the bonding apparatus
    • H01L2224/85169—Aligning involving movement of a part of the bonding apparatus being the upper part of the bonding apparatus, i.e. bonding head, e.g. capillary or wedge
    • H01L2224/8518—Translational movements
    • H01L2224/85186—Translational movements connecting first outside the semiconductor or solid-state body, i.e. off-chip, reverse stitch
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/0001—Technical content checked by a classifier
    • H01L2924/00014—Technical content checked by a classifier the subject-matter covered by the group, the symbol of which is combined with the symbol of this group, being disclosed without further technical details
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    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/013—Alloys
    • H01L2924/014—Solder alloys
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/10—Details of semiconductor or other solid state devices to be connected
    • H01L2924/11—Device type
    • H01L2924/14—Integrated circuits
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    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
    • H01L2924/181—Encapsulation
    • H—ELECTRICITY
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    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/30—Technical effects
    • H01L2924/301—Electrical effects
    • H01L2924/30107—Inductance

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  • Lead Frames For Integrated Circuits (AREA)
  • Wire Bonding (AREA)

Abstract

A method of processing a semiconductor device is provided. The method includes providing a semiconductor device supported by a carrier structure. The carrier structure defines a plurality of vias from a first surface of the carrier structure adjacent the semiconductor device to a second surface of the carrier structure. The method also includes extending a conductor through one of the vias such that a first end of the conductor at least partially extends below the second surface. The method also includes electrically coupling another portion of the conductor to a portion of the semiconductor device.

Description

The encapsulation of integrated ball and via hole and formation technology
Cross reference
The present invention relates to and require the U.S. Provisional Application sequence number No.60/570 of submission on May 12nd, 2004, the U.S. Provisional Patent Application sequence number No.60/660 that on March 9th, 704 and 2005 submitted to, 486 priority, it is all incorporated into once more by reference.
Technical field
The present invention relates to be used for the technology of processing semiconductor device, relate in particular to the technology that is used for providing to semiconductor device the electricity connection by carrier structure.
Background technology
In the processing and encapsulation of semiconductor device (as the BGA device), integrated circuit (IC)-components (as semiconductor crystal wafer or chip) is installed in the upper surface of multilayer board usually, wherein, printed circuit board (PCB) comprises the plated via (via) from the upper surface break-through of this printed circuit board (PCB) to the printed circuit board (PCB) lower surface.Solder ball links to each other with the contact mat electricity of the plated via of printed circuit board (PCB) lower surface (as adopting solder reflow process).The part (as the contact mat on the integrated circuit (IC)-components) that lead engages the contact mat of the plated via of (1) printed circuit board (PCB) upper surface and (2) integrated circuit (IC)-components couples together to conductivity.Therefore, by the plated via on the printed circuit board (PCB), the contact mat of integrated circuit (IC)-components can be electrically connected with solder ball.
Unfortunately, the processing of this traditional integrated circuit (IC)-components and the huge and processed complex of encapsulation cost.Moreover, because the processing and the combination of materials of these complexity, electrical property is affected through regular meeting.For example, be used to support that the multilayer board of integrated circuit (IC)-components is tending towards expensive.Similarly, solder ball material also is tending towards expensive with relevant reflux technique.
Therefore, need provide a kind of processing method of semiconductor/integrated circuit (IC)-components, this method can overcome one or more above-mentioned shortcomings.
Summary of the invention
According to one example embodiment, a kind of method of processing semiconductor device is provided, described method comprises the following steps: to provide the semiconductor device of being supported by carrier structure, and this carrier structure limits a plurality of via holes from the first surface of this carrier structure adjacent with described semiconductor device to the second surface of this carrier structure; Conductor extension is passed a described via hole, make first end of this conductor extend at least in part under this second surface, wherein these a plurality of via holes that limited by this carrier structure were limited before this extension step in advance; After this extends step, at first end formation free air balls of described conductor; Described free air balls is pulled at least in part with described second surface contacts; And another part of this conductor is electrically connected with the part of this semiconductor device.
According to another example embodiment of the present invention, provide a kind of processing method of semiconductor device.This method comprises provides a kind of semiconductor device of being supported by carrier structure.This carrier structure limits a plurality of via holes from the first surface of the carrier structure adjacent with semiconductor device to the second surface of carrier structure.This method also comprises provides a kind of template, is provided with a plurality of grooves in the first surface of this template.This method also comprises conducting sphere is placed in the groove at least in part.This method also is included in alignment of semiconductor devices on the template, makes at least a portion of a plurality of via holes align with a conducting sphere respectively.This method comprises that also the first end lead with conductor joins on the conducting sphere, and the second end lead of conductor is joined on the part of semiconductor device.
Description of drawings
The present invention will be described in detail below in conjunction with accompanying drawing, to make the present invention easier to understand.What particularly point out is that routinely, each part among the figure is all made not in scale.On the contrary, for the purpose of clear, the size of each part is at random amplified or is reduced.Accompanying drawing comprises following figure:
Fig. 1 is this end view according to the lead bond semiconductor device of an example embodiment of invention;
Fig. 2 is the end view of the lead bond semiconductor device after according to one example embodiment the encapsulation;
Fig. 3 A-3E is the schematic diagram of the lead bonding operation that is used for the processing semiconductor device according to one example embodiment;
Fig. 4 is the end view with lead bond semiconductor device that stacked conductors engages after according to one example embodiment the encapsulation;
Fig. 5 A-5F is the end view of the process operation of semiconductor device according to one example embodiment;
Fig. 6 A-6D is the end view of another process operation of semiconductor device according to one example embodiment;
Fig. 7 illustrates the flow chart of processing method of semiconductor/integrated circuit (IC)-components according to one example embodiment;
Fig. 8 illustrates the flow chart of another processing method of semiconductor/integrated circuit (IC)-components according to one example embodiment; And
Fig. 9 illustrates the flow chart of another processing method of semiconductor/integrated circuit (IC)-components according to one example embodiment.
Embodiment
Herein, term " semiconductor device " and " integrated circuit (IC)-components " mean (nude film or the encapsulated) device arbitrarily with semiconductor property, such as the device after wafer, chip, the encapsulation etc.In addition, these terms are used interchangeably.In addition, term " semiconductor device " can refer to finished integrated circuit (IC)-components (is accessible as chip or wafer, its be installed on carrier or the substrate and contact with electricity with the lead joint etc.).
Herein, term " contact mat " means any conductive region that being used for transmission or received signal (as signal, power supply or ground connection) on semiconductor device or the substrate/carrier, and it is not limited to any specific configuration.For example, contact mat can be a conductive region on the semiconductor chip, is configured to be used to connect an end of conductor loop.Equally, contact mat can be carrier or on-chip conductive region, is configured to be used to connect the other end of bonded wire loop.
Followingly release, the invention provides the semiconductor device (and semiconductor device fabrication method of expensive efficient) of expensive efficient packaged by each example embodiment.The present invention is particularly suitable for being applied in the semiconductor device after the encapsulation, and this semiconductor device utilization is positioned at its surperficial conducting sphere/sphere, thus provide with this encapsulation after the electrically contacting of device (as the BGA device); Yet the present invention is not limited to this.According to one example embodiment, in single processing, (1) conduction place (as conducting sphere or sphere) can partly be formed under the carrier structure at least, (2) conductive path (lead) can form by the via hole that is arranged in carrier structure, and (3) can be on semiconductor crystal wafer configure interconnected (engaging) as lead.
In addition, according to one example embodiment, provide the three-dimension packaging interconnection of ball with the different size that is used for second level interconnection (as different dimensional requirements).
Fig. 1 is the end view of semiconductor device 100.Semiconductor device 100 comprises the integrated circuit (IC)-components of being supported by carrier structure 102 104 (as semiconductor crystal wafer).Though integrated circuit (IC)-components 104 is illustrated as directly contacting with carrier structure 102, be not limited thereto, because other structure can be provided between them.In addition, though integrated circuit (IC)-components 104 is illustrated as individual devices, but a plurality of stacked devices (as mutual stacked a plurality of wafer/chips) can support that wherein one or more stacked devices are electrically connected by carrier structure according to the present invention by carrier structure 102.
Carrier structure 102 can make up and can comprise any multiple material with any various configurations.For example, carrier structure 102 can be printed circuit board (PCB), layered substrates or ceramic monolith; Yet as described below, carrier structure 102 is more preferably with simply and not expensive structure manufacturing.For example, carrier structure 102 can be polymers/plastics sheet (as polystyrene, polyurethane or a polyimide piece etc.).
Carrier structure 102 limits from the first surface of (1) integrated circuit (IC)-components 104 and extends to (2) a plurality of aperture 102a away from the second surface of integrated circuit (IC)-components 104.The not necessarily any specific shape of aperture 102a.In Fig. 1, aperture 102a is illustrated as wedge shape, and matching with lead joining tool (as described below), but they are not limited to this configuration.
102 lower surface provides conductive path (as comprise such as materials such as gold, copper, aluminium, palladium and alloys thereof lead) from integrated circuit (IC)-components 104 to carrier structure.More specifically, this conductive path comprises conducting sphere 106 (as the free air balls that solidifies) and by the lead 108 that begins to extend and be engaged to the part of integrated circuit (IC)-components 104 from conducting sphere the contact mat of integrated circuit (IC)-components 104 (as be connected to).Preferably, conducting sphere 106 is formed by melting rod (being the EFO rod) as electronics by the part of lead 108.The CONSTRUCTED SPECIFICATION of semiconductor device 100 will be in the following more specific description of carrying out, for example, and with reference to figure 3A-3E.
Fig. 2 has illustrated semiconductor device 112, this semiconductor device is similar to the semiconductor device 100 shown in Fig. 1 basically, except semiconductor device 112 comprises encapsulating material 110, this encapsulating material 110 is used for the part of packaging integrated circuit devices 104, conductor 108 and conducting sphere 106.
Though Figure 102 shows single semiconductor device (100 or 112),, be actual with the form processing semiconductor device of array in specific occasions.For example, a plurality of integrated circuit (IC)-components can be processed on bigger carrier structure, and engage or other processing (as encapsulation) is separated after finishing at lead.
Fig. 3 A-3E has illustrated the part of method of processing semiconductor device.In Fig. 3 A, show the system that a part of lead engages, comprising: (1) lead joining tool 306 (as capillary 306); (2) extend through the lead 304 of the passage that limits by lead joining tool 306; And (3) influence the wire clamp 308 that move of lead 304 in the passage that is limited by lead joining tool 306.
In Fig. 3 A, lead joining tool 306 moves with roughly downward direction, makes the part of lead 304 extend through the hole 302a that is limited by carrier structure 302, and wire clamp 308 is positioned at off-position simultaneously.Aperture 302a can form in many ways.For example, they can be by pre-punching, pre-etching or boring before the lead bonding operation begins.Perhaps, aperture 302a can be formed by laser etc. during the lead bonding operation.
In Fig. 3 B, wire clamp 308 still is positioned at off-position, and the end that energy 310 (being provided by EFO rod etc.) is applied to lead 304 is to form free air balls 304a, and lead joining tool 306 is mentioned to the lower surface of carrier structure 310.In Fig. 3 C, wire clamp 308 still is positioned at detent position, and still apply energy 310 with to free air balls 304a insulation, lead joining tool 306 is further mentioned, and makes free air balls 304a enter in the part in (as fusing, with adhesive attachment etc.) hole 302.More specifically, according to one example embodiment, the free air balls 304a of heat is molten into plastic construction (part as carrier is melted), thereby is fixed thereon.According to another example embodiment of the present invention, conducting sphere (as free air balls 304a) can use adhesive to be attached on the carrier structure at Kong Chu, perhaps use extra adhesive except wedged hole (wherein on the surface of carrier structure, the hole is bigger, and conducting sphere can enter in the hole by it) is outer.Can consider that also other is used for conducting sphere is fixed in configuration as an alternative on the carrier structure.
In Fig. 3 D, free air balls 304a is positioned at the fixed position, and wire clamp 308 is positioned at open position, and operation lead joining tool 306 twines leads to the integrated circuit (IC)-components of being supported by carrier structure 302 312, forms conductor loop 316 thus.In Fig. 3 E, wire clamp 308 is in off-position, and the end 314 of conductor loop 316 was joined to the contact mat (not shown) of integrated circuit (IC)-components 312 by lead after, lead 304 was cut off/avulses bonded wire loop 316.
Fig. 4 is the end view of semiconductor device 400.Semiconductor device 400 comprises the integrated circuit (IC)-components of being supported by carrier structure 402 404.Carrier structure 402 limits from (1) and integrated circuit (IC)-components 404 adjacent first surfaces and extends to (2) some apertures away from the second surface of integrated circuit (IC)-components 404.Conductor loop 408 (conducting sphere 406 is attached thereto) extends to the junction point 408a that engages with the contact mat (not shown) of integrated circuit (IC)-components 404 from the lower surface (passing conducting sphere 406) of carrier structure 402.Semiconductor device 400 comprises the encapsulating material of a part that is used for packaging integrated circuit devices 404, conductor/wire ring 408 and conducting sphere 406.As shown in Figure 4, conductor loop 408 is (conductor loop is positioned on another conductor loop 408 at least in part) of mutual " stacked ", so that a kind of semiconductor device 400 that has more the encapsulation of space efficiency to be provided.
Fig. 5 A-5F has illustrated the present invention's example embodiment as an alternative.When the BGA of device side needs big ball, this embodiment is particularly useful, though it is not limited to this.In Fig. 5 A, semiconductor device 500 is illustrated as and comprises the integrated circuit (IC)-components of being supported by carrier structure 504 502.Carrier structure 504 limits the hole 504a that passes wherein.
In Fig. 5 B, the 506a model/template 506 that forms groove is provided, be used for the interim processing of semiconductor device.Conducting sphere 508 (as preformed gold, copper or Ag ball etc.) is arranged in groove 506a at least in part.In Fig. 5 C, semiconductor device 500 (comprising integrated circuit (IC)-components 502 and carrier structure 504) is positioned on the template 506, makes aperture 504a and conducting sphere 508 align.
In Fig. 5 D, conductor loop 510 is bonded between the contact mat (not shown) of conducting sphere 508 and integrated circuit (IC)-components 502 by lead.In Fig. 5 E, encapsulating material 512 is used to integrated circuit (IC)-components 500 and conductor loop 510, to form the semiconductor device 514 of encapsulation.In Fig. 5 F, the semiconductor device 514 of encapsulation separates by the demoulding or from template 506.
Fig. 6 A-6D has illustrated another example embodiment as an alternative of the present invention.When the BGA of device side needs big ball, this embodiment is particularly useful, though it is not limited to this.Fig. 6 A has illustrated by the integrated circuit (IC)-components 600 of carrier structure 602 supports.Carrier structure 602 limiting hole 602a dispose conductive contact 604 under the 602a of hole.
For example, carrier structure 602 can be formed by plastic sheet.Work in-process, conductive foil etc. can be placed on the surface (bottom surface of Fig. 6 A) of plastic sheet.Conductive foil is by etching optionally, forming conductive contact 604, and can in plastic sheet, bore, wear, etching or punch with formation aperture 602a with other method.
In Fig. 6 B, conductor loop 606 is bonded between the contact mat (not shown) of conductive contact 604 and integrated circuit 600 by lead.In Fig. 6 C, encapsulating material 608 is used to integrated circuit (IC)-components 600 and conductor loop 606.In Fig. 6 D, solder ball is (as using solder reflow process) that are electrically connected with the lower surface of conductive contact 604, thereby forms the semiconductor device of encapsulation.
Fig. 7-9 has illustrated according to the flow chart of the method for the processing semiconductor device of each example embodiment of the present invention.More specifically, Fig. 7 roughly is associated with the example structure shown in Fig. 1-2,3A-3E and 4; Yet the method for Fig. 7 is not limited to the strictness configuration of these example structure.Equally, though Fig. 8 is associated with the example structure shown in the 5A-5F substantially, the method for Fig. 8 is not limited to the strictness configuration of these example structure.In addition, though Fig. 9 is associated with the example structure shown in the 6A-6D substantially, the method for Fig. 9 is not limited to the strictness configuration of these example structure.It should be noted that according to certain embodiment of the present invention, can be omitted in the flow chart step shown in Fig. 7-9, adjustment order or replace.
Please see Figure 7 exemplary process method now,, provide the semiconductor device of supporting by carrier structure in step 700.For example, this carrier structure can comprise any multiple material and have certain varied in thickness scope, as long as it can satisfy the required machinery of this carrier structure (and other is essential) characteristic.For example, because its low cost and machining property, slice plastic is the examples material that can be used for this carrier structure.The a plurality of via holes of this carrier structure definition from the first surface of the carrier structure adjacent to the second surface of carrier structure with semiconductor device.
In addition, can a plurality of semiconductor device of time processing, wherein a plurality of integrated circuit (IC)-components are by sizable carrier structure support, and after device fabrication (engage as lead and encapsulation etc.), carrier structure can be separated so that a plurality of semiconductor device to be provided.
In step 702, the conductor lead of lead joining tool (as extend through) extends through a via hole, makes first end of conductor extend under the second surface at least in part.In step 704, free air balls is formed on first end of conductor.In step 706, free air balls is pulled at least in part and contacts with the second surface of carrier structure.Step 708 (it can be synchronous with step 706), when free air balls is pulled to when contacting with the second surface of carrier structure at least in part, heat is added on the free air balls.
In step 710, another part of conductor (as second end) is electrically connected with the part of semiconductor device (as the contact mat of semiconductor device).For example, step 710 can comprise that the second end lead with conductor joins on the contact mat of semiconductor device.According to example embodiment of the present invention, step 702,704,706,708 and 710 can be considered the processing of lead, to form first conductor loop between two contact points (conducting sphere of the second surface of carrier structure and the contact mat of semiconductor device).
In step 712, by in step 702,704,706,708 and 710 described, another conductor can be processed to second conductor loop, makes second conductor loop be positioned at least in part on first conductor loop, thereby the semiconductor device of the encapsulation with space efficiency is provided.
In step 714, semiconductor device (comprising wire bonded conductor) is packed so that the semiconductor device after the encapsulation to be provided.
With reference now to the exemplary process method of Fig. 8,,, provides the semiconductor device of supporting by carrier structure in step 800.Carrier structure limits a plurality of via holes from the first surface of the carrier structure adjacent with semiconductor device to the second surface of carrier structure.In step 802, a kind of template is provided, limit a plurality of grooves at the first surface of this template.In step 804, conductive contact is placed in the groove at least in part.In step 806, semiconductor device is aligned on the template, and each is aimed at conductive contact respectively to make at least a portion of a plurality of via holes.In step 808, first end of conductor is joined to a conductive contact by lead, and in step 810, second end of conductor is joined to the part of semiconductor device (as the contact mat of semiconductor device) by lead.In step 812, the conductor that semiconductor device and lead engage is packed.In step 814, the semiconductor device after the encapsulation (together with carrier structure and conductive contact) is separated from template so that the semiconductor device after the encapsulation to be provided.
Please see Figure 9 exemplary process method now,, provide the semiconductor device of supporting by carrier structure in step 900.Carrier structure limits a plurality of via holes from the first surface of the carrier structure adjacent with semiconductor device to the second surface of carrier structure.Step 902 (it can be used as the part of step 900 and consider), the part at the via hole adjacent with the second surface of carrier structure disposes conductive contact at least.For example, can provide conductive layer (as Copper Foil etc.) at second surface adjacent, and the selected portion of conductive layer can be etched to form conductive contact with carrier structure.In step 904, first end of conductor is joined to a conductive contact by lead.In step 906, second end of conductor is joined to the part (as the contact mat of semiconductor device) of semiconductor device by lead.In step 908, the conductor that semiconductor device and lead engage is packed.In step 910, solder ball is connected with conductive contact surface electrical away from carrier structure.
By above-mentioned method, the present invention provides significant improvement to traditional semiconductor processing technology.For example, can avoid using quite expensive multilayer board, and can adopt simple carrier structure (as plastic sheet) with plated via.In addition, for example adopt lead joining technique disclosed herein, can avoid using a large amount of welding processing in tradition processing.Further, by technology disclosed herein (as engaging), can provide littler packaging by on semiconductor crystal wafer, forming second lead.
Other useful aspect of the present invention comprises and reduces processing/assembly cost, improves electric property (as current capacity, resistance and inductance) and improves thermal property.
The present invention is particularly useful in the arrayed applications of neighboring area, though it is not limited thereto, wherein contacting on the lower surface of carrier structure (with the semiconductor crystal wafer facing surfaces) is not to be located immediately under the semiconductor crystal wafer, but is configured in the periphery of wafer.This exemplary die can be DRAM wafer (being dynamic random access memory), and the conducting sphere/sphere that wherein is configured on the lower surface of carrier structure is not located immediately under the wafer.
Though with reference to specific embodiment the present invention is illustrated and the details shown in the present invention is not limited to is described at this.On the contrary, in the scope and boundary of claim, and do not depart under the prerequisite of essence of the present invention, can do various modifications the present invention.

Claims (14)

1, a kind of method of processing semiconductor device, described method comprises the following steps:
The semiconductor device of being supported by carrier structure is provided, and this carrier structure limits a plurality of via holes from the first surface of this carrier structure adjacent with described semiconductor device to the second surface of this carrier structure;
Conductor extension is passed a described via hole, make first end of this conductor extend at least in part under this second surface, wherein these a plurality of via holes that limited by this carrier structure were limited before this extension step in advance;
After this extends step, at first end formation free air balls of described conductor;
Described free air balls is pulled at least in part with described second surface contacts; And
Another part of this conductor is electrically connected with the part of this semiconductor device.
2, the method for claim 1, wherein described pulling step heats described free air balls during being included in this pulling step.
3, the method for claim 1, wherein described electrical connection step comprises that the second end lead with described conductor joins on the contact mat of described semiconductor device.
4, the method for claim 1, wherein described pulling step comprises the part fusing of the described carrier structure that will contact with described free air balls, makes described free air balls be fixed on the described carrier structure.
5, the method for claim 1, wherein described pulling step comprises described free air balls and described carrier structure bonding connection.
6, the method for claim 1, wherein, described pulling step comprises described free air balls is pulled in the aperture adjacent with described second surface one at least in part, this aperture adjacent with described second surface is wedge shape, and locates described free air balls and described carrier structure bonding connection in described wedge shape aperture.
7, method as claimed in claim 3 further comprises following step:
Another conductor extension is passed another described via hole, make first end of described another conductor extend at least in part under the described second surface;
After described extension step, form another free air balls at described first end of described another conductor, and described another free air balls is pulled at least in part with described second surface contacts; And
Join the second end lead of described another conductor the part of described semiconductor device to, make the conductor loop that in second end to described another conductor carries out step that lead engages, forms be located at least in part on another conductor loop that second end to described conductor carries out forming in the step that lead engages.
8, method as claimed in claim 3 further comprises following step: described semiconductor device of encapsulation and described conductor after described electrical connection step.
9, the method for claim 1 wherein saidly provides step to be included in a plurality of described semiconductor device are provided on the described carrier structure, and further is included in the step that described carrier structure is separated into after the described electrical connection step a plurality of semiconductor device.
10, the method for claim 1, wherein this provides step by the semiconductor device of carrier structure support to comprise provides this carrier structure to limit these a plurality of via holes so that these via holes are tapered to this second surface from this first surface.
11, method as claimed in claim 10, wherein this provides step by the semiconductor device of carrier structure support to comprise provides this carrier structure to limit these a plurality of via holes so that these via holes have bigger opening having smaller opening on the second surface on this first surface.
12, a kind of method of processing semiconductor device said method comprising the steps of:
The semiconductor device of being supported by carrier structure is provided, and this carrier structure limits a plurality of via holes from the first surface of the carrier structure adjacent with described semiconductor device to the second surface of described carrier structure;
One template is provided, and it limits a plurality of grooves on the first surface of this template;
Conducting sphere is placed in the described groove at least in part;
On described template, aim at described semiconductor device, make at least a portion of described a plurality of via holes aim at each some described conducting spheres;
The first end lead of conductor is joined on the described conducting sphere; And
The second end lead of described conductor is joined on the part of described semiconductor device.
13, method as claimed in claim 12 further is included in after lead engages first end and lead and engage the step of second end, encapsulates the step of at least a portion of described semiconductor device and described conductor.
14, method as claimed in claim 13 further comprises the semiconductor device after the described encapsulation is separated from described template together with described carrier structure and conducting sphere, so that the step of the semiconductor device after the assembling to be provided.
CNB2005800147664A 2004-05-12 2005-05-10 Integrated ball and via package and formation process Expired - Fee Related CN100447966C (en)

Applications Claiming Priority (3)

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US57070404P 2004-05-12 2004-05-12
US60/570,704 2004-05-12
US60/660,486 2005-03-09

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Citations (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US20020027265A1 (en) * 1995-11-08 2002-03-07 Fujitsu Limited Semiconductor device, method for fabricating the semiconductor device, lead frame and method for producing the lead frame
CN1359154A (en) * 2000-10-10 2002-07-17 株式会社东芝 Semiconductor device
CN1492498A (en) * 1995-11-29 2004-04-28 ������������ʽ���� Semiconductor device

Patent Citations (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US20020027265A1 (en) * 1995-11-08 2002-03-07 Fujitsu Limited Semiconductor device, method for fabricating the semiconductor device, lead frame and method for producing the lead frame
CN1492498A (en) * 1995-11-29 2004-04-28 ������������ʽ���� Semiconductor device
CN1359154A (en) * 2000-10-10 2002-07-17 株式会社东芝 Semiconductor device

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