CN100447642C - Pixel structure and its making method - Google Patents
Pixel structure and its making method Download PDFInfo
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- CN100447642C CN100447642C CNB2004100314397A CN200410031439A CN100447642C CN 100447642 C CN100447642 C CN 100447642C CN B2004100314397 A CNB2004100314397 A CN B2004100314397A CN 200410031439 A CN200410031439 A CN 200410031439A CN 100447642 C CN100447642 C CN 100447642C
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- 238000000034 method Methods 0.000 title claims abstract description 26
- 230000008878 coupling Effects 0.000 claims abstract description 32
- 238000010168 coupling process Methods 0.000 claims abstract description 32
- 238000005859 coupling reaction Methods 0.000 claims abstract description 32
- 239000003990 capacitor Substances 0.000 claims abstract description 27
- 230000015572 biosynthetic process Effects 0.000 claims abstract 2
- 239000012212 insulator Substances 0.000 claims description 37
- 230000001681 protective effect Effects 0.000 claims description 36
- 239000000758 substrate Substances 0.000 claims description 31
- 239000010409 thin film Substances 0.000 claims description 31
- 238000003860 storage Methods 0.000 claims description 24
- 230000008569 process Effects 0.000 claims description 8
- 238000005530 etching Methods 0.000 abstract description 9
- 238000004519 manufacturing process Methods 0.000 abstract description 6
- 238000009413 insulation Methods 0.000 abstract 1
- 229910052751 metal Inorganic materials 0.000 description 16
- 239000002184 metal Substances 0.000 description 16
- 239000000463 material Substances 0.000 description 6
- 229910021417 amorphous silicon Inorganic materials 0.000 description 4
- 229910052581 Si3N4 Inorganic materials 0.000 description 2
- RTAQQCXQSZGOHL-UHFFFAOYSA-N Titanium Chemical compound [Ti] RTAQQCXQSZGOHL-UHFFFAOYSA-N 0.000 description 2
- 239000004411 aluminium Substances 0.000 description 2
- 229910052782 aluminium Inorganic materials 0.000 description 2
- XAGFODPZIPBFFR-UHFFFAOYSA-N aluminium Chemical compound [Al] XAGFODPZIPBFFR-UHFFFAOYSA-N 0.000 description 2
- 238000000149 argon plasma sintering Methods 0.000 description 2
- 239000013078 crystal Substances 0.000 description 2
- 238000005516 engineering process Methods 0.000 description 2
- 230000003628 erosive effect Effects 0.000 description 2
- 239000010408 film Substances 0.000 description 2
- 239000004973 liquid crystal related substance Substances 0.000 description 2
- HQVNEWCFYHHQES-UHFFFAOYSA-N silicon nitride Chemical group N12[Si]34N5[Si]62N3[Si]51N64 HQVNEWCFYHHQES-UHFFFAOYSA-N 0.000 description 2
- 239000010936 titanium Substances 0.000 description 2
- 229910052719 titanium Inorganic materials 0.000 description 2
- 230000004888 barrier function Effects 0.000 description 1
- 230000008901 benefit Effects 0.000 description 1
- 230000008859 change Effects 0.000 description 1
- 239000004020 conductor Substances 0.000 description 1
- 239000011521 glass Substances 0.000 description 1
- 238000003475 lamination Methods 0.000 description 1
- 238000000059 patterning Methods 0.000 description 1
- 238000012797 qualification Methods 0.000 description 1
- 230000000452 restraining effect Effects 0.000 description 1
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Abstract
The present invention relates to a pixel structure and a manufacturing method thereof. When the method is used for forming a data line and a source electrode/drain electrode, a conductive layer is simultaneously formed. The formed conductive layer comprises a coupling part and a connecting part, wherein the coupling part is used as an upper electrode of a pixel reservoir capacitor; the connecting part connects the coupling part with the drain electrode; then, an opening of a touch window is limited above the connecting part in order that pixel electrodes in subsequent formation can be in electric contact with the connecting part of the conductive layer through the opening of the contact window, so the pixel electrodes, the conductive layer (including the coupling part) and the drain electrode can be in mutual electric conduction. Because the contact window of the present invention is not formed right above the pixel reservoir capacitor, although the etching treatment of the contact window is possible to etch through an insulation layer of the grid electrode, the pixel reservoir capacitor has no electric leakage.
Description
Technical field
The present invention relates to the dot structure and the manufacture method thereof of a kind of thin film transistor (TFT) array (Thin Film Transistor Array) substrate, and be particularly related to a kind of dot structure and manufacture method thereof that can prevent pixel storage capacitor device generation electric leakage.
Background technology
Thin Film Transistor-LCD mainly is made of thin-film transistor array base-plate, colorful filter array substrate and liquid crystal layer, and wherein thin-film transistor array base-plate is by a plurality of thin film transistor (TFT) and pixel electrodes (Pixel Electrode) of corresponding configuration with each thin film transistor (TFT) and constitute a plurality of dot structures with arrayed.And above-mentioned thin film transistor (TFT) comprises grid, channel layer, drain electrode and source electrode, and it is used as the on-off element of liquid crystal display.
Please refer to Fig. 1, it is for having the wherein schematic plan of a dot structure of thin-film transistor array base-plate now.This dot structure is configured on the substrate (not shown), and it comprises one scan line 102, a data line 104, a thin film transistor (TFT) 130, a pixel storage capacitor device 116 and a pixel electrode 112.
Wherein, thin film transistor (TFT) 130 comprises grid 106, channel layer 108 and source/drain 110a/110b, and grid 106 electrically connects with sweep trace 102, and source electrode 110a and data line 104 electrically connect, and drain electrode 110b electrically connects with pixel electrode 112 by contact hole 114.
In addition, pixel storage capacitor device 116 comprises lower electrode 118, upper electrode 120 and the capacitance dielectric layer between lower electrode 118 and upper electrode 120, and upper electrode 120 electrically connects with pixel electrode 112 by contact hole 122.Wherein, lower electrode 118 is a bridging line, and itself and sweep trace 102 and grid 106 are to belong to the first metal layer (M1) equally.And upper electrode 120 belongs to second metal level (M2) with data line 104 and source/drain 110a/110b.And between the first metal layer and second metal level, dispose a gate insulator (not shown), then be to dispose a protective seam (not shown) between second metal level and pixel electrode 112.
What is particularly worth mentioning is that, generally two edges at substrate can design the portion of terminal (not shown), in order to electrically connect with driving circuit, wherein portion of terminal is a part that belongs to the first metal layer (M1), and data line 104 extends to substrate edges with sweep trace 102 and all can electrically connect with portion of terminal.
In order to make portion of terminal expose out,, therefore the gate insulator and the protective seam of portion of terminal top all must be lost open so that it can electrically connect with driving circuit.Yet; for contact hole 114,122; but only need the protective seam erosion is opened; particularly for the contact hole on the pixel storage capacitor device 116 122; only can lose out the protective seam at this place; and the necessary gate insulator that keeps this place, to produce electric leakage between the upper and lower part electrode 118,120 of avoiding pixel storage capacitor device 116.Therefore, the etching step of protective seam and gate insulator is quite crucial for the film crystal pipe manufacturer and has the technology of difficulty.
In the prior art, in order to overcome the problems referred to above, a kind of method is that multiform becomes one deck amorphous silicon layer under contact hole, and it is limited when limiting the channel layer of thin film transistor (TFT) simultaneously.In other words, utilize amorphous silicon layer, to prevent that gate insulator under the contact hole is by eating thrown as the restraining barrier.Yet this kind method must be adjusted the etching selectivity between amorphous silicon and the gate insulator, is not to finish easily therefore.
Another kind of existing method is to form an opening earlier in the lower electrode under contact hole, meaning promptly will hollow out corresponding to the lower electrode place under the contact hole earlier, thus, even the gate insulator under the contact hole is opened by erosion, can not make yet and produce electric leakage between upper electrode and the lower electrode.But this kind method still has its shortcoming, and just prior to digging out in the lower electrode after the opening, follow-up contact window will the aligning with the opening in the lower electrode still has the problem that is difficult for of aiming at.
Summary of the invention
Therefore; purpose of the present invention just provides a kind of dot structure and manufacture method thereof; to solve the gate insulator in the film crystal pipe manufacturer and the etching step of protective seam in the prior art, the electric leakage problem of upper and lower part electrode generation of the pixel storage capacitor device of dot structure takes place easily.
The present invention proposes a kind of dot structure, and it comprises one scan line, a bridging line, a gate insulator, a data line, an on-off element (for example being a thin film transistor (TFT)), a conductive layer, a protective seam, a flatness layer, a contact hole and a pixel electrode.Wherein, sweep trace is configured on the substrate, and bridging line also is configured on the substrate, and bridging line and sweep trace configured in parallel, and bridging line is as the usefulness of the lower electrode of pixel storage capacitor device.Gate insulator is configured on the substrate, covers sweep trace and bridging line.Data line is configured on the gate insulator.In addition, on-off element is configured on the substrate, and this on-off element and sweep trace and data line electric connection.In addition, conductive layer is configured on the gate insulator, and this conductive layer has a coupling part and a junction, and wherein coupling part is in the top of bridging line, and it is as the usefulness of the upper electrode of pixel storage capacitor device, and connecting portion couples together coupling part and on-off element.In a preferred embodiment, the connecting portion of conductive layer is the design of a multi-channel structure, it comprises and is used for the first that is connected with on-off element, be used for the second portion that is connected with coupling part, and the third part between first and second portion, third part is the design of multi-channel structure.Protective seam covers data line, on-off element and conductive layer, and flatness layer is configured on the protective seam.In addition, contact hole is configured in the flatness layer and protective seam on the connecting portion, and in a preferred embodiment, contact hole is configured in the flatness layer and protective seam on the passage in the multi-channel structure of connecting portion.And pixel electrode is configured on the surface of flatness layer, and wherein pixel electrode electrically connects with the connecting portion of conductive layer by contact hole.Because on-off element and conductive layer link together, pixel electrode again with the connecting portion electric connection of conductive layer, so just electrically conduct each other between pixel electrode, whole conductive layer (comprising coupling part) and the on-off element.
The present invention proposes a kind of one pixel structure process method again, the method at first on a substrate, form a grid, with the one scan line of grid electric connection and a bridging line parallel, the follow-up lower electrode of bridging line as a pixel storage capacitor device with sweep trace.Then, on substrate, form a gate insulator, cover gate, sweep trace and bridging line.Afterwards, on the gate insulator above the grid, form a channel layer.Subsequently, form a data line and a conductive layer on gate insulator, and form source on the channel layer simultaneously, wherein grid, channel layer, source/drain constitute a thin film transistor (TFT), and data line and source electrode electric connection.In addition, formed conductive layer has a coupling part and a junction, wherein coupling part is formed on the top of bridging line, and it is as the usefulness of the upper electrode of pixel storage capacitor device, and the connecting portion of conductive layer couples together the drain electrode of its coupling part and thin film transistor (TFT).In a preferred embodiment, the connecting portion of conductive layer is the design of a multi-channel structure, it comprises and being used for and the first that drains and be connected, be used for the second portion that is connected with coupling part, and the third part between first and second portion, third part is the design of multi-channel structure, and follow-up formed contact window then can expose a wherein passage of third part.Afterwards, above substrate, form a protective seam, cover data line, conductive layer and thin film transistor (TFT), and on protective seam, form a flatness layer.Then, form a contact window in flatness layer and protective seam, expose the connecting portion of conductive layer, in a preferred embodiment, formed contact window exposes a wherein passage of connecting portion.Subsequently, form a pixel electrode on the surface of flatness layer, wherein pixel electrode electrically connects with the connecting portion of conductive layer by contact window.Because drain electrode links together with conductive layer, pixel electrode electrically connects with conductive layer again, so just electrically conducts each other between pixel electrode, conductive layer and the drain electrode.
Because between the upper electrode of its pixel electrode of dot structure of the present invention and drain electrode and pixel storage capacitor device, be to see through an identical contact hole to electrically connect, therefore dot structure of the present invention is a kind of design that is different from existing dot structure.
Because its contact hole of dot structure of the present invention is not the top that is arranged on the pixel storage capacitor device; therefore; even the etching step of protective seam and gate insulator can be with the gate insulator eating thrown, also can not cause producing electric leakage between the upper and lower part electrode of pixel storage capacitor device.
Description of drawings
Fig. 1 is the schematic plan of the dot structure in the existing thin-film transistor array base-plate;
Fig. 2 is the schematic plan according to the dot structure in the thin-film transistor array base-plate of one embodiment of the present invention;
Fig. 3 is the schematic cross sectional views of Fig. 2 by I-I '; And
Fig. 4 is the vertical view of conductive layer among Fig. 2.
Embodiment
For above-mentioned and other purposes, feature and advantage of the present invention can be become apparent, a preferred embodiment cited below particularly, and cooperate appended graphicly, be described in detail below.
Please refer to Fig. 2 and Fig. 3, Fig. 2 is the vertical view according to the dot structure in a kind of thin-film transistor array base-plate of one embodiment of the present invention, and Fig. 3 is by the schematic cross sectional views of I-I ' among Fig. 2.One pixel structure process method of the present invention at first provides a substrate 200, and wherein substrate 200 for example is a glass substrate or a plastic base.Afterwards, on substrate 200, form a grid 206, with the one scan line 202 of grid 206 electric connections and a bridging line 218 parallel, the bridging line 218 follow-up lower electrodes that are used as pixel storage capacitor device 216 with sweep trace 202.And grid 206, sweep trace 202 and bridging line 218 belong to the first metal layer (M1).
At this, the first metal layer also comprises a plurality of portion of terminal (not shown), and it is formed on two edges of substrate 200, and above-mentioned formed sweep trace 202 and follow-up formed data line, its edge that extends to substrate 200 all can electrically connect with portion of terminal.
Then, on substrate 200, form a gate insulator 205, cover the first metal layer (comprising grid 206, sweep trace 202 and bridging line 218).In a preferred embodiment, the material of gate insulator 205 for example is silicon nitride or monox.
Afterwards, on the gate insulator above the grid 206 205, form a channel layer 208.In a preferred embodiment, the material of channel layer 208 for example is an amorphous silicon, and on the surface of channel layer 208, also is formed with an ohmic contact layer (not shown), in order to improve electrical contact the between channel layer 208 and the follow-up formed source/drain.
Subsequently, on gate insulator 205, form a data line 204 and a conductive layer 250 (as shown in Figure 4), and form source/drain 210a/210b simultaneously on channel layer 208, data line 204, conductive layer 250 belong to second metal level (M2) with source/drain 210a/210b.Wherein, source electrode 210a and data line 204 electrically connect, and grid 206, channel layer 208 and source/drain 210a/210b constitute a thin film transistor (TFT).
Above-mentioned formed conductive layer 250 has a coupling part 220 and a junction 240, wherein coupling part 220 is formed on the top of bridging line 218, it is as the upper electrode of pixel storage capacitor device 216, and connecting portion 240 couples together coupling part 220 with drain electrode 210b.
Particularly, in a preferred embodiment, the connecting portion 240 of conductive layer 250 more can be defined as multichannel structure, as shown in Figure 4, connecting portion 240 comprises the 226a of first that is connected with drain electrode 210b, the second portion 226b that is connected with coupling part 220, and the third part 224 between 226a of first and second portion 226b, third part 224 is a multi-channel structure, and three passage 224a, 224b, 224c are that example explains shown in the figure, but is not in order to limit the present invention.The purpose of making this kind multi-channel structure is follow-uply can be limited at the wherein top of a passage when limiting contact window, for example is the top that is limited at center-aisle 224b.Other passage 224a, 224c then is the task of serving as the conduction carrier, if when a passage (for example being passage 224a) wherein being arranged because of manufacturing factor or other factors can't conducting the time, its remaining passage (for example being 224c) then can continue to shoulder the task of conduction carrier, and can can't not operate because of above-mentioned reason just makes whole dot structure.
What is particularly worth mentioning is that, the beneath light shield layer 222 that more can form in the third part 224 of connecting portion 240, this light shield layer 222 belongs to the part of the first metal layer, and in other words, light shield layer 222 is formerly limited when limiting grid 206, sweep trace 202 with bridging line 218 simultaneously.The purpose that forms light shield layer 222 herein is to be used for that the follow-up Fang Yin thereon of shield is formed with contact hole and the light scattering phenomenon that can cause.
Forming second metal level (comprising data line 204, conductive layer 250 and source/drain 210a/210b) afterwards, above substrate 200, form a protective seam 211, cover second metal level, wherein the material of protective seam 211 for example is silicon nitride or monox.Subsequently, form a flatness layer 213 on protective seam 211, wherein the material of flatness layer 213 for example is the organic photo material.
Afterwards, patterning flatness layer 213 and protective seam 211 to form a contact window 228 in flatness layer 213 and protective seam 211, expose the part of the connecting portion 240 of conductive layer 250.In a preferred embodiment, contact window 228 exposes a wherein passage 224b of connecting portion 240.At this, if second metal level is to use titanium/aluminium double-level-metal layer as its material, then in the etching process that limits contact window 228, may be with the appropriate to the occasion aluminium lamination of removing passage 224b upper strata, and stay the titanium layer of lower floor, so the thickness of passage 224b is obviously little than passage 224a, 224c thickness among Fig. 3.
What is particularly worth mentioning is that, since contact window 228 of the present invention be not be limited at pixel storage capacitor device 216 directly over, therefore, also can not cause between the upper and lower part electrode 218,220 of pixel storage capacitor device 216 and produce electric leakage even can be in the etching step that limits contact window 228 with gate insulator 205 eating throwns.And if this etching step can be with gate insulator 205 eating throwns, but because what disposed under the contact window 228 is light shield layer 222, therefore it still can not have bad influence to whole element for the rete of electric connection is not arranged with other conductive material layers.
Afterwards, form a pixel electrode 212 on the surface of flatness layer 213, wherein pixel electrode 212 electrically connects with the connecting portion 240 (being passage 224b) of conductive layer 250 by contact window 228.
And owing to link together by connecting portion 240 between the drain electrode 210b of the coupling part 220 of conductive layer 250 and thin film transistor (TFT) 230, and pixel electrode 212 electrically connects with connecting portion 240 again, so just electrically conducts each other between the drain electrode 210b of pixel electrode 212, conductive layer 250 (comprising coupling part 220 and connecting portion 240) and thin film transistor (TFT) 230.
Dot structure of the present invention comprises one scan line 202, a bridging line 218, a gate insulator 205, a data line 204, an on-off element 230 (for example being thin film transistor (TFT)), a conductive layer 250, a protective seam 211, a flatness layer 213, a contact hole 228 and a pixel electrode 212.
Wherein, sweep trace 202 is configured on the substrate 200, and bridging line 218 also is configured on the substrate 200, and it is as the lower electrode of pixel storage capacitor device 216, and bridging line 218 and sweep trace 202 configured in parallel.
Gate insulator 205 is configured on the substrate 200, covers sweep trace 202 and bridging line 218.Data line 204 is configured on the gate insulator 205.
In addition, on-off element 230 for example is a thin film transistor (TFT), it is configured on the substrate 200, this thin film transistor (TFT) 230 has a grid 206, a channel layer 208 and source 210a/210b, wherein grid 206 electrically connects with sweep trace 202, channel layer 208 is configured on the gate insulator 205 of grid 206 tops, and source/drain 210a/210b is configured on the channel layer 208, and source electrode 210a and data line 204 electrically connect.
In addition, conductive layer 250 is configured on the gate insulator 205, this conductive layer 250 has a coupling part 220 and a junction 240, wherein coupling part 220 is positioned at the top of bridging line 218, it is as the upper electrode of pixel storage capacitor device 216, and connecting portion 240 couples together the drain electrode 210b of coupling part 220 with thin film transistor (TFT) 230.In preferred embodiment shown in Figure 4, the connecting portion 240 of conductive layer 250 for example is a multi-channel structure, connecting portion 240 comprises the 226a of first that is connected with drain electrode 210b, the second portion 226b that is connected with coupling part 220, and the third part 224 of position between 226a of first and second portion 226b, third part 224 is the design of multi-channel structure.And, the beneath light shield layer 222 that more disposes in third part 224 parts of connecting portion 240, this light shield layer 222 is to belong to the first metal layer with grid 206, sweep trace 202 and bridging line 218 equally, and light shield layer 222 is used for that the follow-up Fang Yin thereon of shield is formed with contact hole and the light scattering phenomenon that can cause.
Moreover protective seam 211 covers data line 204, thin film transistor (TFT) 230 and conductive layer 250.In addition, flatness layer 213 is configured on the protective seam 211.
And contact hole 228 is configured in the flatness layer 213 and protective seam 211 of connecting portion 240 tops, and the connecting portion 240 of contact hole 228 and conductive layer 250 electrically connects.In a preferred embodiment, contact hole 228 is configured in flatness layer 213 and the protective seam 211 of passage 224b top of connecting portion 240, and itself and the passage 224b electric connection of connecting portion 240.
Therefore, between the upper electrode of its pixel electrode of dot structure of the present invention and drain electrode and pixel storage capacitor device, be to see through an identical contact hole to electrically connect, therefore dot structure of the present invention is a kind of design that is different from existing dot structure.
In addition; because the contact hole of dot structure of the present invention is not the top that is arranged on the pixel storage capacitor device; therefore, even the etching step of protective seam and gate insulator can be with the gate insulator eating thrown, also can not cause producing electric leakage between the upper and lower part electrode of pixel storage capacitor device.
Though the present invention discloses as above with preferred embodiment; right its is not in order to qualification the present invention, those of ordinary skill in the art, without departing from the spirit and scope of the present invention; when can doing a little change and retouching, so protection scope of the present invention is as the criterion when looking claims person of defining.
Claims (10)
1. dot structure comprises:
The one scan line is configured on the substrate;
One bridging line is configured on this substrate, and it is as the lower electrode of a pixel storage capacitor device;
One gate insulator is configured on this substrate, covers this sweep trace and this bridging line;
One data line is configured on this gate insulator;
One on-off element is configured on this substrate, and wherein this on-off element and this sweep trace and this data line electrically connect;
One conductive layer, be configured on this gate insulator, wherein this conductive layer has a coupling part and a junction, and this coupling part is in the top of this bridging line, it is as the upper electrode of this pixel storage capacitor device, and this connecting portion couples together this coupling part and this on-off element;
One protective seam covers this data line, this on-off element and this conductive layer;
One contact hole is configured in this protective seam of this connecting portion top; And
One pixel electrode is configured on this protective seam, and wherein this pixel electrode electrically connects with this coupling part of this on-off element and this conductive layer by this contact hole;
It is characterized in that this connecting portion of this conductive layer is a multi-channel structure, it comprises:
One first, it is connected with this coupling part;
One second portion, it is connected with this on-off element; And
One third part, between this first and this second portion, and this third part has a plurality of passages;
Wherein, this contact hole is configured in this protective seam of a described passage top in this third part, and electrically connects with this passage.
2. dot structure as claimed in claim 1 is characterized in that, under this connecting portion that disposes this contact hole place, also disposes a light shield layer.
3. dot structure as claimed in claim 1 is characterized in that, between this protective seam and this pixel electrode, also disposes a flatness layer.
4. dot structure as claimed in claim 1 is characterized in that this on-off element is a thin film transistor (TFT), and it comprises:
One grid, this grid and this sweep trace electrically connect;
One channel layer, this channel layer are configured on this gate insulator of this grid top; And
An one source pole and a drain electrode, this source electrode and drain configuration are on this channel layer, and this source electrode and the electric connection of this data line, and this drain electrode is connected with this connecting portion of this conductive layer.
5. dot structure as claimed in claim 1 is characterized in that, this sweep trace and this bridging line configured in parallel.
6. one pixel structure process method comprises:
The one scan line and the bridging line that on a substrate, form a grid, electrically connect with this grid;
On this substrate, form a gate insulator, cover this grid, this sweep trace and this bridging line;
On this gate insulator above this grid, form a channel layer;
On this gate insulator, form a data line and a conductive layer, and on this channel layer, form an one source pole and a drain electrode simultaneously, wherein this data line and this source electrode electrically connect, and this conductive layer has a coupling part and a junction, this coupling part is formed on the top of this bridging line, this connecting portion couples together this coupling part and this drain electrode, and this grid, channel layer, source electrode and drain electrode constitute a thin film transistor (TFT);
Above this substrate, form a protective seam, cover this data line, this conductive layer and this thin film transistor (TFT);
In this protective seam, form a contact window, expose this connecting portion of this conductive layer; And
Form a pixel electrode on this protective seam, wherein this pixel electrode electrically connects with this conductive layer by this contact window;
It is characterized in that this connecting portion of this conductive layer is a multi-channel structure, it comprises:
One first, it is connected with this coupling part;
One second portion, it is connected with this thin film transistor (TFT); And
One third part, between this first and this second portion, and this third part has a plurality of passages;
Wherein, this contact hole is configured in this protective seam of a described passage top in this third part, and electrically connects with this passage.
7. one pixel structure process method as claimed in claim 6 is characterized in that, under this connecting portion under this contact hole, also is formed with a light shield layer.
8. one pixel structure process method as claimed in claim 7 is characterized in that, this light shield layer is institute's part of formation simultaneously when forming this grid, this sweep trace and this bridging line.
9. one pixel structure process method as claimed in claim 6 is characterized in that, before forming this pixel electrode, also forms a flatness layer on this protective seam.
10. one pixel structure process method as claimed in claim 6 is characterized in that, formed this bridging line is parallel with this sweep trace.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CNB2004100314397A CN100447642C (en) | 2004-03-29 | 2004-03-29 | Pixel structure and its making method |
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| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CNB2004100314397A CN100447642C (en) | 2004-03-29 | 2004-03-29 | Pixel structure and its making method |
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| CN1677202A CN1677202A (en) | 2005-10-05 |
| CN100447642C true CN100447642C (en) | 2008-12-31 |
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| CNB2004100314397A Expired - Fee Related CN100447642C (en) | 2004-03-29 | 2004-03-29 | Pixel structure and its making method |
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Families Citing this family (3)
| Publication number | Priority date | Publication date | Assignee | Title |
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| TWI453835B (en) | 2012-01-11 | 2014-09-21 | Chunghwa Picture Tubes Ltd | Pixel structure and manufacturing method thereof |
| CN102543996B (en) * | 2012-02-10 | 2014-06-04 | 福建华映显示科技有限公司 | Pixel structure and manufacturing method thereof |
| CN111240084B (en) * | 2020-03-25 | 2022-02-22 | 厦门天马微电子有限公司 | Display panel and display device |
Citations (5)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN1327167A (en) * | 2000-05-31 | 2001-12-19 | 夏普公司 | Liquid crystal display device and its fault correcting method |
| CN1338658A (en) * | 2000-08-10 | 2002-03-06 | 索尼株式会社 | Film semiconductor device and liquid crystal display unit and manufacture thereof |
| US20020149729A1 (en) * | 2001-02-28 | 2002-10-17 | Etsuko Nishimura | Liquid crystal display apparatus |
| CN1428836A (en) * | 2001-12-24 | 2003-07-09 | 矽统科技股份有限公司 | Integrated manufacture method of inner metal dielectric layer |
| CN2685925Y (en) * | 2004-03-29 | 2005-03-16 | 广辉电子股份有限公司 | Picture element struture |
-
2004
- 2004-03-29 CN CNB2004100314397A patent/CN100447642C/en not_active Expired - Fee Related
Patent Citations (5)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN1327167A (en) * | 2000-05-31 | 2001-12-19 | 夏普公司 | Liquid crystal display device and its fault correcting method |
| CN1338658A (en) * | 2000-08-10 | 2002-03-06 | 索尼株式会社 | Film semiconductor device and liquid crystal display unit and manufacture thereof |
| US20020149729A1 (en) * | 2001-02-28 | 2002-10-17 | Etsuko Nishimura | Liquid crystal display apparatus |
| CN1428836A (en) * | 2001-12-24 | 2003-07-09 | 矽统科技股份有限公司 | Integrated manufacture method of inner metal dielectric layer |
| CN2685925Y (en) * | 2004-03-29 | 2005-03-16 | 广辉电子股份有限公司 | Picture element struture |
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| CN1677202A (en) | 2005-10-05 |
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