CN1428836A - Integrated manufacture method of inner metal dielectric layer - Google Patents
Integrated manufacture method of inner metal dielectric layer Download PDFInfo
- Publication number
- CN1428836A CN1428836A CN 01144731 CN01144731A CN1428836A CN 1428836 A CN1428836 A CN 1428836A CN 01144731 CN01144731 CN 01144731 CN 01144731 A CN01144731 A CN 01144731A CN 1428836 A CN1428836 A CN 1428836A
- Authority
- CN
- China
- Prior art keywords
- layer
- insulating barrier
- metal dielectric
- inner metal
- layers
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
Images
Abstract
The integration making method of internal metal dielectric layer includes the following steps: providing a base on which several conductive stacked layers, every conductive stacked layer is formed from first metal layer and antireflection layer with multilayer structure. It adopts high-density electric slurry deposition process to form first insulating layer on the base, the thickness of the first insulating layer only has need of reaching that the gap between the conductive stacked layers is filled up, then form flat layer on the first insulating layer, the flat layer and first insulating layer are formed into an internal metal dielectric layer; form several dielectric hales in internal metal dielectric layer and conductive stacked layer, then form barrier layer on the conductive stacked layer and on the side wall of dielectric hole, and form inserting balt in dielectric hole, ther implement post metallization process.
Description
Technical field
The invention relates to a kind of manufacture method of semiconductor integrated circuit, particularly relevant for a kind of integrated manufacture method of inner metal dielectric layer.
Background technology
Integration increase when integrated circuit, when making the surface of chip can't provide enough areas to make required intraconnections (Interconnects), in order to cooperate the MOS electric crystal to dwindle the intraconnections demand that the back is increased, two-layer above metal level design just becomes the essential mode that adopts of integrated circuit.
Basically, the making of multi-metal intra-connection (Multilevel interconnects) is just to begin afterwards to carry out finishing the main body of assembly (for example MOS electric crystal).Mutually directly contact and be short-circuited (but have the place of connector except) must be isolated with insulator between each metal level for fear of each layer metal wire.This layer is called " inner metal dielectric layer " (Inter-Metal Dielectric in order to the dielectric material (Dielectrics) of isolating metal layer; Abbreviate IMD as).
At present in the semiconductor industry, no matter with regard to technology such as thin film deposition (insulating barrier, metal level etc.), planarization, etching interlayer hole, metallization and multiple internal connecting lines, have respectively each independently particular process be suggested.But,, do not have the people in the industry can propose a manufacturing process of highly integrating from forming inner metal dielectric layer up to finishing metallization.
Summary of the invention
The inventor through developmental research chronically, creates technical scheme of the present invention based on research of in the industry cycle being engaged in and practical experience.
The integrated manufacture method that the purpose of this invention is to provide a kind of inner metal dielectric layer, by with industry each independently technology give the height integration, the people in the industry is provided a kind of manufacturing process that can stablize running, integrate spent mental and physical efforts of each fabrication schedule and mistake voluntarily to reduce the people in the industry, reach the purpose of the production efficiency that promotes integral body, essence.
The object of the present invention is achieved like this: a kind of integrated manufacture method of inner metal dielectric layer is characterized in that: it comprises the steps:
(1) provide one to be formed with a majority laminated substrate of conduction dimension, each conduction stack of layers is made up of the first metal layer and the anti-reflecting layer with sandwich construction;
(2) use the high-density electric slurry sedimentation, form first insulating barrier on this substrate, the thickness of this first insulating barrier only need reach the gap of filling up between these conduction stack of layers and get final product;
(3) form a flatness layer on this first insulating barrier, this flatness layer and this first insulating barrier then constitute an inner metal dielectric layer;
(4) form most interlayer holes among this inner metal dielectric layer and these conduction stack of layers;
(5) formation of compliance ground has the barrier layer of one to multiple layer structure on these conduction stack of layers and on the sidewall of this interlayer hole;
(6) form plug in these interlayer holes;
(7) finish follow-up metallization process.
It in these interlayer holes the first metal layer that exposes these conduction stack of layers.In each this interlayer hole, be a specific aspect of exposing in the sandwich construction of this anti-reflecting layer.This anti-reflecting layer is to form Ti layer, TiN layer or SiON layer at least in regular turn on this first metal layer and get.In each these interlayer hole, be the TiN layer that exposes in this anti-reflecting layer.
The step that forms this flatness layer comprises: form second insulating barrier on this first insulating barrier, the thickness of this second insulating barrier is greater than the thickness of this first insulating barrier; This second insulating barrier is carried out planarization, and reduce the thickness of this second insulating barrier; Form the 3rd insulating barrier in this on second insulating barrier of planarization; By adjusting the thickness of the 3rd insulating barrier, make this flatness layer that this second, third insulating barrier constituted have a set thickness.
The step that forms this flatness layer comprises: form second insulating barrier on this first insulating barrier, the thickness of this second insulating barrier is greater than the thickness of this first insulating barrier; This second insulating barrier is carried out planarization, and reduce the set thickness of thickness to one of this second insulating barrier.This second insulating barrier is carried out planarization be to use chemical mechanical milling method.
The integrated manufacture method of another kind of inner metal dielectric layer, it is characterized in that: it comprises the steps:
(1) provide a substrate that is formed with most conduction stack of layers, each this conduction stack of layers is made up of the first metal layer and anti-reflecting layer with sandwich construction;
(2) form flatness layer on this substrate, in order to clog gap between these conduction stack of layers, and to cover this conduction stack of layers, this flatness layer is as an inner metal dielectric layer;
(3) form most interlayer holes among this inner metal dielectric layer and these conduction stack of layers;
(4) in forming to compliance barrier layer on these anti-reflecting layers and on the sidewall of these interlayer holes with one to multiple layer structure;
(5) form plug in this interlayer hole;
(6) finish follow-up metallization process.
It in these interlayer holes the first metal layer that exposes these conduction stack of layers.It in each these interlayer hole a specific aspect of exposing in the sandwich construction in this reflector.This anti-reflecting layer is to form Ti layer, TiN layer or SiON layer at least in regular turn on this first metal layer and get.It in each these interlayer hole the TiN layer that exposes in this anti-reflecting layer.
The step that forms this flatness layer comprises: form insulating barrier on this substrate; This insulating barrier is carried out planarization, and reduce the thickness of this insulating barrier; Form cover layer on this insulating barrier of planarization; By adjusting this tectal thickness, make this flatness layer that this insulating barrier and cover layer constituted have a set thickness.
The step that forms this flatness layer comprises: form insulating barrier in this substrate; This insulating barrier is carried out planarization, and reduce the set thickness of thickness to one of this insulating barrier.
In detail sharp bright below in conjunction with preferred embodiment and accompanying drawing.
Description of drawings
Fig. 1-Fig. 8 is the manufacturing process generalized section of the embodiment of the invention 1.
Fig. 9-Figure 12 is the manufacturing process generalized section of the embodiment of the invention 2.
Figure 13 is the partial structurtes enlarged diagram of Fig. 6 intermediary layer hole and conduction stack of layers.
Figure 14 is the partial structurtes enlarged diagram of Figure 10 intermediary layer hole and conduction stack of layers.
Figure 15-Figure 21 is the manufacturing process generalized section of the embodiment of the invention 3.
Figure 22-the 25th, the manufacturing process generalized section of the embodiment of the invention 4.
Embodiment
Embodiment 1
Consult Fig. 1-shown in Figure 8, manufacturing process of the present invention comprises the steps:
At first, as shown in Figure 1, provide a substrate 100 that is formed with most conduction dimensions laminated 102.Above-mentioned conduction stack of layers 102 is made up of anti-reflecting layer (multi-anti-reflecting layer) 102b that a first metal layer 102a and has sandwich construction.
In the present embodiment, the sandwich construction (not being shown among Fig. 1) that above-mentioned anti-reflecting layer 102b is had for example is to form Ti layer, TiN and SiON layer in regular turn to go up and get in above-mentioned the first metal layer 102a, but is not limited to above-mentioned sandwich construction.
Then, as shown in Figure 2, form one first insulating barrier 104 on above-mentioned substrate 100.Wherein, the thickness of above-mentioned first insulating barrier 104 only need reach and fill up above-mentioned conduction stack of layers 102 gap each other and get final product, in the present embodiment, and also simultaneously with above-mentioned conduction stack of layers 102 coverings.
In the present embodiment, above-mentioned first insulating barrier 104 is to use high density plasma enhanced chemical vapor deposition method (HDPCVD) to form to have the oxide layer of well filling out hole (gap fill) ability.
As shown in Figure 5, formation has the flatness layer 106 of set thickness (for example about 8000 ) on above-mentioned first insulating barrier 104.106 of above-mentioned flatness layers and the above-mentioned first insulating barrier IO4 constitute an inner metal dielectric layer;
Consult Fig. 3-shown in Figure 5, form the step of above-mentioned flatness layer 106, as described below:
(a) at first, as shown in Figure 3, form one second insulating barrier 106a on above-mentioned first insulating barrier 104; The thickness of the above-mentioned second insulating barrier 106a for example is not less than 8000 , and greater than the thickness of above-mentioned first insulating barrier 104.In the present embodiment, the above-mentioned second insulating barrier 106a is for example for using oxide layer that the PECVD method deposited or TEOS layer etc.
(b) then, as shown in Figure 4, for example use chemical mechanical milling method (CMP), the above-mentioned second insulating barrier 106a is carried out planarization, and reduce the thickness of the above-mentioned second insulating barrier 106a; The thickness of the second insulating barrier 106a after planarization for example is to be reduced to about 5000-6000 .
(c) last, as shown in Figure 5, cover again (recap) one the 3rd insulating barrier 106b in above-mentioned on the second insulating barrier 106a of planarization, and obtain above-mentioned flatness layer 106; By adjusting the thickness of above-mentioned the 3rd insulating barrier 106b, the above-mentioned flatness layer 106 that makes above-mentioned second, third insulating barrier (106a, 106b) be constituted reaches above-mentioned set thickness (that is 8000 ).Be that to make the thickness of above-mentioned the 3rd insulating barrier 106b be 3000-2000 in the present embodiment; The 3rd insulating barrier 106b for example is an oxide layer.
Above-mentioned flatness layer 106 is made of second and third insulating barrier (106a, 106b), but be not to be defined in this, as shown in Figure 9, can also directly form the have set thickness single flatness layer 306 of (for example about 8000 ) on above-mentioned first insulating barrier 104, so that constitute an inner metal dielectric layer with above-mentioned first insulating barrier 104.
Consult Fig. 3 and shown in Figure 9, the step that forms above-mentioned single flatness layer 306 is as follows:
(a) at first, as shown in Figure 3, form one second insulating barrier 106a on above-mentioned first insulating barrier 104; The thickness of the above-mentioned second insulating barrier 106a, for example greater than 8000 , and greater than the thickness of above-mentioned first insulating barrier 104.In the present embodiment, the above-mentioned first insulating barrier 106a is for example for using oxide layer that the PECVD method deposited or TEOS layer etc.
(b) then, as shown in Figure 9, re-use the CMP method, the above-mentioned first insulating barrier 106a is carried out planarization, and the thickness of the above-mentioned second insulating barrier 106a directly is reduced to 8000 , and get above-mentioned single flatness layer 306;
Then, at above-mentioned inner metal dielectric layer (shown in Figure 5 106 and 104; Or shown in Figure 9 306 and 104) in, and among the above-mentioned conduction stack of layers 102, form most interlayer holes (via) 108, as Fig. 6 and shown in Figure 10.
Required according to what use, optionally allow the certain layer in the sandwich construction of this anti-reflecting layer 102b show in these interlayer holes 108; Can also select to allow the first metal layer 102a of these conduction stack of layers be exposed in these interlayer holes 108.
Figure 13 is the partial structurtes enlarged diagram of Fig. 6 intermediary layer hole 108 and conduction stack of layers 102.Figure 14 is the partial structurtes enlarged diagram of Figure 10 intermediary layer hole 108 and conduction stack of layers 102.
With Fig. 6 structure is example, is to select to allow a specific aspect in the sandwich construction of this anti-reflecting layer 102b, be exposed in this interlayer hole 108 (but be not limited to this, also can select this first metal layer 102a is exposed to interlayer hole 108).In other words, when etching formed interlayer hole 108, etching program was to end in the TiN layer of this anti-reflecting layer 102b, makes the TiN layer be exposed in the interlayer hole 108; As shown in figure 13.
Embodiment 2
Consulting Fig. 9-shown in Figure 12, is example with Figure 10 structure, is to select to allow the first metal layer 102a of conduction stack of layers, be exposed in this interlayer hole 108 (but be not limited to this, also can select the TiN layer of this anti-reflecting layer 102b is exposed to interlayer hole 108).In other words, when etching formed interlayer hole 108, etching program was to end among this first metal layer 102a, makes the first metal layer 102a be exposed in the interlayer hole 108, as shown in figure 14.
Then, compliance ground (conformally) forms a barrier layer 110 with sandwich construction on the sidewall of (also or on the above-mentioned the first metal layer 102a), above-mentioned interlayer hole 108 on the TiN of the above-mentioned reflector 102b layer and on the above-mentioned flatness layer 106.
Deposit a metal level (for example tungsten metal level) again and add on the above-mentioned barrier layer 110, and fill up above-mentioned interlayer hole 108; Re-use the CMP method and grind up to exposing above-mentioned flatness layer 106, and form connector (plug) 112 in above-mentioned interlayer hole 108, as Fig. 7 and shown in Figure 11.
At last, form most metallization stack of layers and electrically contact, and finish metallization process, as Fig. 8 and shown in Figure 12 with above-mentioned connector 112 formations.
Each above-mentioned metallization stack of layers comprises: adhesion coating 114, one metal levels 116 and with sandwich construction have the anti-reflecting layer 118 of sandwich construction.
Embodiment 3
Consult Figure 15-shown in Figure 21.The manufacturing process of present embodiment is as follows:
At first, provide a substrate 100 that is formed with most conduction stack of layers 102 wherein, above-mentioned conduction stack of layers 102 is made up of the anti-reflecting layer 102b that a first metal layer 102a and has sandwich construction, as shown in figure 15.
In the present embodiment, the sandwich construction (not being shown among Figure 15) that above-mentioned anti-reflecting layer 102b is had for example is to form Ti layer, TiN layer and SiON layer in regular turn to go up and get in above-mentioned the first metal layer 102a, but is not limited to above-mentioned sandwich construction.
Then, formation has the flatness layer 506 of set thickness (for example about 8000 ) on above-mentioned substrate 100, as an inner metal dielectric layer, as shown in figure 18.
Consult Figure 16-shown in Figure 180, form the step of above-mentioned flatness layer 506, comprise the steps:
(a) at first, form an insulating barrier 506a in above-mentioned substrate 100, as shown in figure 16.Above-mentioned insulating barrier is in order to the gap of clogging 102 of this conduction stack of layers and cover these conduction stack of layers 102.The thickness of this insulating barrier 506a is for example greater than 8000 .In the present embodiment, above-mentioned insulating barrier 506a, for example by use to use high density plasma enhanced chemical vapor deposition method (HDPCVD) formation have the oxide layer of well filling out the hole ability.
(b) then, re-use the CMP method, 506a carries out planarization to this insulating barrier, and reduces the thickness of above-mentioned insulating barrier 506a, as shown in figure 17.At this, the thickness of insulating barrier 506a after planarization for example is to be reduced to about 5000-6000 .
(c) last, form a cover layer 506b in above-mentioned on the insulating barrier 506a of planarization, and obtain above-mentioned flatness layer 506, as shown in figure 18.At this,, make above-mentioned flatness layer 506 reach above-mentioned set thickness (that is 8000 ) by adjusting the thickness of above-mentioned cover layer 506b.In the present embodiment, be that to make the thickness of above-mentioned cover layer 506b be 3000-2000 , cover layer 506b for example is an oxide layer.
Above-mentioned flatness layer 506 is made of insulating barrier 506a and cover layer 506b, but is not to be defined in this.As shown in figure 22, can also directly be split into the have set thickness single flatness layer 706 of (for example about 8000 ) on above-mentioned substrate 100, and as inner metal dielectric layer.
Consult Figure 16 and shown in Figure 22, the step that forms above-mentioned single flatness layer 706 is as follows:
(a) at first, form insulating barrier 506a in above-mentioned substrate 100, as shown in figure 16.The thickness of the above-mentioned first insulating barrier 106a is for example greater than 8000 .
(b) then, re-use the CMP method, above-mentioned insulating barrier 506a is carried out planarization, and its thickness directly is reduced to 8000 , and get above-mentioned single flatness layer 706, as shown in figure 22.
Then, in above-mentioned inner metal dielectric layer (flatness layer 506 shown in Figure 180, or single flatness layer 706 shown in Figure 22), and among the above-mentioned conduction stack of layers 102, form most interlayer holes 108, as Figure 19 and shown in Figure 23.
Required according to what use, optionally allow the certain layer in the sandwich construction of this anti-reflecting layer 102b show in these interlayer holes 108; Can also select to allow the first metal layer 102a of these conduction stack of layers be exposed in this interlayer hole 108,
Figure 13 is the partial structurtes enlarged diagram of Figure 19 intermediary layer hole 108 and conduction stack of layers 102, and Figure 14 is the partial structurtes enlarged diagram of Figure 23 intermediary layer hole 108 and conduction stack of layers 102.
Structure shown in Figure 19 is an example, is to select to allow a specific aspect in the sandwich construction of this anti-reflecting layer 102b, be exposed in these interlayer holes 198 (but be not limited to this, also can select this first metal layer 102a is exposed to interlayer hole 108).In other words, when etching formed interlayer hole 108, etching program was to end in the TiN layer of this anti-reflecting layer 102b, makes the TiN layer be exposed in the interlayer hole 108, as shown in figure 13.
Embodiment 4
Consulting Figure 22-shown in Figure 25, is example with structure shown in Figure 23, is to select to allow the first metal layer 102a of conduction stack of layers, be exposed in these interlayer holes 108 (but be not limited to this, also can select the TiN layer of this anti-reflecting layer I02b is exposed to interlayer hole 108).In other words, when etching formed interlayer hole 108, etching program was to end among this first metal layer 102a, makes the first metal layer 102a be exposed in the interlayer hole 108, as shown in figure 14.
Then, compliance ground forms a barrier layer 110 with sandwich construction on the sidewall of (also or on the above-mentioned the first metal layer 102a), above-mentioned interlayer hole 108 on the TiN of the above-mentioned anti-reflecting layer 102b layer and on the above-mentioned flatness layer 106.
Deposit a metal level (for example tungsten metal level) again on above-mentioned barrier layer 110, and fill up above-mentioned interlayer hole 108; Re-use the CMP method and grind up to exposing above-mentioned flatness layer 106, and form connector 112 in above-mentioned interlayer hole 108, as Figure 20 and shown in Figure 24.
At last, form most metallization stack of layers and electrically contact, and finish metallization process, as Figure 21 and shown in Figure 25 with above-mentioned connector 112 formations.
Each above-mentioned metallization stack of layers comprises: adhesion coating 114, one metal levels 116 and with sandwich construction have the anti-reflecting layer 118 of sandwich construction.
In sum, in the present invention considers electricity belong to dielectric layer production capacity, fill out hole ability and interface features, industry people can be easily uses required integration processing procedure by selecting among the embodiment 1-4 meet most.
For example, for the preferable hole ability of filling out can be arranged, among the foregoing description 1-4, all there is the HDPCVD of use to form the HDP oxide layer, but the cost of HDPCVD board is high and speed of production is slow, therefore if when considering cost and speed of production, and then can be according to the processing procedure of embodiment 1,2, only form thin HDP oxide layer (first insulating barrier 104), its thickness only needs to reach conduction stack of layers 102 is filled up and got final product (shown in Figure 2) in the crack each other.Certainly, if the busy or whole inner metal dielectric layer of HDPCVD board is when being required to have compact texture, also can be as the processing procedure of embodiment 3,4, the direct thicker HDP oxide layer (insulating barrier 506a) of formation.
Be directly to use CMP that the first insulating barrier 106a (Fig. 3) is carried out planarization and obtains flatness layer 306 (Fig. 9) among the embodiment 2;
Also be directly to use CMP that insulating barrier 506a (Figure 16) is carried out planarization and obtains flatness layer 706 (Figure 22) among the embodiment 4.But, after CMP grinds, what can residually have chemical substances such as grinding slurry, dilute hydrofluoric acid in the surface of flatness layer 306,506, and pollute, so in follow-up metallization processes, can make that the interface features of metal level and flatness layer 306,506 is not good, may cause metal wire when suffering external force, have the phenomenon of peeling off easily and produce, thereby influence component characteristic.
Therefore, if the assembly of being produced wishes that above-mentioned interface problem is had preferable immunocompetence, then can use embodiment 1,3 described processing procedures, that is after finishing the CMP processing procedure, cover the 3rd insulating barrier 106b (Fig. 5), cover layer 506b (Figure 18) in addition again, so that isolated by CMP processing procedure surfaces contaminated.In addition, the mode according to embodiment 1,3 also can have preferable control for flatness layer thickness.
Be noted that: among the foregoing description 1-4, when etching interlayer hole 108, optionally allow the specific aspect (for example TiN layer) in the sandwich construction of this anti-reflecting layer 102b be exposed in these interlayer holes 108 (as shown in figure 13); Or select to allow the first metal layer 102a of these conduction stack of layers be exposed in these interlayer holes 108 (as shown in figure 14).
If according to shown in Figure 14, select to allow the first metal layer 102a be exposed in these interlayer holes 108, since more difficult to the control of interlayer hole 108 bottom profile, so what can cause the rising performance of metallization back (plug) resistance backward.Therefore, be strict with, then can adopt as shown in figure 13, allow the specific aspect (for example TiN layer) in the sandwich construction of this anti-reflecting layer 102b be exposed to these interlayer holes 108 if (plug) resistance performance after for metallization of the assembly of manufacturing has; Because preferable to the control of interlayer hole 108 bottom profile, so (plug) resistance after the metallization is lower.
Though the present invention discloses as above with preferred embodiment, so it is not in order to limiting the present invention, anyly is familiar with this skill person, and without departing from the spirit and scope of the present invention, a little change and the retouching done all belongs within protection scope of the present invention.
Claims (16)
1, a kind of integrated manufacture method of inner metal dielectric layer, it is characterized in that: it comprises the steps:
(1) provide one to be formed with a majority laminated substrate of conduction dimension, each conduction stack of layers is made up of the first metal layer and the anti-reflecting layer with sandwich construction;
(2) use the high-density electric slurry sedimentation, form first insulating barrier on this substrate, the thickness of this first insulating barrier only need reach the gap of filling up between these conduction stack of layers and get final product;
(3) form a flatness layer on this first insulating barrier, this flatness layer and this first insulating barrier then constitute an inner metal dielectric layer;
(4) form most interlayer holes among this inner metal dielectric layer and these conduction stack of layers;
(5) formation of compliance ground has the barrier layer of one to multiple layer structure on these conduction stack of layers and on the sidewall of this interlayer hole;
(6) form plug in these interlayer holes;
(7) finish follow-up metallization process.
2, the integrated manufacture method of inner metal dielectric layer according to claim 1 is characterized in that: be the first metal layer that exposes these conduction stack of layers in these interlayer holes.
3, the integrated manufacture method of inner metal dielectric layer according to claim 1 is characterized in that: in each this interlayer hole, be a specific aspect of exposing in the sandwich construction of this anti-reflecting layer.
4, the integrated manufacture method of inner metal dielectric layer according to claim 3 is characterized in that: this anti-reflecting layer is to form Ti layer, TiN layer or SiON layer at least in regular turn on this first metal layer and get.
5, the integrated manufacture method of inner metal dielectric layer according to claim 4 is characterized in that: in each these interlayer hole, be the TiN layer that exposes in this anti-reflecting layer.
6, the integrated manufacture method of inner metal dielectric layer according to claim 1 is characterized in that: the step that forms this flatness layer comprises:
Form second insulating barrier on this first insulating barrier, the thickness of this second insulating barrier is greater than the thickness of this first insulating barrier; This second insulating barrier is carried out planarization, and reduce the thickness of this second insulating barrier; Form the 3rd insulating barrier in this on second insulating barrier of planarization; By adjusting the thickness of the 3rd insulating barrier, make this flatness layer that this second, third insulating barrier constituted have a set thickness.
7, the integrated manufacture method of inner metal dielectric layer according to claim 1 is characterized in that: the step that forms this flatness layer comprises:
Form second insulating barrier on this first insulating barrier, the thickness of this second insulating barrier is greater than the thickness of this first insulating barrier; This second insulating barrier is carried out planarization, and reduce the set thickness of thickness to one of this second insulating barrier.
8, according to the integrated manufacture method of claim 6 or 7 described inner metal dielectric layers, it is characterized in that: this second insulating barrier is carried out planarization be to use chemical mechanical milling method.
9, a kind of integrated manufacture method of inner metal dielectric layer, it is characterized in that: it comprises the steps:
(1) provide a substrate that is formed with most conduction stack of layers, each this conduction stack of layers is made up of the first metal layer and anti-reflecting layer with sandwich construction;
(2) form flatness layer on this substrate, in order to clog gap between these conduction stack of layers, and to cover this conduction stack of layers, this flatness layer is as an inner metal dielectric layer;
(3) form most interlayer holes among this inner metal dielectric layer and these conduction stack of layers;
(4) in forming to compliance barrier layer on these anti-reflecting layers and on the sidewall of these interlayer holes with one to multiple layer structure;
(5) form plug in this interlayer hole;
(6) finish follow-up metallization process.
10, the integrated manufacture method of inner metal dielectric layer according to claim 9 is characterized in that: be the first metal layer that exposes these conduction stack of layers in these interlayer holes.
11, the integrated manufacture method of inner metal dielectric layer according to claim 9 is characterized in that: be a specific aspect of exposing in the sandwich construction in this reflector in each these interlayer hole.
12, the integrated manufacture method of inner metal dielectric layer according to claim 11 is characterized in that: this anti-reflecting layer is to form Ti layer, TiN layer or SiON layer at least in regular turn on this first metal layer and get.
13, the integrated manufacture method of inner metal dielectric layer according to claim 12 is characterized in that: be the TiN layer that exposes in this anti-reflecting layer in each these interlayer hole.
14, the integrated manufacture method of inner metal dielectric layer according to claim 9 is characterized in that: the step that forms this flatness layer comprises:
Form insulating barrier on this substrate; This insulating barrier is carried out planarization, and reduce the thickness of this insulating barrier; Form cover layer on this insulating barrier of planarization; By adjusting this tectal thickness, make this flatness layer that this insulating barrier and cover layer constituted have a set thickness.
15, the integrated manufacture method of inner metal dielectric layer according to claim 9 is characterized in that: the step that forms this flatness layer comprises:
Form insulating barrier in this substrate; This insulating barrier is carried out planarization, and reduce the set thickness of thickness to one of this insulating barrier.
16, according to the integrated manufacture method of claim 14 or 15 described inner metal dielectric layers, it is characterized in that: this insulating barrier is carried out planarization be to use chemical mechanical milling method.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN 01144731 CN1428836A (en) | 2001-12-24 | 2001-12-24 | Integrated manufacture method of inner metal dielectric layer |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN 01144731 CN1428836A (en) | 2001-12-24 | 2001-12-24 | Integrated manufacture method of inner metal dielectric layer |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| CN1428836A true CN1428836A (en) | 2003-07-09 |
Family
ID=4677795
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| CN 01144731 Pending CN1428836A (en) | 2001-12-24 | 2001-12-24 | Integrated manufacture method of inner metal dielectric layer |
Country Status (1)
| Country | Link |
|---|---|
| CN (1) | CN1428836A (en) |
Cited By (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US7268025B2 (en) | 2003-08-12 | 2007-09-11 | Au Optronics Corporation | Pixel structure and fabricating method thereof |
| CN100447642C (en) * | 2004-03-29 | 2008-12-31 | 友达光电股份有限公司 | Pixel structure and its making method |
| CN102867741A (en) * | 2011-07-03 | 2013-01-09 | 南亚科技股份有限公司 | Semiconductor process |
| CN104253052A (en) * | 2013-06-28 | 2014-12-31 | 华邦电子股份有限公司 | Metal interconnection structure and manufacturing method thereof |
-
2001
- 2001-12-24 CN CN 01144731 patent/CN1428836A/en active Pending
Cited By (6)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US7268025B2 (en) | 2003-08-12 | 2007-09-11 | Au Optronics Corporation | Pixel structure and fabricating method thereof |
| CN100447642C (en) * | 2004-03-29 | 2008-12-31 | 友达光电股份有限公司 | Pixel structure and its making method |
| CN102867741A (en) * | 2011-07-03 | 2013-01-09 | 南亚科技股份有限公司 | Semiconductor process |
| CN102867741B (en) * | 2011-07-03 | 2015-03-25 | 南亚科技股份有限公司 | Semiconductor manufacturing process |
| CN104253052A (en) * | 2013-06-28 | 2014-12-31 | 华邦电子股份有限公司 | Metal interconnection structure and manufacturing method thereof |
| CN104253052B (en) * | 2013-06-28 | 2017-12-15 | 华邦电子股份有限公司 | Metal interconnecting structure and its manufacture method |
Similar Documents
| Publication | Publication Date | Title |
|---|---|---|
| CN1197159C (en) | Semiconductor device with capactor and its producing method | |
| CN100345297C (en) | Embedded capacitor structure used for logic integrated cireuit | |
| CN101047209A (en) | Capacitor structure and multi-layer capacitor structure | |
| CN1211855C (en) | Conductive copper wire with redundant liner | |
| CN1930685A (en) | Method of making a semiconductor device, and semiconductor device made thereby | |
| CN1893020A (en) | Semiconductor device and a method of manufacturing the same | |
| CN1933153A (en) | Mim capacitor integrated into the damascene structure and method of making thereof | |
| CN1624917A (en) | Inductor device having improved quality factor | |
| CN1835235A (en) | Semiconductor device and mim capacitor | |
| CN1685475A (en) | MIM capacitor structures and fabrication methods in dual-damascene structures | |
| CN1722425A (en) | Semiconductor structure | |
| CN101064296A (en) | Semiconductor devices and fabrication method thereof | |
| CN1881558A (en) | Dual mosaic structure, interconnect structure and methods for fabricating the same | |
| CN1300850C (en) | Semiconductor device and method for fabricating the same | |
| CN1949502A (en) | Semiconductor device and integrated circuit device | |
| CN1750249A (en) | Semiconductor device in IC circuit and method for producing it | |
| CN1507055A (en) | Integrated circuit capacitor | |
| CN1062680C (en) | Fabrication method of semiconductor device | |
| CN1518093A (en) | Semiconductor device and its manufacturing method | |
| CN1635625A (en) | Method and structure for manufacturing high-capacitance capacitor by using copper | |
| CN1841733A (en) | Pyramid-shaped capacitor structure and its manufacturing method | |
| CN1428836A (en) | Integrated manufacture method of inner metal dielectric layer | |
| CN1917211A (en) | Dynamic random access memory, and manufacturing method | |
| CN1750265A (en) | Semiconductor device and method for fabricating the same | |
| CN1825561A (en) | Method of forming metal line in semiconductor device |
Legal Events
| Date | Code | Title | Description |
|---|---|---|---|
| C10 | Entry into substantive examination | ||
| SE01 | Entry into force of request for substantive examination | ||
| C06 | Publication | ||
| PB01 | Publication | ||
| C10 | Entry into substantive examination | ||
| SE01 | Entry into force of request for substantive examination | ||
| C02 | Deemed withdrawal of patent application after publication (patent law 2001) | ||
| WD01 | Invention patent application deemed withdrawn after publication |