CN100446443C - Optical burst-mode receiver - Google Patents
Optical burst-mode receiver Download PDFInfo
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- CN100446443C CN100446443C CNB2005100215358A CN200510021535A CN100446443C CN 100446443 C CN100446443 C CN 100446443C CN B2005100215358 A CNB2005100215358 A CN B2005100215358A CN 200510021535 A CN200510021535 A CN 200510021535A CN 100446443 C CN100446443 C CN 100446443C
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Abstract
The present invention provides an optical burst mode receiver which belongs to the field of optical communication technique. The present invention comprises a photodiode, a transimpedance preamplifier, a top and a bottom detecting circuits, a resistance potential divider and a limiting amplifier. The optical burst mode receiver is characterized in that the optical burst mode receiver also comprises a feed-forward type reset pulse signal generating circuit, a delay unit and a gate circuit, a charge capacitor in the top detecting circuit adopts a variable capacitor, and the feed-forward type reset pulse signal generating circuit comprises a limiting amplifier, an envelope pulse generating circuit and a reset pulse signal shaping circuit; the delay unit can shorten the required time of a protective band, so the utilization rate of information channels is improved; the variable capacitor solves one pair of conflicts existing in capacitors with fixed value that charge time is long when signals are large and detecting error is large when the signals are small, the utilization rate of the information channels is improved, and error codes are reduced; an output end adopts gate circuit technology, interference is eliminated, and meanwhile, complicated fast discharge circuits are avoided from being used in the optical burst mode receiver, so the performance/price ratio of the optical burst mode receiver is improved.
Description
Technical field
The invention belongs to the optical communication technique field, it is particularly related to the identification of light digital signal of burst mode light digital signal, inhomogeneous code stream (amplitude and block length inhomogeneous) and the burst mode optical receiver of reception.
Background technology
The optical fiber communication development in an all-round way also is deep into each utilization field, people are being conceived to study the key technology and the band optical fiber Access Network of optical fiber telecommunications system of future generation, make the main line of the existing high-speed wideband of fiber optic network, having fast and easily again, band optical fiber is linked into each user.EPON (PON, Passive Optical Network) have service transparency better, the signal applicable to any standard and speed, anti-electromagnetic interference and be easy to advantage such as maintenance, be a very potential emerging Optical Access Network technology.ATM Passive Optical Network (APON) and ethernet passive optical network (EPON) have successively appearred.No matter be APON, or the core of its physical layer Optical Fiber Transmission of EPON all being that transmission of up optical burst-mode and downlink broadcast transmit, is wherein emphasis and difficult point with up optical burst-mode receiver especially, and it will directly influence the speed and the bandwidth availability ratio of network.
Along with the maturation and the extensive use of DWDM optical transport technology and equipment, directly realize that at photosphere the demand of operation exchange is increasing, therefore, realize that full light exchange is considered to overcome the effective way of electric exchange rate bottleneck.(Optical Burst Switching, OBS) (Optical Packet Switching, OPS) technology is subjected to people's attention to the light burst-switched of Ti Chuing day by day with the light packet switching in recent years.The key technology of OBS and OPS system optical transport layer still is an optical burst-mode receiver, and it is directly connected to the speed and the bandwidth availability ratio of network.
Therefore, no matter based on the application of PON Access Network, still satisfy the demand of light switching technology OBS and OPS, all be necessary to research and develop the optical burst-mode receiver that can handle optical burst signal.Optical burst-mode receiver is exactly will have the optical receiver that the time of advent is uncertain and optical burst signal constant amplitudes amplitude characteristics inequality are recovered out without distortion.
As shown in Figure 1, the prominent pattern emitter/receiver of typical light is made up of photodiode, transimpedance preamplifier, top detection circuit, bottomside sounding circuit, resitstance voltage divider, limiting amplifier.Input optical signal is imported transimpedance amplifier after photodiode changes into current signal; The output voltage signal of transimpedance amplifier is divided into three the tunnel, the one tunnel and is input to the top detection circuit, and one the tunnel is input to the bottomside sounding circuit; Obtained the decision level of transimpedance amplifier output signal after the signal process resitstance voltage divider effect of the signal of top detection circuit output and the output of bottomside sounding circuit, other one tunnel output of it and transimpedance preamplifier is input to limiting amplifier together, and the output of limiting amplifier is required constant-amplitude signal.
This receiver when a burst packets arrives detection circuit, need charge to the electric capacity in the detection circuit when work; After this burst packets finishes, arrive before the next burst packets arrival, need a reseting pulse signal that the electric capacity in the detection circuit is discharged.Its reseting pulse signal of existing optical burst-mode receiver generally adds, in this case, need the software and hardware by a series of complexity produce reseting pulse signal in the gap of burst packets and to suitably controlling its resetting time, do like this and not only be difficult to control resetting time, and increased the complexity of receiving system greatly.Its top detection circuit of existing optical burst-mode receiver has used a definite value electric capacity to carry out top signal and has surveyed, charging interval detection error this a pair of contradiction greatly during long and small-signal makes higher channel utilization and smaller error not to get both when having large-signal.
Someone improves this optical burst-mode receiver, as shown in Figure 2, it is made up of (referring to document Quan Le photodiode, transimpedance preamplifier, top detection circuit, bottomside sounding circuit, resitstance voltage divider, limiting amplifier and reaction type reseting pulse signal generation circuit; Sang-Gug Lee; Yong-Hun Oh; Ho-Yong Kang; Tae-HwanYoo:A burst-mode receiver for 1.25-Gb/s ethernet PON with AGC and internally created resetsignal, IEEE, J.Solid-State Circuits, 2004,39 (12), pp.2379-2388).Be that with receiver difference shown in Figure 1 it is to produce circuit by the reaction type reseting pulse signal to produce reseting pulse signal automatically.The input signal that this reaction type reseting pulse signal produces circuit is the difference output of limiting amplifier, they obtain required reseting pulse signal after through two envelope detectors and comparator circuit and a series of gate circuit that is used for stable output, divide two-way with this reseting pulse signal then, one the tunnel feeds back to the top detection circuit, another road feeds back to the bottomside sounding circuit after anti-phase, in the gap of burst packets electric capacity is discharged.Yet this reaction type reseting pulse signal produces circuit and exists bigger defective: the one, and the signal demand of limiting amplifier output is input to and carries out the envelope detection in the envelope detector, makes required lead code time and boundary belt time understand corresponding increase; The 2nd, the input term signal of whole relatively receiver, the reaction type reseting pulse signal generation reseting pulse signal that circuit produced has the delay of certain hour, top detection circuit and bottomside sounding circuit need be waited for the arrival of reseting pulse signal, thereby make the time of boundary belt further increase, thereby reduced channel utilization; The 3rd, the width of the described reseting pulse signal of Fig. 2 is not suitably controlled, and the overshoot when making discharge is comparatively serious, has increased the time of lead code, thereby has further reduced channel utilization; The 4th, the reaction type reseting pulse signal produces circuit owing to introduced feedback mechanism, makes to be easy to generate vibration by the receiving circuit less stable.
Summary of the invention
The purpose of this invention is to provide a kind of optical burst-mode receiver; compare with similar receiver; have high reception sensitivity and bigger luminous power and receive dynamic range, less lead code time and less characteristics such as boundary belt time; need not add reseting pulse signal, cost lower, be fit to the demand for development in technology and market, and be easy to integrated or secondary integrated.
The content of the present invention of description for convenience, at first make term definition:
Lead code is meant recovering and phase locked distinct symbols for the data of light burst packets being carried out amplitude of being provided with in the front portion of each light burst packets.
Boundary belt is meant zone blanking time that exists between the adjacent light burst packets.
As shown in Figure 3, a kind of optical burst-mode receiver provided by the invention comprises photodiode 1, transimpedance preamplifier 2, top detection circuit 5, bottomside sounding circuit 6, resitstance voltage divider 7, limiting amplifier 8; It is characterized in that it also comprises: the feed forward type reseting pulse signal produces circuit 3, delay cell 4, gate circuit 9; Charging capacitor in the described top detection circuit 5 adopts variable capacitance; Described feed forward type reseting pulse signal produces circuit 3 and comprises limiting amplifier A2, a profiled pulses generation circuit, a reseting pulse signal forming circuit; The output of photodiode 1 is connected to the input of transimpedance preamplifier 2, and the output of transimpedance preamplifier 2 is connected respectively to the input of delay cell 4, top detection circuit 5 and bottomside sounding circuit 6; The output of top detection circuit 5 and bottomside sounding circuit 6 is connected respectively to two inputs of resitstance voltage divider 7, and the output of the output of resitstance voltage divider 7 and delay cell 4 is connected with two inputs of limiting amplifier 8 respectively; Two outputs of limiting amplifier 8 are connected respectively to two inputs of gate circuit, and two inputs in addition of gate circuit link to each other with the output that the feed forward type reseting pulse signal produces the profiled pulses generation circuit in the circuit 3; The feed forward type reseting pulse signal produces the opposite reseting pulse signal of phase place of the reseting pulse signal forming circuit output two-way certain width in the circuit 3, one the tunnel is fed to the top detection circuit, for it provides reset pulse, another road is fed to the bottomside sounding circuit, for it provides reset pulse.
Described delay cell 4 is made up of device that can delayed electric signal, and described device that can delayed electric signal can be broadband delay cable, gate circuit, transmission delay line etc.
Described gate circuit 9 can be made up of OR-NOT circuit or AND circuit.
Described variable capacitance can be a variable capacitance diode.
Essence of the present invention is: optical burst-mode receiver provided by the invention, can produce the reseting pulse signal that circuit produces certain width automatically by the feed forward type reseting pulse signal according to input signal, make to be easy to control resetting time, shorten the time of lead code and boundary belt effectively; Charging capacitor in the detection circuit of top adopts variable capacitance, effectively solved existed when adopting definite value electric capacity be input as large-signal the time long and big this a pair of contradiction of detection error when being input as small-signal of charging interval; Adopt the mode of delay cell and feed forward type reseting pulse signal generation circuit, top detection circuit and the collaborative work of bottomside sounding circuit, shortened the required lead code time of burst and the time of boundary belt greatly; Adopt gate technology at output, eliminated interference, avoided simultaneously in optical burst-mode receiver, using complicated quick discharging circuit, promoted the cost performance of optical burst-mode receiver.
Operation principle of the present invention is:
Photodiode converts the light digital signal that is received to current signal, and this current signal is divided into two-way output after transimpedance preamplifier is converted into voltage signal, one road input delay unit, and another road input feed forward type reseting pulse signal produces circuit.The delay cell output signal is divided into three the tunnel, and wherein the first via is imported the top detection circuit, the second tunnel input bottomside sounding circuit, and Third Road is input to a differential input end of limiting amplifier.The two paths of signals of top detection circuit and bottomside sounding circuit output obtains the decision level of transimpedance preamplifier output signal after through a resitstance voltage divider.(limiting amplifier is to the input of different range signals through the limiting amplifier in the feed forward type reseting pulse signal generation circuit for another road output signal of transimpedance preamplifier, output amplitude all equates) after the constant amplitude output signal produce circuit through a profiled pulses, obtained profiled pulse signal.Profiled pulse signal has obtained the opposite reseting pulse signal of phase place of two-way certain width through the reseting pulse signal forming circuit, wherein a road be fed to the top detection circuit, for its charging capacitor provides reset pulse; Another road is fed to the bottomside sounding circuit, for its charging capacitor provides reset pulse.The Third Road signal of the output signal of resitstance voltage divider and delay cell output is input to two differential input ends of limiting amplifier, after amplifying through the limiting amplifier difference, the voltage signal of different amplitudes all is enlarged into the signal output of constant amplitude.In the gap section that receives optical burst signal, the input end signal of limiting amplifier makes zero in the gap section, the decision level input (output signal of resitstance voltage divider) that is obtained by resitstance voltage divider then is at slowly make zero (discharge process), the output at limiting amplifier 8 will produce a spike this moment, this can cause erroneous judgement for the signal processing of back, in order to eliminate the influence of spike, the two-way output signal of limiting amplifier is carried out certain logical operation with the profiled pulse signal that the reseting pulse signal circuit produces respectively, thereby eliminated the error code that spike brings, finally obtained the difference output of burst packets data-signal.
Utilize optical burst-mode receiver provided by the invention, will have the following advantages with similar receiver contrast:
(1) owing to is used for the generation time of reseting pulse signal that detecting circuit is discharged and compares with the concluding time of burst packets certain delay is arranged; therefore adopt delay cell that signal is carried out suitable delay and can shorten the needed time of boundary belt greatly, thereby improve channel utilization.
(2) in the detection circuit of signal top, substitute definite value electric capacity with variable capacitance, when the input large-signal, the variable capacitance capacitance diminishes, charging interval accelerates, shortened the lead code time of burst packets, thereby improved channel utilization, when the input small-signal, the variable capacitance capacitance increases, overshoot reduces, and corresponding detection error reduces, thereby has reduced error code, therefore, charging interval detection error this a pair of contradiction greatly during long and small-signal had both improved channel utilization when using variable capacitance to solve the large-signal that has existed when adopting definite value electric capacity, had also reduced error code.
(3) the general required reseting pulse signal of optical burst-mode receiver all adds, and is difficult to control resetting time, and has increased the complexity of receiving system greatly; Though the optical burst-mode receiver that has can produce reseting pulse signal by input signal; but owing to adopt the reaction type reseting pulse signal to produce circuit; make lead code and boundary belt time increase greatly; and the width of reseting pulse signal is not suitably controlled yet; overshoot is comparatively serious when making discharge; increased the time of lead code; in addition; the reaction type reseting pulse signal produces circuit owing to introduced feedback mechanism; make the receiving circuit less stable; be easier to produce vibration, solve the above problem that exists and adopt the feed forward type reseting pulse signal to produce circuit.
(4) in the gap section that receives optical burst signal, the input end signal of limiting amplifier makes zero in the gap section, the decision level input that is obtained by resitstance voltage divider then is at slowly make zero (discharge process), the output at limiting amplifier will produce a spike this moment, this can cause erroneous judgement for the signal processing of back, connect a gate circuit at the limiting amplifier output, limiting amplifier output signal envelope pulse signal is carried out logical operation, thereby eliminated the error code that the packet signal gap is brought by discharge, also avoided simultaneously in burst-mode receiver, using complicated quick discharging circuit, promoted the cost performance of burst mode optical receiver.
Description of drawings
Fig. 1 is typical optical burst receiver circuit structure block diagram, and wherein, 1 is photodiode, and 2 is transimpedance preamplifier, and 5 is the top detection circuit, and 6 is the bottomside sounding circuit, and 7 is resitstance voltage divider, and 8 is limiting amplifier.
Fig. 2 is existing a kind of optical burst receiver circuit structure block diagram that can produce reseting pulse signal automatically, wherein, 1 is photodiode, 2 is transimpedance preamplifier, 3 for reseting pulse signal produces circuit, and 5 is the top detection circuit, and 6 is the bottomside sounding circuit, 7 is resitstance voltage divider, and 8 is limiting amplifier.
Fig. 3 is an optical burst receiver circuit structure block diagram of the present invention, wherein, 1 is photodiode, and 2 is transimpedance preamplifier, 3 are feed forward type reseting pulse signal generation circuit, 4 is delay cell, and 5 is the top detection circuit, and 6 is the bottomside sounding circuit, 7 is resitstance voltage divider, 8 is limiting amplifier, and 9 is gate circuit
Fig. 4 is a kind of embodiment circuit diagram among the present invention, wherein, 1 is photodiode, and 2 is transimpedance preamplifier, and 3 are feed forward type reseting pulse signal generation circuit, 4 are the cable delay unit, 5 is the top detection circuit, and 6 is the bottomside sounding circuit, and 7 is resitstance voltage divider, 8 is limiting amplifier, and 9 is gate circuit.
Embodiment
The present invention is further described below in conjunction with accompanying drawing and a kind of embodiment.
Fig. 4 is a specific embodiment of the present invention, wherein 1 is photodiode, and T1 is a bipolar transistor to T40, and R1 is a resistance to R37, DL is the cable delay unit, D1 is a diode to D4, and M1 is metal oxide semiconductor field effect tube (a CMOS pipe) to M28, and VC is a variable capacitance diode, C1 and C4 are electric capacity, L1 is an inductance, and I1 is a current source to I15, and VB1, VC1 are power supply.
The circuit of specific embodiments of the invention is composed as follows:
The negative pole of photodiode 1 is connected to power supply VB1, and its positive pole is received the base stage of bipolar transistor T1, the positive pole of diode D1 and an end of resistance R 8; The negative pole of diode D1 links to each other with the other end of resistance R 8 and the emitter-base bandgap grading of bipolar transistor T5 by resistance R 9; The emitter-base bandgap grading of bipolar transistor T1 is by resistance R 4 ground connection, and its collector electrode links to each other with the emitter-base bandgap grading of bipolar transistor T2; The collector electrode of bipolar transistor T2 links to each other with the base stage of bipolar transistor T3, and meets power supply VC1 by resistance R 3; The base stage of bipolar transistor T2 is passed through resistance R 2 ground connection, and meets power supply VC1 by resistance R 1; The collector electrode of bipolar transistor T3 meets power supply VC1, and its emitter-base bandgap grading links to each other with the base stage of bipolar transistor T4 and passes through resistance R 5 ground connection; The collector electrode of bipolar transistor T4 meets power supply VC1, and its emitter-base bandgap grading links to each other with the base stage of bipolar transistor T5 and passes through resistance R 6 ground connection; The collector electrode of bipolar transistor T5 links to each other with the base stage of bipolar transistor T6 and meets power supply VC1 by resistance R 7, and its emitter-base bandgap grading is by resistance R 10 ground connection; The collector electrode of bipolar transistor T6 meets power supply VC1, and its emitter-base bandgap grading is by resistance R 11 ground connection;
The emitter-base bandgap grading of bipolar transistor T6 links to each other with the input of cable delay cells D L and the base stage of bipolar transistor T7; The collector electrode of bipolar transistor T7 meets power supply VC1, and its emitter-base bandgap grading links to each other with the base stage of bipolar transistor T8 and passes through resistance R 12 ground connection; The collector electrode of bipolar transistor T8 links to each other with the base stage of bipolar transistor T10 and meets power supply VC1 by resistance R 13, the collector electrode of bipolar transistor T9 links to each other with the base stage of bipolar transistor T11 and meets power supply VC1 by resistance R 14, the base stage of bipolar transistor T9 is by resistance R 15 ground connection, and the emitter-base bandgap grading of bipolar transistor T8, T9 links to each other and passes through current source I1 ground connection; The emitter-base bandgap grading of bipolar transistor T10 links to each other with the base stage of bipolar transistor T12 and passes through resistance R 16 ground connection, the emitter-base bandgap grading of bipolar transistor T11 links to each other with the base stage of bipolar transistor T13 and by resistance R 17 ground connection, the collector electrode of bipolar transistor T10, T11 meets power supply VC1; The collector electrode of bipolar transistor T12 meets power supply VC1 by resistance R 18, the collector electrode of bipolar transistor T13 links to each other with the base stage of bipolar transistor T14 and meets power supply VC1 by resistance R 19, and the emitter-base bandgap grading of bipolar transistor T12, T13 links to each other and passes through current source I2 ground connection; The collector electrode of bipolar transistor T16, T17 meets power supply VC1, its base stage interconnects and links to each other with the emitter-base bandgap grading of bipolar transistor T16 and the collector electrode of bipolar transistor T14, the emitter-base bandgap grading of bipolar transistor T17 links to each other with the positive pole of diode D2 and the collector electrode of bipolar transistor T15, and the emitter-base bandgap grading interconnection of bipolar transistor T14, T15 is also passed through current source I3 ground connection; Capacitor C 1 and resistance R 20 parallel connections, one end ground connection, the other end links to each other with the negative pole of diode D2, the grid of CMOS pipe M1, M2; The drain electrode of CMOS pipe M1, M2 meets power supply VC1, and the source electrode of CMOS pipe M1 links to each other with the base stage of bipolar transistor T15 and by current source I4 ground connection, the source electrode of CMOS pipe M2 links to each other with the base stage of bipolar transistor T18 and passes through current source I5 ground connection; The collector electrode of bipolar transistor T18 meets power supply VC1 by resistance R 21, the collector electrode of bipolar transistor T19 links to each other with the base stage of bipolar transistor T20 and meets power supply VC1 by resistance R 22, the base stage of bipolar transistor T19 meets power supply VC1 by resistance R 23 and by resistance R 24 ground connection, the interconnection of the emitter-base bandgap grading of bipolar transistor T18, T19 is also passed through current source I6 ground connection; Resistance R 25 is in parallel with capacitor C 2, one end ground connection, and the other end links to each other with the emitter-base bandgap grading of bipolar transistor T20, an end of inductance L 1 and the grid of CMOS pipe M3, M4, and the collector electrode of bipolar transistor T20 meets power supply VC1; The drain electrode of CMOS pipe M3 meets power supply VC1, and its source electrode manages the grid of M6, M7 with CMOS and the drain electrode of CMOS pipe M4 links to each other the source ground of CMOS pipe M4; The source electrode of CMOS pipe M5 meets power supply VC1, and the gate interconnection of the other end of its grid and inductance L 1 and CMOS pipe M8 is also passed through capacitor C 3 ground connection; The source ground of CMOS pipe M8; The drain electrode of CMOS pipe M5, M6 and M7 links to each other with the grid of CMOS pipe M9, M10; The drain electrode of CMOS pipe M9, M11 meets power supply VC1, and the source electrode of CMOS pipe M9 links to each other with the drain electrode of CMOS pipe M10 and the grid of CMOS pipe M11, M12, and the source electrode of CMOS pipe M11 links to each other with the drain electrode of CMOS pipe M12, the source ground of CMOS pipe M10, M12;
The output of cable delay cells D L links to each other with the base stage of bipolar transistor T21, T26 and T32;
The collector electrode of bipolar transistor T23, T24 meets power supply VC1, its base stage interconnection also connects the emitter-base bandgap grading of bipolar transistor T23 and the collector electrode of bipolar transistor T21, the emitter-base bandgap grading of bipolar transistor T24 links to each other with the positive pole of diode D3 and the collector electrode of bipolar transistor T22, and the emitter-base bandgap grading of bipolar transistor T21, T22 is by current source I7 ground connection; The negative pole of diode D3 is managed the grid of M13, M14, the collector electrode of bipolar transistor T25 and the negative pole of variable capacitance diode VC with CMOS and is linked to each other the plus earth of the emitter-base bandgap grading of bipolar transistor T25 and variable capacitance diode VC; The drain electrode of CMOS pipe M13, M14 meets power supply VC1, and the source electrode of CMOS pipe M13 connects the base stage of bipolar transistor T22 and by current source I8 ground connection, the source electrode of CMOS pipe M14 is by current source I9 ground connection; The base stage of bipolar transistor T25 links to each other with the source electrode of CMOS pipe M9;
The collector electrode of bipolar transistor T28, T29 meets power supply VC1, its base stage interconnection also connects the emitter-base bandgap grading of bipolar transistor T28 and the collector electrode of bipolar transistor T26, the emitter-base bandgap grading of bipolar transistor T29 links to each other with the negative pole of diode D4 and the collector electrode of bipolar transistor T27, and the emitter-base bandgap grading of bipolar transistor T26, T27 is by current source I10 ground connection; The positive pole of diode D4 is managed the grid of M15, M16, the emitter-base bandgap grading of bipolar transistor T30 and an end of capacitor C 4 with CMOS and is linked to each other another termination power VC1 of the collector electrode of bipolar transistor T30 and capacitor C 4; The drain electrode of CMOS pipe M15, M16 meets power supply VC1, and the source electrode of CMOS pipe M15 connects the base stage of bipolar transistor T27 and by current source I11 ground connection, the source electrode of CMOS pipe M16 is by current source I12 ground connection; The base stage of bipolar transistor T30 links to each other with the source electrode of CMOS pipe M11;
Resistance R 26, R27 series connection, its tie point connects the base stage of bipolar transistor T31, the source electrode of another termination CMOS pipe M14 of resistance R 26, the source electrode of another termination CMOS pipe M16 of resistance R 27;
The collector electrode of bipolar transistor T31 links to each other with the base stage of bipolar transistor T33 and meets power supply VC1 by resistance R 28, the collector electrode of bipolar transistor T32 links to each other with the base stage of bipolar transistor T34 and meets power supply VC1 by resistance R 29, and the emitter-base bandgap grading of bipolar transistor T31, T32 is by current source I13 ground connection; The collector electrode of bipolar transistor T33, T34 meets power supply VC1, the emitter-base bandgap grading of bipolar transistor T33 links to each other with the base stage of bipolar transistor T35 and by resistance R 30 ground connection, the emitter-base bandgap grading of bipolar transistor T34 links to each other with the base stage of bipolar transistor T36 and passes through resistance R 31 ground connection; The collector electrode of bipolar transistor T35 links to each other with the base stage of bipolar transistor T37 and meets power supply VC1 by resistance R 32, the collector electrode of bipolar transistor T36 links to each other with the base stage of bipolar transistor T38 and meets power supply VC1 by resistance R 33, and the emitter-base bandgap grading of bipolar transistor T35, T36 is by current source I14 ground connection; The collector electrode of bipolar transistor T37, T38 meets power supply VC1, the emitter-base bandgap grading of bipolar transistor T37 links to each other with the base stage of bipolar transistor T39 and by resistance R 34 ground connection, the emitter-base bandgap grading of bipolar transistor T38 links to each other with the base stage of bipolar transistor T40 and passes through resistance R 35 ground connection; The collector electrode of bipolar transistor T39 meets power supply VC1 by resistance R 36, and the collector electrode of bipolar transistor T40 meets power supply VC1 by resistance R 37, and the emitter-base bandgap grading of bipolar transistor T39, T40 links to each other and passes through current source I15 ground connection;
The source electrode of CMOS pipe M17 meets power supply VC1, and its grid links to each other with the grid of CMOS pipe M20 and the emitter-base bandgap grading of bipolar transistor T20; The source electrode of CMOS pipe M18 meets power supply VC1, its grid links to each other with the grid of CMOS pipe M19 and the collector electrode of bipolar transistor T39, the source electrode of CMOS pipe M19 links to each other with the drain electrode of CMOS pipe M20, the source ground of CMOS pipe M20, the drain electrode of CMOS pipe M17, M18 and M19 link to each other and link to each other with the grid of CMOS pipe M27, M28; The source electrode of CMOS pipe M21 meets power supply VC1, and its grid links to each other with the grid of CMOS pipe M24 and the emitter-base bandgap grading of bipolar transistor T20; The source electrode of CMOS pipe M22 meets power supply VC1, its grid links to each other with the grid of CMOS pipe M23 and the collector electrode of bipolar transistor T40, the source electrode of CMOS pipe M23 links to each other with the drain electrode of CMOS pipe M24, the source ground of CMOS pipe M24, the drain electrode of CMOS pipe M21, M22 and M23 link to each other and link to each other with the grid of CMOS pipe M25, M26; The drain electrode of CMOS pipe M25, M27 meets power supply VC1, and the source electrode of CMOS pipe M25 links to each other with the drain electrode of CMOS pipe M26, the source ground of CMOS pipe M26, and the source electrode of CMOS pipe M27 links to each other with the drain electrode of CMOS pipe M28, the source ground of CMOS pipe M28.
The drain electrode difference of the drain electrode of CMOS pipe M25 and CMOS pipe M27 is exported the required constant-amplitude signal of whole receiver.
The circuit working principle of specific embodiments of the invention is as follows:
The signal of transimpedance preamplifier 2 outputs is divided into two-way, one the tunnel is input to the feed forward type reseting pulse signal produces circuit 3, other one tunnel process cable delay unit 4 carries out being divided into three the tunnel again behind the suitable time-delay, one the tunnel is input to signal top detection circuit 5, another road is input to signal bottomside sounding circuit 6, and Third Road is input to an input of limiting amplifier 8.
Two-stage limiting amplifier in the feed forward type reseting pulse signal generation circuit is respectively by transistor T 8, T9, resistance R 13, R14 and transistor T 12, T13, resistance R 18, R19 form, T7, T10 and T11 are emitter follower, play the effect of isolation buffer, the times magnification number average of two-stage limiting amplifier is not too big, to guarantee that noise can not disturb the next stage peak-detector circuit, the signal amplitude of exporting behind the unequal signal process of the amplitude two-stage limiting amplifier all equates, to alleviate the pressure of peak-detector circuit.Peak-detector circuit and signal top detection circuit similar are made of the T14 that is used for constituting differential amplifier, T15, T16, T17 and the M1, the M2 that play the isolation buffer effect.Diode D2 forward is placed, and realizing peak detection, capacitor C 1 two ends resistance R 20 in parallel replaces the triode of discharge usefulness, suitably selects the value of capacitor C 1 and resistance R 20, has in the input signal long zero also can realize detection even make.The signal peak that peak-detector circuit detects is input to the comparison circuit of being made up of transistor T 18, T19 and resistance R 21, R22, and the input reference voltage of comparison circuit is determined by divider resistance R23, R24.Behind an emitter-base bandgap grading device T20 who plays level shift and isolation buffer effect, the profiled pulse signal that comparator obtains is divided into two-way, one tunnel process is by L1, C2, the delay cell that C3 constitutes suitably postpones, be that peak signal is discharged the needed time time of delay, another road process is by M3, behind the inverter that M4 constitutes, with output after last road postpones with, wherein with door by M6, M7, M8, M9, M10 constitutes, be divided into two-way with the output of door, one the tunnel is fed to the base stage of T25, the one tunnel through one by M11, be fed to the two ends of T30 behind the inverter that M12 constitutes; Adopt this method just can obtain the reseting pulse signal of certain width; do not need again optical burst receiver to be added the reseting pulse signal signal; thereby the complexity and the resetting time that reduce optical receiver are comparatively accurate; in addition; the width of reseting pulse signal is that standard is selected with maximum input signal required discharge time, has therefore reduced greatly because lead code time that overcharging during discharge caused and the increase of boundary belt time.
Signal top detection circuit 5, T21, T22, T23 and T24 constitute differential amplifier circuit, and T23 and T24 form active load.Diode D3 forward is placed, and makes the circuit forward conduction, and oppositely not conducting reduces capacitance discharges.Replace variable capacitance with variable capacitance diode VC, make that the variable capacitance diode equivalent capacitance value diminishes when the input large-signal, the charging interval accelerates, and when the input small-signal, the variable capacitance diode equivalent capacitance value increases, and overcharges to reduce, and corresponding detection error reduces.M13 and M14 and current source I8, I9 form buffer circuit, and the output of M13 feeds back to the base stage of T22, has constituted a unit gain ring, make the value that the top detection circuit obtains and the peak value of signal equate.T25 is used in the gap of burst packets variable capacitance diode being discharged, so that prepare for the arrival of next burst packets.
Signal bottomside sounding circuit 6, T26, T27, T28 and T29 constitute differential amplifier circuit, and T28 and T29 are as active load.Adopt the diode D4 that oppositely places, make the bottom that circuit can detectable signal.Capacitor C 4 is connected to voltage source V C1, and M15, M16 and current source I11, I12 form buffer circuit, and the output of M15 feeds back to the base stage of T27, has constituted a unit gain ring, makes the value that the bottomside sounding circuit obtains and the bottom value of signal equate.T30 is used for gap in burst packets to capacitor discharge, so that prepare for the arrival of next burst packets.
Limiting amplifier 8 is made of three grades of limiting amplifiers, T31, T32 and R28, R29 form the first order, input signal is the signal after resitstance voltage divider 7 and process delay cable DL postpone, output signal is the differential signal of symmetry, has obtained the signal that constant amplitude is exported after the third level limiting amplifier amplitude limit amplification of forming through the second level limiting amplifier is made up of T35, T36 with by T39, T40 then.Wherein the emitter follower of T33 and R30, T34 and R31, T37 and R34, T38 and R35 composition plays the effect of isolation buffer.
Gate circuit 9 is formed with door by two, these two with the door constitute by M17, M18, M19, M20, M27, M28 and M21, M22, M23, M24, M25, M26 respectively, the output of the two-way of limiting amplifier be input to respectively two with an input, with the other two-way input of door be the profiled pulse signal that profiled pulses produces circuit output, through after the effect of gate circuit, eliminate the spike in the limiting amplifier output signal, thereby reduced error code.
Need to prove: the device in the foregoing description all can adopt the product of market-ripe, so just can reduce cost greatly, and be easy to adopt integrated circuit technology to carry out integrated or secondary is integrated.
The optical burst-mode receiver that the embodiment of the invention provides; under 1.25Gb/s speed; receiving sensitivity is-26dBm; but the maximum received optical power is-0.8dBm; receive dynamic range and reach 25.2dB; be 60ns, reseting pulse signal width time when being 25ns time of delay, and the minimum preamble time is 20ns, and the minimum boundary belt time is 140ns.It can be widely used in the design and the application of the optical burst-mode receiver in optical communication and the optical fiber telecommunications system.
Claims (6)
1, a kind of optical burst-mode receiver comprises photodiode (1), transimpedance preamplifier (2), top detection circuit (5), bottomside sounding circuit (6), resitstance voltage divider (7), limiting amplifier (8); It is characterized in that it also comprises: the feed forward type reseting pulse signal produces circuit (3), delay cell (4), gate circuit (9); Charging capacitor in the described top detection circuit (5) is a variable capacitance; Described feed forward type reseting pulse signal produces circuit (3) and comprises limiting amplifier (A2), a profiled pulses generation circuit, a reseting pulse signal forming circuit; The output of photodiode (1) is connected to the input of transimpedance preamplifier (2), and the output of transimpedance preamplifier (2) is connected respectively to the input of delay cell (4), top detection circuit (5) and bottomside sounding circuit (6); The output of top detection circuit (5) and bottomside sounding circuit (6) is connected respectively to two inputs of resitstance voltage divider (7), and the output of the output of resitstance voltage divider (7) and delay cell (4) is connected with two inputs of limiting amplifier (8) respectively; Two outputs of limiting amplifier (8) are connected respectively to two inputs of gate circuit, and two inputs in addition of gate circuit link to each other with the output that the feed forward type reseting pulse signal produces the profiled pulses generation circuit in the circuit (3); The feed forward type reseting pulse signal produces the opposite reseting pulse signal of phase place of the reseting pulse signal forming circuit output two-way certain width in the circuit (3), one the tunnel is fed to the top detection circuit, for it provides reset pulse, another road is fed to the bottomside sounding circuit, for it provides reset pulse; Described gate circuit (9) is used for the profiled pulse signal of the output signal of limiting amplifier (8) and feed forward type reseting pulse signal generation circuit (3) generation is carried out logical operation to eliminate the error code that the packet signal gap is brought by discharge.
2, a kind of optical burst-mode receiver according to claim 1 is characterized in that, described delay cell (4) is made up of device that can delayed electric signal.
3, a kind of optical burst-mode receiver according to claim 2 is characterized in that, described device that can delayed electric signal is broadband delay cable, gate circuit, transmission delay line.
4, a kind of optical burst-mode receiver according to claim 1 is characterized in that, described gate circuit (9) is made up of OR-NOT circuit or AND circuit.
5, a kind of optical burst-mode receiver according to claim 1 is characterized in that, described variable capacitance is a variable capacitance diode.
6, according to claim 3,4 or 5 described a kind of optical burst-mode receivers, it is characterized in that:
Photodiode (1) is made of a photodiode; Transimpedance preamplifier (2) is made up of bipolar transistor (T1 is to T6), resistance (R1 is to R11) and diode (D1); The feed forward type reseting pulse signal produces circuit (3) and is made up of bipolar transistor (T7 is to T20), resistance (R12 is to R25), metal oxide semiconductor field effect tube (M1 is to M12), electric capacity (C1 is to C3), current source (I1 is to I6), diode (D2) and inductance (L1); Cable delay unit (4) is made of the circuit delay line; Top detection circuit (5) is made up of bipolar transistor (T21 is to T25), metal oxide semiconductor field effect tube (M13 and M14), variable capacitance diode (VC), current source (I7 is to I9) and diode (D3); Bottomside sounding circuit (6) is made up of bipolar transistor (T26 is to T30), metal oxide semiconductor field effect tube (M15 and M16), electric capacity (C4), current source (I10 is to I12) and diode (D4); Resitstance voltage divider (7) is made up of resistance (R26 and R27); Limiting amplifier (8) is made up of bipolar transistor (T31 is to T40), resistance (R28 is to R37) and current source (I13 is to I15); Gate circuit (9) is made up of metal oxide semiconductor field effect tube (M17 is to M28);
The negative pole of photodiode (1) is connected to power supply (VB1), and its positive pole is received the base stage of the 1st bipolar transistor (T1), the positive pole of the 1st diode (D1) and an end of the 8th resistance (R8); The negative pole of the 1st diode (D1) links to each other with the other end of the 8th resistance (R8) and the emitter-base bandgap grading of the 5th bipolar transistor (T5) by the 9th resistance (R9); The emitter-base bandgap grading of the 1st bipolar transistor (T1) is by the 4th resistance (R4) ground connection, and its collector electrode links to each other with the emitter-base bandgap grading of the 2nd bipolar transistor (T2); The collector electrode of the 2nd bipolar transistor (T2) links to each other with the base stage of the 3rd bipolar transistor (T3), and connects power supply (VC1) by the 3rd resistance (R3); The base stage of the 2nd bipolar transistor (T2) is passed through the 2nd resistance (R2) ground connection, and connects power supply (VC1) by the 1st resistance (R1); The collector electrode of the 3rd bipolar transistor (T3) connects power supply (VC1), and its emitter-base bandgap grading links to each other with the base stage of the 4th bipolar transistor (T4) and passes through the 5th resistance (R5) ground connection; The collector electrode of the 4th bipolar transistor (T4) connects power supply (VC1), and its emitter-base bandgap grading links to each other with the base stage of the 5th bipolar transistor (T5) and passes through the 6th resistance (R6) ground connection; The collector electrode of the 5th bipolar transistor (T5) links to each other with the base stage of the 6th bipolar transistor (T6) and connects power supply (VC1) by the 7th resistance (R7), and its emitter-base bandgap grading is by the 10th resistance (R10) ground connection; The collector electrode of the 6th bipolar transistor (T6) connects power supply (VC1), and its emitter-base bandgap grading is by the 11st resistance (R11) ground connection;
The emitter-base bandgap grading of the 6th bipolar transistor (T6) links to each other with the input of cable delay unit (DL) and the base stage of the 7th bipolar transistor (T7); The collector electrode of the 7th bipolar transistor (T7) connects power supply (VC1), and its emitter-base bandgap grading links to each other with the base stage of the 8th bipolar transistor (T8) and passes through the 12nd resistance (R12) ground connection; The collector electrode of the 8th bipolar transistor (T8) links to each other with the base stage of the 10th bipolar transistor (T10) and connects power supply (VC1) by the 13rd resistance (R13), the collector electrode of the 9th bipolar transistor (T9) links to each other with the base stage of the 11st bipolar transistor (T11) and connects power supply (VC1) by the 14th resistance (R14), the base stage of the 9th bipolar transistor (T9) is by the 15th resistance (R15) ground connection, and the 8th links to each other with the emitter-base bandgap grading of the 9th bipolar transistor (T8, T9) and pass through the 1st current source (I1) ground connection; The emitter-base bandgap grading of the 10th bipolar transistor (T10) links to each other with the base stage of the 12nd bipolar transistor (T12) and passes through the 16th resistance (R16) ground connection, the emitter-base bandgap grading of the 11st bipolar transistor (T11) links to each other with the base stage of the 13rd bipolar transistor (T13) and by the 17th resistance (R17) ground connection, the collector electrode of the 10th and the 11st bipolar transistor (T10, T11) connects power supply (VC1); The collector electrode of the 12nd bipolar transistor (T12) connects power supply (VC1) by the 18th resistance (R18), the collector electrode of the 13rd bipolar transistor (T13) links to each other with the base stage of the 14th bipolar transistor (T14) and connects power supply (VC1) by the 19th resistance (R19), and the 12nd links to each other with the emitter-base bandgap grading of the 13rd bipolar transistor (T12, T13) and by the 2nd current source (I2) ground connection; The collector electrode of the 16th and the 17th bipolar transistor (T16, T17) connects power supply (VC1), its base stage interconnects and links to each other with the emitter-base bandgap grading of the 16th bipolar transistor (T16) and the collector electrode of the 14th bipolar transistor (T14), the emitter-base bandgap grading of the 17th bipolar transistor (T17) links to each other with the positive pole of the 2nd diode (D2) and the collector electrode of the 15th bipolar transistor (T15), and the emitter-base bandgap grading interconnection of the 14th and the 15th bipolar transistor (T14, T15) is also passed through the 3rd current source (I3) ground connection; The 1st electric capacity (C1) and the 20th resistance (R20) parallel connection, one end ground connection, the other end links to each other with the grid of 2CMOS pipe (M1, M2) with the negative pole, the 1st of the 2nd diode (D2); The 1st and the drain electrode of 2CMOS pipe (M1, M2) connect power supply (VC1), the source electrode of 1CMOS pipe (M1) links to each other with the base stage of the 15th bipolar transistor (T15) and by the 4th current source (I4) ground connection, the source electrode of 2CMOS pipe (M2) links to each other with the base stage of the 18th bipolar transistor (T18) and passes through the 5th current source (I5) ground connection; The collector electrode of the 18th bipolar transistor (T18) connects power supply (VC) by the 21st resistance (R21), the collector electrode of the 19th bipolar transistor (T19) links to each other with the base stage of the 20th bipolar transistor (T20) and connects power supply (VC1) by the 22nd resistance (R22), the base stage of the 19th bipolar transistor (T19) connects power supply (VC1) by the 23rd resistance (R23) and by the 24th resistance (R24) ground connection, the interconnection of the emitter-base bandgap grading of the 18th and the 19th bipolar transistor (T18, T19) is also passed through the 6th current source (I6) ground connection; The 25th resistance (R25) is in parallel with the 2nd electric capacity (C2), one end ground connection, the other end links to each other with the emitter-base bandgap grading of the 20th bipolar transistor (T20), an end and the 3rd of inductance (L1), the grid of 4CMOS pipe (M3, M4), and the collector electrode of the 20th bipolar transistor (T20) connects power supply (VC1); The drain electrode of 3CMOS pipe (M3) connects power supply (VC1), and its source electrode links to each other the source ground of 4CMOS pipe (M4) with the 6th with the grid of 7CMOS pipe (M6, M7) and the drain electrode of 4CMOS pipe (M4); The source electrode of 5CMOS pipe (M5) connects power supply (VC1), and the gate interconnection of the other end of its grid and inductance (L1) and 8CMOS pipe (M8) is also passed through the 3rd electric capacity (C3) ground connection; The source ground of 8CMOS pipe (M8); 5th, the 6th links to each other with the drain electrode and the 9th of 7CMOS pipe (M5, M6 and M7), the grid of 10CMOS pipe (M9, M10); 9th, the drain electrode of 11CMOS pipe (M9, M11) connects power supply (VC1), the source electrode of 9CMOS pipe (M9) links to each other with the drain electrode and the 11st of 10CMOS pipe (M10), the grid of 12CMOS pipe (M11, M12), the drain electrode of the source electrode of 11CMOS pipe (M11) and 12CMOS pipe (M12) links to each other, and the 10th, 12CMOS manages the source ground of (M10, M12);
The base stage of the output and the 21st, the 26th of cable delay unit (DL), the 32nd bipolar transistor (T21, T26 and T32) links to each other;
23rd, the collector electrode of the 24th bipolar transistor (T23, T24) connects power supply (VC1), its base stage interconnection also connects the emitter-base bandgap grading of the 23rd bipolar transistor (T23) and the collector electrode of the 21st bipolar transistor (T21), the emitter-base bandgap grading of the 24th bipolar transistor (T24) links to each other with the positive pole of the 3rd diode (D3) and the collector electrode of the 22nd bipolar transistor (T22), and the emitter-base bandgap grading of the 21st, the 22nd bipolar transistor (T21, T22) is by the 7th current source (I7) ground connection; Grid, the collector electrode of the 25th bipolar transistor (T25) and the negative pole of variable capacitance diode (VC) of the negative pole and the 13rd of the 3rd diode (D3), 14CMOS pipe (M13, M14) link to each other the plus earth of the emitter-base bandgap grading of the 25th bipolar transistor (T25) and variable capacitance diode (VC); 13rd, the drain electrode of 14CMOS pipe (M13, M14) connects power supply (VC1), the source electrode of 13CMOS pipe (M13) connects the base stage of the 22nd bipolar transistor (T22) and by the 8th current source (I8) ground connection, the source electrode of 14CMOS pipe (M14) is by the 9th current source (I9) ground connection; The base stage of the 25th bipolar transistor (T25) links to each other with the source electrode of 9CMOS pipe (M9);
28th, the collector electrode of the 29th bipolar transistor (T28, T29) connects power supply (VC1), its base stage interconnection also connects the emitter-base bandgap grading of the 28th bipolar transistor (T28) and the collector electrode of the 26th bipolar transistor (T26), the emitter-base bandgap grading of the 29th bipolar transistor (T29) links to each other with the negative pole of the 4th diode (D4) and the collector electrode of the 27th bipolar transistor (T27), and the emitter-base bandgap grading of the 26th, the 27th bipolar transistor (T26, T27) is by the 10th current source (I10) ground connection; The positive pole of the 4th diode (34) links to each other another termination power (VC1) of the collector electrode of the 30th bipolar transistor (T30) and the 4th electric capacity (C4) with the 15th with grid, the emitter-base bandgap grading of the 30th bipolar transistor (T30) and an end of the 4th electric capacity (C4) of 16CMOS pipe (M15, M16); The 15th and the drain electrode of 16CMOS pipe (M15, M16) connect power supply (VC1), the source electrode of 15CMOS pipe (M15) connects the base stage of the 27th bipolar transistor (T27) and by the 11st current source (I11) ground connection, the source electrode of 16CMOS pipe (M16) is by the 12nd current source (I12) ground connection; The base stage of the 30th bipolar transistor (T30) links to each other with the source electrode of 11CMOS pipe (M11);
The the 26th and the 27th resistance (R26, R27) series connection, its tie point connects the base stage of the 31st bipolar transistor (T31), the source electrode of another termination 14CMOS pipe (M14) of the 26th resistance (R26), the source electrode of another termination 16CMOS pipe (M16) of the 27th resistance (R27);
The collector electrode of the 31st bipolar transistor (T31) links to each other with the base stage of the 33rd bipolar transistor (T33) and connects power supply (VC1) by the 28th resistance (R28), the collector electrode of the 32nd bipolar transistor (T32) links to each other with the base stage of the 34th bipolar transistor (T34) and connects power supply (VC1) by the 29th resistance (R29), and the emitter-base bandgap grading of the 31st and the 32nd bipolar transistor (T31, T32) is by the 13rd current source (I13) ground connection; The collector electrode of the 33rd and the 34th bipolar transistor (T33, T34) connects power supply (VC1), the emitter-base bandgap grading of the 33rd bipolar transistor (T33) links to each other with the base stage of the 35th bipolar transistor (T35) and by the 30th resistance (R30) ground connection, the emitter-base bandgap grading of the 34th bipolar transistor (T34) links to each other with the base stage of the 36th bipolar transistor (T36) and passes through the 31st resistance (R31) ground connection; The collector electrode of the 35th bipolar transistor (T35) links to each other with the base stage of the 37th bipolar transistor (T37) and connects power supply (VC1) by the 32nd resistance (R32), the collector electrode of the 36th bipolar transistor (T36) links to each other with the base stage of the 38th bipolar transistor (T38) and connects power supply (VC1) by the 33rd resistance (R33), and the emitter-base bandgap grading of the 35th and the 36th bipolar transistor (T35, T36) is by the 14th current source (I14) ground connection; The collector electrode of the 37th and the 38th bipolar transistor (T37, T38) connects power supply (VC1), the emitter-base bandgap grading of the 37th bipolar transistor (T37) links to each other with the base stage of the 39th bipolar transistor (T39) and by the 34th resistance (R34) ground connection, the emitter-base bandgap grading of the 38th bipolar transistor (T38) links to each other with the base stage of the 40th bipolar transistor (T40) and passes through the 35th resistance (R35) ground connection; The collector electrode of the 39th bipolar transistor (T39) connects power supply (VC1) by the 36th resistance (R36), the collector electrode of the 40th bipolar transistor (T40) connects power supply (VC1) by the 37th resistance (R37), and the 39th links to each other with the emitter-base bandgap grading of the 40th bipolar transistor (T39, T40) and by the 15th current source (I15) ground connection;
The source electrode of 17CMOS pipe (M17) connects power supply (VC1), and its grid links to each other with the grid of 20CMOS pipe (M20) and the emitter-base bandgap grading of the 20th bipolar transistor (T20); The source electrode of 18CMOS pipe (M18) connects power supply (VC1), its grid links to each other with the grid of 19CMOS pipe (M19) and the collector electrode of the 39th bipolar transistor (T39), the source electrode of 19CMOS pipe (M19) links to each other with the drain electrode of 20CMOS pipe (M20), the source ground of 20CMOS pipe (M20), the 17th, the 18th links to each other with the drain electrode of 19CMOS pipe (M17, M18 and M19) and links to each other with the grid of 28CMOS pipe (M27, M28) in the 27th; The source electrode of 21CMOS pipe (M21) connects power supply (VC1), and its grid links to each other with the grid of 24CMOS pipe (M24) and the emitter-base bandgap grading of the 20th bipolar transistor (T20); The source electrode of 22CMOS pipe (M22) connects power supply (VC1), its grid links to each other with the grid of 23CMOS pipe (M23) and the collector electrode of the 40th bipolar transistor (T40), the source electrode of 23CMOS pipe (M23) links to each other with the drain electrode of 24CMOS pipe (M24), the source ground of 24CMOS pipe (M24), the 21st, the 22nd links to each other with the drain electrode of 23CMOS pipe (M21, M22 and M23) and links to each other with the grid of 26CMOS pipe (M25, M26) with the 25th; The 25th and the drain electrode of 27CMOS pipe (M25, M27) connect power supply (VC1), the source electrode of 25CMOS pipe (M25) links to each other with the drain electrode of 26CMOS pipe (M26), the source ground of 26CMOS pipe (M26), the source electrode of 27CMOS pipe (M27) links to each other with the drain electrode of 28CMOS pipe (M28), the source ground of 28CMOS pipe (M28).
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| CN101355388B (en) * | 2007-07-25 | 2012-07-04 | 华为技术有限公司 | Receiving apparatus and method |
| CN101145848B (en) * | 2007-10-25 | 2012-05-30 | 青岛海信光电科技股份有限公司 | Optical receiving-transmission integrated module for 1000M passive optical network office |
| CN102347794B (en) * | 2010-08-04 | 2014-07-30 | 成都优博创技术有限公司 | Burst light signal receiving apparatus |
| CN103166714B (en) * | 2013-02-22 | 2016-08-03 | 青岛海信宽带多媒体技术有限公司 | Signal supervisory instrument based on burst mode optical receiver |
| CN105897342A (en) * | 2016-06-03 | 2016-08-24 | 广州日铨电子有限公司 | Photo-electric transmission module and photo-electric transmission system |
| CN116781177B (en) * | 2023-08-24 | 2023-11-17 | 上海米硅科技有限公司 | Burst mode limiting amplifier and control method |
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| US20030194244A1 (en) * | 2002-04-15 | 2003-10-16 | Hee-Chan Doh | Burst-mode optical receiver of differential output structure |
| EP1357717A1 (en) * | 2002-04-25 | 2003-10-29 | Samsung Electronics Co., Ltd. | Automatic detection threshold control device for burst mode optical receiver |
| CN1545224A (en) * | 2003-11-27 | 2004-11-10 | 武汉电信器件公司 | Burst mode optical receiver |
| CN1601929A (en) * | 2003-09-24 | 2005-03-30 | 夏普株式会社 | Receiving circuit for free-space optical communication |
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| US20030194244A1 (en) * | 2002-04-15 | 2003-10-16 | Hee-Chan Doh | Burst-mode optical receiver of differential output structure |
| EP1357717A1 (en) * | 2002-04-25 | 2003-10-29 | Samsung Electronics Co., Ltd. | Automatic detection threshold control device for burst mode optical receiver |
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