CN101552647B - Method and device for receiving optical signals - Google Patents
Method and device for receiving optical signals Download PDFInfo
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- CN101552647B CN101552647B CN 200810066603 CN200810066603A CN101552647B CN 101552647 B CN101552647 B CN 101552647B CN 200810066603 CN200810066603 CN 200810066603 CN 200810066603 A CN200810066603 A CN 200810066603A CN 101552647 B CN101552647 B CN 101552647B
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Abstract
The invention discloses an optical receiver which comprises a receiving unit, a converting unit, a detecting unit and a burst clock data recovering circuit, wherein the receiving unit is used for receiving optical signals which at least comprise optical signals having two different transmission rates; the converting unit is used for converting the received optical signals to voltage signals; the detecting unit is used for detecting the transmission rates of the voltage signals and outputting control signals according to the detecting result; and the burst clock data recovering circuit is used for recovering the clock and the data for the voltage signals according to the control signals. Correspondingly, the invention also discloses a method for receiving optical signals. By the invention, not only time multiplexing signals with two rates of GEPON and 10G EPON can be received, but also fast synchronization and time saving can be realized.
Description
Technical field
The present invention relates to network communication field, specifically, relate to the method and apparatus that a kind of light signal receives.
Background technology
Passive optical network PON is a kind of Optical Fiber Transmission and access technology of point-to-multipoint, and its structure as shown in Figure 1.It is comprised of the optical network unit ONU of the optical line terminal OLT of office's side, user's side or Optical Network Terminal ONT and Optical Distribution Network ODN.Wherein, OLT is down direction to the transmission direction of ONU, adopts the TDM mode, and OLT issues information broadcasting each ONU continuously, and each ONU selects one's own data receiver; ONU adopts the TDMA mode to the up direction that is transmitted as of OLT, and namely upstream data sends and happens suddenly, and different ONU take different ascending time slots, and a plurality of ONU share up link by time-multiplexed mode.
In order to utilize the fiber resource of existing GEPON system, following 10G EPON needs and the GEPON coexistence of systems, and in 10G/1G EPON symbiotic system, OLT must support the ONU of 10G, two kinds of speed of 1G.
Do not consider the lock in time of the critical component of many rate receivers in existing many speed optical receiver technology, take larger time overhead, can't reach Fast synchronization.
Summary of the invention
The technical problem that the embodiment of the invention will solve is: the method and apparatus that provides a kind of light signal to receive overcomes that many speed reception technique takies larger time overhead in the existing 10G/1G EPON symbiotic system, can't reach the shortcoming of Fast synchronization.
For solving the problems of the technologies described above, the embodiment of the invention provides a kind of optical receiver, comprising: receiving element, converting unit, detecting unit and burst clock data recovering circuit; Receiving element is used for receiving optical signals, and this light signal comprises the light signal of two kinds of different transmission rates at least; Converting unit, the light signal that is used for receiving is converted to voltage signal; Detecting unit is for detection of the transmission rate of voltage signal, according to testing result output control signal; Burst clock data recovering circuit is used for according to control signal voltage signal being carried out clock and data recovery and processes;
Described detecting unit specifically comprises:
The pattern detecting unit is used for described voltage signal is postponed to process with gate circuit, if it is corresponding with the time of delay to occur the transmission rate of predetermined pattern and described voltage signal in the described voltage signal, exports an instantaneous high level of bit;
The threshold processing unit is used for the instantaneous high level of described pattern detecting unit output is carried out integration, and the signal behind the instantaneous high level integration and high threshold and the low threshold preset are compared; If the signal behind the described integration greater than described default high threshold, is exported the control signal of receiver voltage signal; If the signal behind the described integration is lower than described default low threshold, the control signal that the receiver voltage signal is forbidden in output.
Correspondingly, the method that the embodiment of the invention provides a kind of light signal to receive comprises: receiving optical signals, and this light signal comprises the light signal of two kinds of different transmission rates at least; The light signal that receives is converted to voltage signal; The transmission rate of detectable voltage signals is according to testing result output control signal; According to control signal control burst clock data recovering circuit, voltage signal is carried out clock and data recovery process;
The transmission rate of the described voltage signal of described detection according to testing result output control signal, specifically comprises:
Described voltage signal is postponed to process with gate circuit, if it is corresponding with the time of delay to occur the transmission rate of predetermined pattern and described voltage signal in the described voltage signal, export an instantaneous high level of bit;
Described instantaneous high level is carried out integration, the signal behind the instantaneous high level integration and high threshold and the low threshold preset are compared; If the signal behind the described integration greater than described default high threshold, is exported the control signal of receiver voltage signal; If the signal behind the described integration is lower than described default low threshold, the control signal that the receiver voltage signal is forbidden in output.
Can be found out by the technical scheme that the invention described above embodiment provides, the invention provides the method and apparatus that a kind of light signal receives, be converted to voltage signal by the light signal that will receive, the transmission rate of detectable voltage signals, according to testing result output control signal, according to control signal control burst clock data recovering circuit voltage signal is carried out clock and data recovery and process.Adopt technical scheme of the present invention, not only can receive two kinds of rate time-division multiplex signals of GEPON and 10G EPON, and can reach Fast synchronization, reduce time overhead.
Description of drawings
Fig. 1 is the structural representation of EPON in the prior art;
Fig. 2 is the principle schematic of 10G/1G EPON coexistence of systems in the prior art;
Fig. 3 is the structural representation of the optical receiver of the embodiment of the invention one;
Fig. 4 is the structural representation of the optical receiver of the embodiment of the invention two;
Fig. 5 is the realization block diagram of the signal deteching circuit of the embodiment of the invention two;
Fig. 6 is the schematic diagram of 101/010 pattern testing circuit of the embodiment of the invention two;
Fig. 7 is the schematic diagram of the threshold processing circuit of the embodiment of the invention two;
Fig. 8 is the schematic diagram of the burst clock data recovering circuit of the embodiment of the invention two;
Fig. 9 is the schematic diagram of the splitter of the embodiment of the invention two;
Figure 10 is the structural representation of the optical receiver of the embodiment of the invention three;
Figure 11 is the structural representation of the optical receiver of the embodiment of the invention four;
Figure 12 is the method schematic diagram that the light signal of the embodiment of the invention five receives.
Embodiment
Adopt the embodiment of the invention, can realize the reception to the light signal of multiple different transmission rates, for convenience of description, below only describe as an example of the light signal of GEPON and two kinds of speed of 10G EPON example.
Fig. 3 is the structural representation of the optical receiver of the embodiment of the invention one.This optical receiver comprises: receiving element, converting unit, detecting unit and burst clock data recovering circuit; Wherein, receiving element is used for receiving optical signals, and this light signal comprises the light signal of two kinds of different transmission rates at least; Converting unit, the light signal that is used for receiving is converted to voltage signal; Detecting unit is for detection of the transmission rate of voltage signal, according to testing result output control signal; Burst clock data recovering circuit is used for according to control signal voltage signal being carried out clock and data recovery and processes.
Above-mentioned detecting unit and burst clock data recovering circuit can be integrated in the module.
Above-mentioned detecting unit specifically comprises: pattern detecting unit and threshold processing unit; Wherein, the pattern detecting unit is used for voltage signal is postponed to process with gate circuit, if it is corresponding with the time of delay to occur the transmission rate of predetermined pattern and voltage signal in the voltage signal, exports an instantaneous high level of bit; The threshold processing unit is used for the instantaneous high level of pattern detecting unit output is carried out integration, and the signal behind the instantaneous high level integration and high threshold and the low threshold preset are compared; If the signal behind the integration greater than default high threshold, is exported the control signal of receiver voltage signal; If the signal behind the integration is lower than default low threshold, the control signal that the receiver voltage signal is forbidden in output.
Above-mentioned burst clock data recovering circuit comprises switch, phase-locked loop and frequency of training source; Wherein, the frequency of training source is for generation of frequency of training; Switch is used for receiving the control signal that detecting unit is exported; Based on the control signal of receiver voltage signal, voltage signal is inputted phase-locked loop; Based on the control signal of forbidding the receiver voltage signal, frequency of training is inputted phase-locked loop; Phase-locked loop is used for based on voltage signal, recovers clock and data from voltage signal; Based on frequency of training, the frequency of locking phase-locked loop.
Above-mentioned predetermined pattern comprises 010 and 101.
Present embodiment is realized burst clock data recovering circuit (BCDR) by the mode that adopts traditional " training data " to add phase-locked loop.When not having data inputs, frequency of training is added the phase-locked loop input keeping phase-lock-ring output frequency constant, so that the capture time when accelerating data and arriving, realize the clock and data recovery of burst mode.
Fig. 4 is the structural representation of the optical receiver of the embodiment of the invention two.Its work engineering is: photodetector is converted into current signal with the light signal that receives, and preamplifier amplifies the current signal that photodetector produces, and output voltage signal.Splitter is divided into two-way with the voltage signal of preamplifier output, gives respectively 1G (GEPON) and 10G (10G EPON) branch road and processes.Low pass filter filters out signal high-frequency noise in each branch road, and give main amplifier, main amplifier is adjudicated the analog signal that receives, and changes it into clearly digital signal.Signal deteching circuit determines whether this road signal, at this road signal duration of existence, can export a level, and index signal exists, thereby control burst clock and data recovery (BCDR) circuit working recovers the clock in the signal, and to the data shaping.
Above-mentioned photodetector can adopt avalanche photodide (APD) or general photodiode PIN.PIN is under reversed bias voltage, and the electric current of its generation becomes certain proportionate relationship with irradiation luminous power thereon.APD utilizes avalanche multiplication effect to make photoelectric current obtain multiplication, and remolding sensitivity PIN is large.Can select PIN or APD according to system's needs.The photodetector biasing circuit provides reversed bias voltage to APD or PIN.For APD, also need temperature-compensation circuit for detection of the APD ambient temperature, and produce control signal control photodetector biasing circuit, block the voltage variation with temperature with compensation APD.
Above-mentioned preamplifier can adopt trans-impedance amplifier (TIA).Trans-impedance amplifier amplifies the current signal that photodetector produces, and output voltage signal.The voltage signal of preamplifier output comprises the signal of 1G (GEPON) and 10G (10G EPON).
Splitter (active or passive splitter), the voltage signal that preamplifier is exported is divided into two-way, gives respectively 1G (GEPON) and 10G (10G EPON) branch road and processes.Because 10G (10G EPON) and 1G (GEPON) light signal adopt TDM multiplexing, take different ascending time slots, therefore preamplifier output is after the splitter shunt, and the voltage signal of 1G and two branch roads of 10G includes the signal of 1G and 10G speed TDM.
The processing procedure of signal is as follows behind the splitter:
(1) when the 1G signal arrives, splitter shunts to 1G and 10G branch road with signal.
For the 1G branch road, the first low pass filter filters out signal high-frequency noise, to improve receiving sensitivity, and give the first main amplifier, the first main amplifier adopts limiting amplifier (LA), the 1G analog signal that receives is adjudicated, change it into clearly digital signal, give simultaneously first signal testing circuit and the first clock and data recovery circuit (BCDR).The first signal testing circuit can be exported a level at 1G signal duration of existence, and index signal exists.It is this road signal that the first signal testing circuit is judged, controls BCDR work, and a BCDR recovers the clock in the signal, and to the data shaping.The clock that recovers and the data after the shaping are fed to rear coagulation.The first signal testing circuit is exported a signal designation simultaneously to rear one-level, the arrival of notice 1G signal.
For the 10G branch road, the 1G analog signal changes clearly digital signal into after through the second low pass filter and the second main amplifier, and gives secondary signal testing circuit and the 2nd BCDR.It is not this road signal that the secondary signal testing circuit is judged, forbids the 2nd BCDR work, exports simultaneously an indication to rear one-level, and notice is not this road signal.
(2) when the 10G signal arrives, splitter will shunt to 1G and 10G branch road by signal.
For the 1G branch road, because the first low pass filter and the first main amplifier bandwidth are far smaller than the 10G signal bandwidth, first signal testing circuit cisco unity malfunction, and can't detect signal.It is not this road signal that the first signal testing circuit is judged, forbids BCDR work, exports simultaneously an indication to rear one-level, and notice is not this road signal.
For the 10G branch road, the second low pass filter filters out signal high-frequency noise is to improve receiving sensitivity, and give the second main amplifier, the second main amplifier adopts LA, the 10G analog-signal transitions that receives is digital signal clearly, and gives simultaneously secondary signal testing circuit and the 2nd BCDR.The secondary signal testing circuit can be exported a level at 10G signal duration of existence, and index signal exists.It is this road signal that the secondary signal testing circuit is judged, controls the 2nd BCDR work, and the 2nd BCDR recovers the clock in the signal, and to the data shaping.The clock that recovers and the data after the shaping are fed to rear coagulation.The secondary signal testing circuit is exported a signal designation simultaneously to rear one-level, the arrival of notice 10G signal.
Be illustrated in figure 5 as the realization block diagram of the signal deteching circuit of the embodiment of the invention two, signal deteching circuit comprises 101/010 pattern testing circuit and threshold processing circuit.
When 101/010 pattern testing circuit detects in the data pattern that comprises " 010 " or " 101 ", and speed can export the instantaneous high level that a duration is a bit when consistent with this branch road speed, otherwise output low level.Be illustrated in figure 6 as the schematic diagram of 101/010 pattern testing circuit of the embodiment of the invention two, holding wire is single-ended or differential signal line among the figure.Input data S0 is divided into the identical signal of two-way through driving (1).Wherein one road signal S 1 delivers to an input of XOR (3), and another road signal postpones a bit time through postponing (2), and the signal S3 after the delay is sent to another input of XOR (3).Behind XOR (3), can realize the detection to " 01 " or " 10 " of input data S0.The output S4 of XOR (3) is divided into the identical signal of two-way through overdrive (4), wherein one road signal S5 delivers to an input with door (6), another road signal postpones a bit time through postponing (5), and the signal S6 after the delay delivers to another input with door (6).By with door (6) after, can realize to the signal S4 of XOR (3) output the detection of " 11 ".The output S7 of whole circuit realizes the detection to " 010 " or " 101 " of input data S0.
When in signal, " 010 " or " 101 " pattern occurring, the high level that it is a bit that testing circuit is exported a duration, when occurring in the signal switching continuously such as " 010101... " (comprising continuous " 010 ", " 101 "), testing circuit continuous wave output high level, until the pattern of " 010 " or " 101 " no longer occurs, circuit is output as low.
The signal of threshold processing processing of circuit 101/010 pattern testing circuit output, because when " 010101... " switching occurring continuously in the input data, 101/010 pattern testing circuit continues the output high level, but when appearance " 010 " in the input data, " 101 " are relatively more rare, the high level that the output of 101/010 pattern testing circuit is relatively more rare.For this relatively more rare high level is detected, need to carry out integration to it, compare with a fixed level again.When the probability that occurs when " 010 ", " 101 " in the signal hanged down, the DC level behind the 101/010 pattern testing circuit output signal integration was lower, and comparative level must arrange lower, was output as height after guaranteeing relatively.But when the comparative level setting is low, noise occurs easily to its false triggering, making does not have during the signal, can erroneous trigger produce high level yet.
Therefore the threshold processing circuit is provided with two comparison thresholds in the present embodiment.A higher comparison threshold is used for set, because in the lead code of input data, existing continuously, " 010101... " switches, 101/010 pattern testing circuit continues the output high level, itself and a higher comparison threshold are compared, can guarantee that during lead code, the threshold processing circuit is output as height, namely exports set.Can guarantee again when not having signal, can be by the noise false triggering.Another lower comparison threshold is used for signal is resetted.Because during the useful signal of input data, " 010 ", " 101 " occur relatively more rare, the high level that the output of 101/010 pattern testing circuit is relatively more rare, it is carried out integration after, compare with a more low level comparison threshold, the output after the assurance relatively is continuously height again.And when blackout, low level appears in the output of this low comparison threshold circuit, and it is low that the threshold processing circuit is output as, i.e. output resets.
Be illustrated in figure 7 as the realization schematic diagram of the threshold processing circuit of the embodiment of the invention two.The output S0 of 010/101 pattern testing circuit is through 1 two paths of signals that is divided into single spin-echo of overdriving among the figure.Anti-phase road signal process R1, R3, the integrating circuit that C1 forms, signal S1 behind the integration deliver to an input of 4, one road signal of positive is through R2, R4, the integrating circuit that C2 forms, the signal S2 behind the integration are delivered to the lower comparative level of comparator 2 and and are compared.Signal S3 relatively delivers to or a door input of 3, with door 4 with signal S1 and S4 phase with, the signal of Xiang Yuhou is divided into two-way, one tunnel negate is exported S7 as input.Another road S5 turns back to or a door input of 3.With signal S3 phase or export afterwards S4 and be transmitted back to again input with door 4.Has higher upset thresholding with door 4.
The truth table of S1, S3 and S7 is as follows:
| S1 | S3 | S7 |
| 0 | 0 | 1 |
| 0 | 1 | 1 |
| 1 | 0 | Keep |
| 1 | 1 | 0 |
When signal was arranged, S1 was low level, and output S7 is high level, namely exports set.When not having signal, S1 becomes high level, and S2 is low level, and S3 is high level, and output S7 is low level, i.e. output resets.Suppose during blackout, input has noise, because the upset thresholding higher with door 4, for door 4, the S1 perseverance is high level, and comparator 2 has lower comparison threshold, even S3 is low level by the noise false triggering, according to truth table, state before output S7 still can keep, namely remain low level, noise can not make mistakenly set of circuit.
Be illustrated in figure 8 as the schematic diagram of burst clock and data recovery (BCDR) circuit of the embodiment of the invention two.BCDR adopts traditional " training data " to add the mode of PLL, by with one " training data ", when not having the data input, add the phase-locked loop input to keep phase-lock-ring output frequency constant, so that the capture time when accelerating the data arrival, the clock and data recovery of realization burst mode.Wherein inputting data and training data is switched by the signal deteching circuit control switch.
When not inputting the data arrival, signal deteching circuit can't detect signal, control switch switches to the training data end, make the 1.25G/2.5G/5GHz frequency of training of training data source output, be input to the input of clock and data recovery circuit, the clock and data recovery circuit adopts phase-locked loop to realize clock and data recovery.Frequency of training keeps the output frequency of phase-locked loop VCO stable, can not drift about.When signal arrived, signal deteching circuit detected the input data, and control switch switches to the input data terminal, sent simultaneously a signal designation to next stage.The input data communication device is crossed switch and is entered the clock and data recovery circuit with recovered clock and data.Because the frequency of the clock signal that the frequency of oscillation of clock and data recovery circuit VCO and input data are carried is basically identical, the phase-locked loop of clock and data recovery circuit only carries out phase-locked to the input data, the process that does not have Frequency Locking has reduced locking time of phase-locked loop so greatly.Can realize the clock and data recovery of burst mode.
Be illustrated in figure 9 as the schematic diagram of the embodiment of the invention two splitters.The embodiment of the invention adopts coupling capacitance to add that driver is divided into two-way with the voltage signal of preamplifier output, gives respectively 1G (GEPON) and 10G (10G EPON) branch road and processes.Adopt capacitive coupling can satisfy the requirement that the 10G/1G burst receives settling time, and adopt capacitive coupling, can make the decision threshold automatic centering, be in optimum state, make receiving sensitivity best, also the easiest in the realization.Driver adopts existing one-to-two driver, should have linear characteristic when small-signal, not affect the signal to noise ratio of output signal in its useful passband, affects as small as possible the sensitivity of receiver.
Figure 10 is the structural representation of the optical receiver of the embodiment of the invention three.Different with embodiment two is increased dynamic APD bias control circuit here, and photodetector only to adopt APD.
Dynamically the effect of APD bias control circuit is the deficiency that remedies the preamplifier dynamic range.When the dynamic range of preamplifier can not satisfy requiring of receiver dynamic range, can increase the dynamic range that dynamic APD bias control circuit is expanded receiver.Dynamically the APD bias control circuit detects the output of preamplifier, and default reference voltage relatively, produces the avalanche gain of control voltage control APD.When the light signal strength of input approaches or surpasses certain value, the output of preamplifier is approached or when surpassing default reference voltage, dynamically the APD bias control circuit begins to work.Dynamically the APD bias control circuit to reduce the avalanche gain of APD, makes the output current of APD can not surpass certain value by reducing the reversed bias voltage of APD, so that the stable output of preamplifier is near default reference voltage.Namely the light signal strength of input surpasses certain value, and the output of preamplifier no longer increases along with linearity, but is stabilized near the certain value, has greatly expanded the dynamic range of receiver.
Figure 11 is the structural representation of the optical receiver of the embodiment of the invention four.Here adopted reset signal, burst has been received to adopt the faster response time.Reset signal can be used for preamplifier, dynamic APD bias control circuit, the first and second main amplifiers.For burst receiver, after arriving, burst can experience a transient process, and then reach stable state and begin normal reception.Usually wish that transient process is more short better, so just requires the time constant of circuit as much as possible little.After circuit arrival stable state began to receive, the coded format in the data can affect the drift of data baseline." 1 " and " 0 " in receiving digital code stream occurs inhomogeneous, when " 1 " occurring connecting for a long time or connecting " 0 ", causes that the amplitude of flip-flop changes, and causes the drift of data baseline.In order to reduce baseline shift, wish that the time constant of circuit is the bigger the better.Can not surpass certain value in order to satisfy baseline shift, the time constant of circuit just can not be selected too littlely, just can not reach very fast to the response time of burst like this.
Reset signal is provided by the system of outside in the present embodiment.Preamplifier, dynamic APD bias control circuit, the first and second main amplifiers receive respectively reset signal, produce the control signal of oneself.When bursty data arrives, can adopt less time constant to reduce transient process like this, accelerate the response time that burst receives.After circuit arrival stable state begins to receive, then adopt larger time constant, to reduce the impact on the data baseline shift.The switching of time constant is then by preamplifier, dynamic APD bias control circuit, the control signal control that the first and second main amplifiers produce according to reset signal.
Figure 12 is the method schematic diagram that the light signal of the embodiment of the invention five receives.The step of present embodiment receiving optical signals is as follows:
Step 121: receiving optical signals, this light signal comprises the light signal of two kinds of different transmission rates at least;
Step 122: the light signal that receives is converted to voltage signal;
This step is specially: the light signal that receives is converted into current signal, again current signal is converted into voltage signal.
Step 123: the transmission rate of detectable voltage signals, according to testing result output control signal;
This step is specially: voltage signal is postponed to process with gate circuit, if it is corresponding with the time of delay to occur the transmission rate of predetermined pattern and described voltage signal in the described voltage signal, export an instantaneous high level of bit; Instantaneous high level is carried out integration, the signal behind the instantaneous high level integration and high threshold and the low threshold preset are compared; If the signal behind the integration greater than default high threshold, is exported the control signal of receiver voltage signal; If the signal behind the integration is lower than default low threshold, the control signal that the receiver voltage signal is forbidden in output.
Step 124: according to control signal control burst clock data recovering circuit, voltage signal is carried out clock and data recovery process.
Wherein, burst clock data recovering circuit comprises the frequency of training source of switch, phase-locked loop and generation frequency of training.
This step is specially: the switch reception control signal; When switch receive be the control signal of receiver voltage signal the time, switch is inputted phase-locked loop with voltage signal, phase-locked loop recovers clock and data from voltage signal; When switch receive when forbidding the control signal of receiver voltage signal, switch is frequency of training input phase-locked loop just, the frequency of locking phase-locked loop.
Present embodiment is realized burst clock data recovering circuit by the mode that adopts traditional " training data " to add phase-locked loop.When not having data inputs, frequency of training is added the phase-locked loop input keeping phase-lock-ring output frequency constant, so that the capture time when accelerating data and arriving, realize the clock and data recovery of burst mode.
The above; only for the better embodiment of the present invention, but protection scope of the present invention is not limited to this, anyly is familiar with those skilled in the art in the technical scope that the present invention discloses; the variation that can expect easily or replacement all should be encompassed within protection scope of the present invention.Therefore, protection scope of the present invention should be as the criterion with the protection range of claim.
Claims (5)
1. an optical receiver is characterized in that, comprising:
Receiving element is used for receiving optical signals, and described light signal comprises the light signal of two kinds of different transmission rates at least;
Converting unit is used for the light signal of described reception is converted to voltage signal;
Detecting unit is for detection of the transmission rate of described voltage signal, according to testing result output control signal;
Burst clock data recovering circuit is used for according to described control signal described voltage signal being carried out clock and data recovery and processes;
Described detecting unit specifically comprises:
The pattern detecting unit is used for described voltage signal is postponed to process with gate circuit, if it is corresponding with the time of delay to occur the transmission rate of predetermined pattern and described voltage signal in the described voltage signal, exports an instantaneous high level of bit;
The threshold processing unit is used for the instantaneous high level of described pattern detecting unit output is carried out integration, and the signal behind the instantaneous high level integration and high threshold and the low threshold preset are compared; If the signal behind the described integration greater than described default high threshold, is exported the control signal of receiver voltage signal; If the signal behind the described integration is lower than described default low threshold, the control signal that the receiver voltage signal is forbidden in output.
2. a kind of optical receiver as claimed in claim 1 is characterized in that, described detecting unit and described burst clock data recovering circuit can be integrated in the module.
3. a kind of optical receiver as claimed in claim 1 is characterized in that, described predetermined pattern comprises 010 and 101.
4. the method that light signal receives is characterized in that, comprising:
Receiving optical signals, described light signal comprises the light signal of two kinds of different transmission rates at least;
The light signal of described reception is converted to voltage signal;
Detect the transmission rate of described voltage signal, according to testing result output control signal;
According to described control signal control burst clock data recovering circuit, described voltage signal is carried out clock and data recovery process;
The transmission rate of the described voltage signal of described detection according to testing result output control signal, specifically comprises:
Described voltage signal is postponed to process with gate circuit, if it is corresponding with the time of delay to occur the transmission rate of predetermined pattern and described voltage signal in the described voltage signal, export an instantaneous high level of bit;
Described instantaneous high level is carried out integration, the signal behind the instantaneous high level integration and high threshold and the low threshold preset are compared; If the signal behind the described integration greater than described default high threshold, is exported the control signal of receiver voltage signal; If the signal behind the described integration is lower than described default low threshold, the control signal that the receiver voltage signal is forbidden in output.
5. the method for a kind of light signal reception as claimed in claim 4 is characterized in that described burst clock data recovering circuit comprises the frequency of training source of switch, phase-locked loop and generation frequency of training.
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Families Citing this family (14)
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|---|---|---|---|---|
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| CN106878834B (en) * | 2015-12-10 | 2020-07-31 | 深圳市中兴微电子技术有限公司 | Passive optical network compatible device and implementation method thereof and optical line terminal |
| CN105606136B (en) * | 2016-01-29 | 2017-09-01 | 中国电子科技集团公司第四十四研究所 | Optical frequency change-over circuit and method |
| CN107592111A (en) * | 2017-09-04 | 2018-01-16 | 中国电子科技集团公司第四十研究所 | A kind of anti-error frequency dividing of pulse-modulated signal designs circuit and method |
| CN112910564B (en) * | 2019-12-03 | 2022-02-01 | 烽火通信科技股份有限公司 | High-speed receiving circuit and high-speed transmitting-receiving circuit |
Citations (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN1283903A (en) * | 1999-08-05 | 2001-02-14 | 三星电子株式会社 | Optical receiver having no relation to bit rate, and receiving method thereof |
| CN1342003A (en) * | 2000-09-05 | 2002-03-27 | 三星电子株式会社 | Bit rate detecting circuit and calculating method for optical network |
| JP2005197881A (en) * | 2004-01-05 | 2005-07-21 | Nippon Telegr & Teleph Corp <Ntt> | Multiple speed burst optical signal receiver optimizing reception sensitivity |
-
2008
- 2008-04-03 CN CN 200810066603 patent/CN101552647B/en not_active Expired - Fee Related
Patent Citations (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN1283903A (en) * | 1999-08-05 | 2001-02-14 | 三星电子株式会社 | Optical receiver having no relation to bit rate, and receiving method thereof |
| CN1342003A (en) * | 2000-09-05 | 2002-03-27 | 三星电子株式会社 | Bit rate detecting circuit and calculating method for optical network |
| JP2005197881A (en) * | 2004-01-05 | 2005-07-21 | Nippon Telegr & Teleph Corp <Ntt> | Multiple speed burst optical signal receiver optimizing reception sensitivity |
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| CN101552647A (en) | 2009-10-07 |
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