CN101552647A - Method and device for receiving optical signals - Google Patents
Method and device for receiving optical signals Download PDFInfo
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- CN101552647A CN101552647A CN 200810066603 CN200810066603A CN101552647A CN 101552647 A CN101552647 A CN 101552647A CN 200810066603 CN200810066603 CN 200810066603 CN 200810066603 A CN200810066603 A CN 200810066603A CN 101552647 A CN101552647 A CN 101552647A
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Abstract
The invention discloses an optical receiver which comprises a receiving unit, a converting unit, a detecting unit and a burst clock data recovering circuit, wherein the receiving unit is used for receiving optical signals which at least comprise optical signals having two different transmission rates; the converting unit is used for converting the received optical signals to voltage signals; the detecting unit is used for detecting the transmission rates of the voltage signals and outputting control signals according to the detecting result; and the burst clock data recovering circuit is used for recovering the clock and the data for the voltage signals according to the control signals. Correspondingly, the invention also discloses a method for receiving optical signals. By the invention, not only time multiplexing signals with two rates of GEPON and 10G EPON can be received, but also fast synchronization and time saving can be realized.
Description
Technical field
The present invention relates to network communication field, specifically, relate to the method and apparatus that a kind of light signal receives.
Background technology
Passive optical network PON is a kind of Optical Fiber Transmission and access technology of point-to-multipoint, and its structure as shown in Figure 1.It is made up of the optical network unit ONU of the optical line terminal OLT of office's side, user side or Optical Network Terminal ONT and Optical Distribution Network ODN.Wherein, OLT is a down direction to the transmission direction of ONU, adopts the TDM mode, and OLT issues information broadcast each ONU continuously, and each ONU selects one's own Data Receiving; ONU adopts the TDMA mode to the up direction that is transmitted as of OLT, and promptly upstream data sends and happens suddenly, and different ONU take different ascending time slots, and a plurality of ONU share up link by time-multiplexed mode.
In order to utilize the fiber resource of existing GEPON system, following 10G EPON needs and the GEPON coexistence of systems, and in 10G/1G EPON symbiotic system, OLT must support the ONU of 10G, two kinds of speed of 1G.
Do not consider the lock in time of the critical component of many rate receivers in existing many speed optical receiver technology, take bigger time overhead, can't reach fast synchronously.
Summary of the invention
The technical problem that the embodiment of the invention will solve is: the method and apparatus that provides a kind of light signal to receive overcomes that many speed reception technique takies bigger time overhead in the existing 10G/1G EPON symbiotic system, can't reach synchronous shortcoming fast.
For solving the problems of the technologies described above, the embodiment of the invention provides a kind of optical receiver, comprising: receiving element, converting unit, detecting unit and burst clock data recovering circuit; Receiving element is used for receiving optical signals, and this light signal comprises the light signal of two kinds of different transmission rates at least; Converting unit, the light signal that is used for receiving is converted to voltage signal; Detecting unit is used for the transmission rate of detectable voltage signals, according to testing result output control signal; Burst clock data recovering circuit is used for according to control signal voltage signal being carried out clock and data recovery and handles.
Correspondingly, the method that the embodiment of the invention provides a kind of light signal to receive comprises: receiving optical signals, and this light signal comprises the light signal of two kinds of different transmission rates at least; The light signal that receives is converted to voltage signal; The transmission rate of detectable voltage signals is according to testing result output control signal; According to control signal control burst clock data recovering circuit, voltage signal is carried out clock and data recovery handle.
The technical scheme that is provided by the invention described above embodiment as can be seen, the invention provides the method and apparatus that a kind of light signal receives, be converted to voltage signal by the light signal that will receive, the transmission rate of detectable voltage signals, according to testing result output control signal, according to control signal control burst clock data recovering circuit voltage signal is carried out clock and data recovery and handle.Adopt technical scheme of the present invention, not only can receive two kinds of rate time-division multiplex signals of GEPON and 10G EPON, and can reach fast synchronously, reduce time overhead.
Description of drawings
Fig. 1 is the structural representation of EPON in the prior art;
Fig. 2 is the principle schematic of 10G/1G EPON coexistence of systems in the prior art;
Fig. 3 is the structural representation of the optical receiver of the embodiment of the invention one;
Fig. 4 is the structural representation of the optical receiver of the embodiment of the invention two;
Fig. 5 is the realization block diagram of the signal deteching circuit of the embodiment of the invention two;
Fig. 6 is the schematic diagram of 101/010 yard type testing circuit of the embodiment of the invention two;
Fig. 7 is the schematic diagram of the threshold processing circuit of the embodiment of the invention two;
Fig. 8 is the schematic diagram of the burst clock data recovering circuit of the embodiment of the invention two;
Fig. 9 is the schematic diagram of the splitter of the embodiment of the invention two;
Figure 10 is the structural representation of the optical receiver of the embodiment of the invention three;
Figure 11 is the structural representation of the optical receiver of the embodiment of the invention four;
Figure 12 is the method schematic diagram that the light signal of the embodiment of the invention five receives.
Embodiment
Adopting the embodiment of the invention, can realize the reception to the light signal of multiple different transmission rates, for convenience of description, below is that example describes with the light signal of GEPON and two kinds of speed of 10G EPON only.
Fig. 3 is the structural representation of the optical receiver of the embodiment of the invention one.This optical receiver comprises: receiving element, converting unit, detecting unit and burst clock data recovering circuit; Wherein, receiving element is used for receiving optical signals, and this light signal comprises the light signal of two kinds of different transmission rates at least; Converting unit, the light signal that is used for receiving is converted to voltage signal; Detecting unit is used for the transmission rate of detectable voltage signals, according to testing result output control signal; Burst clock data recovering circuit is used for according to control signal voltage signal being carried out clock and data recovery and handles.
Above-mentioned detecting unit and burst clock data recovering circuit can be integrated in the module.
Above-mentioned detecting unit specifically comprises: sign indicating number type detecting unit and threshold processing unit; Wherein, sign indicating number type detecting unit is used for voltage signal is postponed to handle with gate circuit, if it is corresponding with the time of delay to occur the transmission rate of predetermined sign indicating number type and voltage signal in the voltage signal, exports an instantaneous high level of bit; The threshold processing unit is used for the instantaneous high level of sign indicating number type detecting unit output is carried out integration, and the signal behind the instantaneous high level integration and high threshold and the low threshold preset are compared; If the signal behind the integration is greater than default high threshold, output receives the control signal of voltage signal; If the signal behind the integration is lower than default low threshold, output forbids receiving the control signal of voltage signal.
Above-mentioned burst clock data recovering circuit comprises switch, phase-locked loop and frequency of training source; Wherein, the frequency of training source is used to produce frequency of training; Switch is used to receive the control signal that detecting unit is exported; Based on the control signal that receives voltage signal, voltage signal is imported phase-locked loop; Based on the control signal of forbidding receiving voltage signal, frequency of training is imported phase-locked loop; Phase-locked loop is used for based on voltage signal, recovers clock and data from voltage signal; Based on frequency of training, the frequency of locking phase-locked loop.
Above-mentioned predetermined sign indicating number type comprises 010 and 101.
Present embodiment is realized burst clock data recovering circuit (BCDR) by the mode that adopts traditional " training data " to add phase-locked loop.When not having data inputs, frequency of training is added the phase-locked loop input keeping phase-lock-ring output frequency constant, so that the capture time when accelerating data and arriving, realize the clock and data recovery of burst mode.
Fig. 4 is the structural representation of the optical receiver of the embodiment of the invention two.Its work engineering is: photodetector is converted into current signal with the light signal that receives, and preamplifier amplifies the current signal that photodetector produces, and output voltage signal.Splitter is divided into two-way with the voltage signal of preamplifier output, gives 1G (GEPON) and 10G (10G EPON) branch road respectively and handles.Low pass filter filters out signal high-frequency noise in each branch road, and give main amplifier, main amplifier is adjudicated the analog signal that receives, and changes it into digital signal clearly.Signal deteching circuit judges whether to be this road signal, at this road signal duration of existence, can export a level, and index signal exists, thereby control burst clock and data recovery (BCDR) circuit working recovers the clock in the signal, and to the data shaping.
Above-mentioned photodetector can adopt avalanche photo diode (APD) or general photodiode PIN.PIN is under reversed bias voltage, and the electric current of its generation becomes certain proportionate relationship with irradiation luminous power thereon.APD utilizes the avalanche multiplication effect to make photoelectric current obtain multiplication, and remolding sensitivity PIN is big.Can select PIN or APD for use according to system's needs.The photodetector biasing circuit provides reversed bias voltage for APD or PIN.For APD, also need temperature-compensation circuit to be used to detect the APD ambient temperature, and produce control signal control photodetector biasing circuit, block voltage with variation of temperature with compensation APD.
Above-mentioned preamplifier can adopt trans-impedance amplifier (TIA).Trans-impedance amplifier amplifies the current signal that photodetector produces, and output voltage signal.The voltage signal of preamplifier output comprises the signal of 1G (GEPON) and 10G (10G EPON).
Splitter (active or passive splitter), the voltage signal that preamplifier is exported is divided into two-way, gives 1G (GEPON) and 10G (10G EPON) branch road respectively and handles.Because 10G (10G EPON) and 1G (GEPON) light signal adopt TDM multiplexing, take different ascending time slots, so preamplifier output is after the splitter shunt, and the voltage signal of 1G and two branch roads of 10G includes the signal of 1G and 10G speed TDM.
The Signal Processing process is as follows behind the splitter:
(1) when the 1G signal arrives, splitter shunts to 1G and 10G branch road with signal.
For the 1G branch road, the first low pass filter filters out signal high-frequency noise, to improve receiving sensitivity, and give first main amplifier, first main amplifier adopts limiting amplifier (LA), the 1G analog signal that receives is adjudicated, change it into digital signal clearly, give first signal deteching circuit and the first clock and data recovery circuit (BCDR) simultaneously.First signal deteching circuit can be exported a level at 1G signal duration of existence, and index signal exists.It is this road signal that first signal deteching circuit is judged, controls BCDR work, and a BCDR recovers the clock in the signal, and to the data shaping.Clock that recovers and the data after the shaping are fed to the back one-level and handle.First signal deteching circuit is exported a signal simultaneously and is indicated to the back one-level, the arrival of notice 1G signal.
For the 10G branch road, the 1G analog signal changes digital signal clearly into after through second low pass filter and second main amplifier, and gives secondary signal testing circuit and the 2nd BCDR.It is not this road signal that the secondary signal testing circuit is judged, forbids the 2nd BCDR work, exports an indication simultaneously and gives the back one-level, and notice is not this road signal.
(2) when the 10G signal arrives, splitter will shunt to 1G and 10G branch road by signal.
For the 1G branch road, because first low pass filter and the first main amplifier bandwidth are far smaller than the 10G signal bandwidth, the first signal deteching circuit cisco unity malfunction, and detect less than signal.It is not this road signal that first signal deteching circuit is judged, forbids BCDR work, exports an indication simultaneously and gives the back one-level, and notice is not this road signal.
For the 10G branch road, the second low pass filter filters out signal high-frequency noise is to improve receiving sensitivity, and give second main amplifier, second main amplifier adopts LA, the 10G analog-signal transitions that receives is digital signal clearly, and gives secondary signal testing circuit and the 2nd BCDR simultaneously.The secondary signal testing circuit can be exported a level at 10G signal duration of existence, and index signal exists.It is this road signal that the secondary signal testing circuit is judged, controls the 2nd BCDR work, and the 2nd BCDR recovers the clock in the signal, and to the data shaping.Clock that recovers and the data after the shaping are fed to the back one-level and handle.The secondary signal testing circuit is exported a signal simultaneously and is indicated to the back one-level, the arrival of notice 10G signal.
Be illustrated in figure 5 as the realization block diagram of the signal deteching circuit of the embodiment of the invention two, signal deteching circuit comprises 101/010 yard type testing circuit and threshold processing circuit.
When 101/010 yard type testing circuit detects in the data sign indicating number type that comprises " 010 " or " 101 ", and speed can export the instantaneous high level that a duration is a bit when consistent with this branch road speed, otherwise output low level.Be illustrated in figure 6 as the schematic diagram of 101/010 yard type testing circuit of the embodiment of the invention two, holding wire is single-ended or differential signal line among the figure.Input data S0 is divided into two same signals through driving (1).Wherein one road signal S1 delivers to an input of XOR (3), and another road signal postpones a bit time through postponing (2), and the signal S3 after the delay is sent to another input of XOR (3).Behind XOR (3), can realize detection to " 01 " or " 10 " of input data S0.The output S4 of XOR (3) is divided into two same signals through overdrive (4), wherein one road signal S5 deliver to the door (6) an input, another road signal postpones a bit time through postponing (5), and the signal S6 after the delay delivers to another input with door (6).By with door (6) after, can realize the detection of " 11 " to the signal S4 of XOR (3) output.The output S7 of entire circuit realizes the detection to " 010 " or " 101 " of input data S0.
When " 010 " or " 101 " sign indicating number type in signal, occurring, the high level that it is a bit that testing circuit is exported a duration, when occurring in the signal switching continuously (comprising continuous " 010 ", " 101 ") as " 010101.... ", testing circuit is exported high level continuously, up to the sign indicating number type that " 010 " or " 101 " no longer occurs, circuit is output as low.
The signal of 101/010 yard type testing circuit output of threshold processing processing of circuit, because when " 010101.... " switching occurring continuously in the input data, 101/010 yard type testing circuit continues the output high level, but when appearance " 010 " in the input data, " 101 " are relatively more rare, 101/010 yard high level that the output of type testing circuit is relatively more rare.For this relatively more rare high level is detected, need carry out integration to it, compare with a fixed level again.When the probability that occurs when " 010 " in the signal, " 101 " was low, the DC level behind 101/010 yard type testing circuit output signal integration was lower, and comparative level must be provided with lower, is output as height after guaranteeing relatively.But when the comparative level setting is low, occur noise easily to its false triggering, making does not have during the signal, can erroneous trigger produce high level yet.
Therefore the threshold processing circuit is provided with two comparison thresholds in the present embodiment.A higher comparison threshold is used for set, because in the lead code of input data, existing continuously, " 010101.... " switches, 101/010 yard type testing circuit continues the output high level, itself and a higher comparison threshold are compared, can guarantee that during lead code, the threshold processing circuit is output as height, promptly exports set.Can guarantee again when not having signal, can be by the noise false triggering.Another lower comparison threshold is used for signal is resetted.Because during the useful signal of input data, " 010 ", " 101 " occur relatively more rare, 101/010 yard high level that the output of type testing circuit is relatively more rare, it is carried out integration after, compare with a more low level comparison threshold, the output after the assurance relatively is continuously height again.And when blackout, low level appears in the output of this low comparison threshold circuit, and it is low that the threshold processing circuit is output as, i.e. output resets.
Be illustrated in figure 7 as the realization schematic diagram of the threshold processing circuit of the embodiment of the invention two.The output S0 of 010/101 yard type testing circuit 1 is divided into the opposite two paths of signals of phase place through overdriving among the figure.Anti-phase road signal process R1, R3, the integrating circuit that C1 forms, signal S1 behind the integration deliver to an input of 4, one road signal of positive is through R2, R4, the integrating circuit that C2 forms, the signal S2 behind the integration delivers to comparator 2 and a lower comparative level compares.Signal S3 relatively delivers to or an input of door 3, with door 4 with signal S1 and S4 with, the signal of Xiang Yuhou is divided into two-way, one tunnel negate is exported S7 as input.Another road S5 turns back to or a door input of 3.With signal S3 mutually or back output S4 be transmitted back to input with door 4 again.Has higher upset thresholding with door 4.
The truth table of S1, S3 and S7 is as follows:
| S1 | S3 | S7 |
| 0 | 0 | 1 |
| 0 | 1 | 1 |
| 1 | 0 | Keep |
| 1 | 1 | 0 |
When signal was arranged, S1 was a low level, and output S7 is a high level, promptly exports set.When not having signal, S1 becomes high level, and S2 is a low level, and S3 is a high level, and output S7 is a low level, i.e. output resets.Suppose during blackout, input has noise, because the upset thresholding higher with door 4, for door 4, the S1 perseverance is a high level, and comparator 2 has lower comparison threshold, even S3 is a low level by the noise false triggering, according to truth table, state before output S7 still can keep, promptly remain low level, noise can not make circuit set mistakenly.
Be illustrated in figure 8 as the schematic diagram of burst clock and data recovery (BCDR) circuit of the embodiment of the invention two.BCDR adopts traditional " training data " to add the mode of PLL, by with one " training data ", when not having the data input, add the phase-locked loop input to keep phase-lock-ring output frequency constant, so that the capture time when accelerating the data arrival, the clock and data recovery of realization burst mode.Wherein importing data and training data is switched by the signal deteching circuit control switch.
When not importing the data arrival, signal deteching circuit detects less than signal, control switch switches to the training data end, make the 1.25G/2.5G/5GHz frequency of training of training data source output, be input to the input of clock and data recovery circuit, the clock and data recovery circuit adopts phase-locked loop to realize clock and data recovery.Frequency of training keeps the output frequency of phase-locked loop VCO stable, can not drift about.When signal arrived, signal deteching circuit detected the input data, and control switch switches to the input data terminal, sent a signal simultaneously and was indicated to next stage.The input data enter the clock and data recovery circuit with recovered clock and data by switch.Because the frequency basically identical of the clock signal of the frequency of oscillation of clock and data recovery circuit VCO and input data carry, the phase-locked loop of clock and data recovery circuit only carries out phase-locked to the input data, the process that does not have frequency lock has reduced locking time of phase-locked loop so greatly.Can realize the clock and data recovery of burst mode.
Be illustrated in figure 9 as the schematic diagram of the embodiment of the invention two splitters.The embodiment of the invention adopts coupling capacitance to add that driver is divided into two-way with the voltage signal of preamplifier output, gives 1G (GEPON) and 10G (10G EPON) branch road respectively and handles.Adopt capacitive coupling can satisfy the requirement that the 10G/1G burst receives settling time, and adopt capacitive coupling, can make decision threshold placed in the middle automatically, be in optimum state, make receiving sensitivity the best, also the easiest in the realization.Driver adopts existing one-to-two driver, should have linear characteristic when small-signal, not influence the signal to noise ratio of output signal in its useful passband, influences the sensitivity of receiver as small as possible.
Figure 10 is the structural representation of the optical receiver of the embodiment of the invention three.Different with embodiment two is increased dynamic APD bias control circuit here, and photodetector only to adopt APD.
Dynamically the effect of APD bias control circuit is the deficiency that remedies the preamplifier dynamic range.When the dynamic range of preamplifier can not satisfy requiring of receiver dynamic range, can increase the dynamic range that dynamic APD bias control circuit is expanded receiver.Dynamically the output of APD bias control circuit detection preamplifier and default reference voltage compare, and produce the avalanche gain of control voltage control APD.When the light signal strength of input near or surpass certain value, the output that makes preamplifier near or when surpassing default reference voltage, dynamically the APD bias control circuit begins to work.Dynamically the APD bias control circuit to reduce the avalanche gain of APD, makes the output current of APD can not surpass certain value, so that the output of preamplifier is stabilized near the default reference voltage by reducing the reversed bias voltage of APD.Promptly Shu Ru light signal strength surpasses certain value, and the output of preamplifier no longer increases along with linearity, but is stabilized near the certain value, has expanded the dynamic range of receiver greatly.
Figure 11 is the structural representation of the optical receiver of the embodiment of the invention four.Here adopted reset signal, burst has been received to adopt the response time faster.Reset signal can be used for preamplifier, dynamic APD bias control circuit, first and second main amplifiers.For burst receiver, after arriving, burst can experience a transient process, and reach stable state then and begin normal reception.Usually wish that transient process is short more good more, so just requires the time constant of circuit as much as possible little.After circuit arrival stable state began to receive, the coded format in the data can influence the drift of data baseline." 1 " and " 0 " in receiving digital code stream occurs inhomogeneous, when " 1 " occurring connecting for a long time or connecting " 0 ", causes that the amplitude of flip-flop changes, and causes the drift of data baseline.In order to reduce baseline shift, wish that the time constant of circuit is the bigger the better.Can not surpass certain value in order to satisfy baseline shift, the time constant of circuit just can not be selected too for a short time, and the response time to burst just can not reach very fast like this.
Reset signal is provided by the system of outside in the present embodiment.Preamplifier, dynamic APD bias control circuit, first and second main amplifiers receive reset signal respectively, produce the control signal of oneself.When bursty data arrives, can adopt less time constant like this, accelerate the response time that burst receives to reduce transient process.After circuit arrival stable state begins to receive, then adopt bigger time constant, to reduce influence to the data baseline shift.The switching of time constant is then by preamplifier, dynamic APD bias control circuit, the control signal control that first and second main amplifiers produce according to reset signal.
Figure 12 is the method schematic diagram that the light signal of the embodiment of the invention five receives.The step of present embodiment receiving optical signals is as follows:
Step 121: receiving optical signals, this light signal comprises the light signal of two kinds of different transmission rates at least;
Step 122: the light signal that receives is converted to voltage signal;
This step is specially: the light signal that receives is converted into current signal, again current signal is converted into voltage signal.
Step 123: the transmission rate of detectable voltage signals, according to testing result output control signal;
This step is specially: voltage signal is postponed to handle with gate circuit, if it is corresponding with the time of delay to occur the transmission rate of predetermined sign indicating number type and described voltage signal in the described voltage signal, export an instantaneous high level of bit; Instantaneous high level is carried out integration, the signal behind the instantaneous high level integration and high threshold and the low threshold preset are compared; If the signal behind the integration is greater than default high threshold, output receives the control signal of voltage signal; If the signal behind the integration is lower than default low threshold, output forbids receiving the control signal of voltage signal.
Step 124:, voltage signal is carried out clock and data recovery handle according to control signal control burst clock data recovering circuit.
Wherein, burst clock data recovering circuit comprises the frequency of training source of switch, phase-locked loop and generation frequency of training.
This step is specially: switch receives control signal; When switch receive when receiving the control signal of voltage signal, switch is imported phase-locked loop with voltage signal, phase-locked loop recovers clock and data from voltage signal; When switch receive when forbidding receiving the control signal of voltage signal, switch is frequency of training input phase-locked loop just, the frequency of locking phase-locked loop.
Present embodiment is realized burst clock data recovering circuit by the mode that adopts traditional " training data " to add phase-locked loop.When not having data inputs, frequency of training is added the phase-locked loop input keeping phase-lock-ring output frequency constant, so that the capture time when accelerating data and arriving, realize the clock and data recovery of burst mode.
The above; only for the preferable embodiment of the present invention, but protection scope of the present invention is not limited thereto, and anyly is familiar with those skilled in the art in the technical scope that the present invention discloses; the variation that can expect easily or replacement all should be encompassed within protection scope of the present invention.Therefore, protection scope of the present invention should be as the criterion with the protection range of claim.
Claims (9)
1. an optical receiver is characterized in that, comprising:
Receiving element is used for receiving optical signals, and described light signal comprises the light signal of two kinds of different transmission rates at least;
Converting unit is used for the light signal of described reception is converted to voltage signal;
Detecting unit is used to detect the transmission rate of described voltage signal, according to testing result output control signal;
Burst clock data recovering circuit is used for according to described control signal described voltage signal being carried out clock and data recovery and handles.
2. a kind of optical receiver as claimed in claim 1 is characterized in that, described detecting unit and described burst clock data recovering circuit can be integrated in the module.
3. a kind of optical receiver as claimed in claim 2 is characterized in that, described detecting unit specifically comprises:
Sign indicating number type detecting unit is used for described voltage signal is postponed to handle with gate circuit, if it is corresponding with the time of delay to occur the transmission rate of predetermined sign indicating number type and described voltage signal in the described voltage signal, exports an instantaneous high level of bit;
The threshold processing unit is used for the instantaneous high level of described sign indicating number type detecting unit output is carried out integration, and the signal behind the instantaneous high level integration and high threshold and the low threshold preset are compared; If the signal behind the described integration is greater than described default high threshold, output receives the control signal of voltage signal; If the signal behind the described integration is lower than described default low threshold, output forbids receiving the control signal of voltage signal.
4. a kind of optical receiver as claimed in claim 3 is characterized in that, described burst clock data recovering circuit comprises switch, phase-locked loop and frequency of training source;
Described frequency of training source is used to produce frequency of training;
Described switch is used to receive the control signal that described detecting unit is exported; Based on the control signal of described reception voltage signal, described voltage signal is imported described phase-locked loop; Based on the described control signal of forbidding receiving voltage signal, described frequency of training is imported described phase-locked loop;
Described phase-locked loop is used for recovering clock and data based on described voltage signal from described voltage signal; Based on described frequency of training, lock the frequency of described phase-locked loop.
5. a kind of optical receiver as claimed in claim 3 is characterized in that, described predetermined sign indicating number type comprises 010 and 101.
6. the method that light signal receives is characterized in that, comprising:
Receiving optical signals, described light signal comprises the light signal of two kinds of different transmission rates at least;
The light signal of described reception is converted to voltage signal;
Detect the transmission rate of described voltage signal, according to testing result output control signal;
According to described control signal control burst clock data recovering circuit, described voltage signal is carried out clock and data recovery handle.
7. the method that a kind of light signal as claimed in claim 6 receives is characterized in that, the transmission rate of the described voltage signal of described detection according to testing result output control signal, specifically comprises:
Described voltage signal is postponed to handle with gate circuit,, export an instantaneous high level of bit if it is corresponding with the time of delay to occur the transmission rate of predetermined sign indicating number type and described voltage signal in the described voltage signal;
Described instantaneous high level is carried out integration, the signal behind the instantaneous high level integration and high threshold and the low threshold preset are compared; If the signal behind the described integration is greater than described default high threshold, output receives the control signal of voltage signal; If the signal behind the described integration is lower than described default low threshold, output forbids receiving the control signal of voltage signal.
8. the method that a kind of light signal as claimed in claim 7 receives is characterized in that described burst clock data recovering circuit comprises the frequency of training source of switch, phase-locked loop and generation frequency of training.
9. the method that a kind of light signal as claimed in claim 8 receives is characterized in that, describedly described voltage signal is carried out clock and data recovery handle according to described control signal control burst clock data recovering circuit, specifically comprises:
Described switch receives described control signal; When described switch receive be the control signal of described reception voltage signal the time, described switch is imported described phase-locked loop with described voltage signal, described phase-locked loop recovers clock and data from described voltage signal; When described switch receive for described when forbidding receiving the control signal of voltage signal, the just described frequency of training of described switch is imported described phase-locked loop, locks the frequency of described phase-locked loop.
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| KR100303315B1 (en) * | 1999-08-05 | 2001-11-01 | 윤종용 | Optical receivers with bit-rate independent clock and data recovery and method thereof |
| KR100342521B1 (en) * | 2000-09-05 | 2002-06-28 | 윤종용 | Bit-rate detection device of optical receiver and method thereof |
| JP4204984B2 (en) * | 2004-01-05 | 2009-01-07 | 日本電信電話株式会社 | Multi-speed burst optical signal receiver with optimized reception sensitivity. |
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