CN100446125C - Nonvolatile storage unit in high speed - Google Patents
Nonvolatile storage unit in high speed Download PDFInfo
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- CN100446125C CN100446125C CNB2006100622861A CN200610062286A CN100446125C CN 100446125 C CN100446125 C CN 100446125C CN B2006100622861 A CNB2006100622861 A CN B2006100622861A CN 200610062286 A CN200610062286 A CN 200610062286A CN 100446125 C CN100446125 C CN 100446125C
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Abstract
A high speed storing unit of nonvolatile type is prepared as connecting grid of the first FET to line selected line and one of source / drain (SD) electrodes on the first FET to column selected line as well as another one to grid of the second FET and one of SD electrodes of the third floating gate FET (TTFGFET), connecting one of SD electrodes of the second FET to grid of TTFGFET and leading out another one to form programmable end, forming one being not connected to the first FET and being one of SD electrodes on TTFGFET to be precharge end, carrying out stored information transfer between the second FET and TTFGFET through different state of external connection at two said ends.
Description
Technical field
The present invention relates to storer, more particularly, the non-volatile high-speed memory that relates to a kind of Nonvolatile storage unit in high speed and use described storage unit.
Background technology
Semiconductor memory is for being widely used in a kind of device in fields such as computing machine, communication at present.The semiconductor memory utilization has the semiconductor circuit storing digital information of memory characteristic, can be divided into volatile memory and nonvolatile memory according to its persistence of preserving data.Volatile memory-elements have access speed fast, can unordered random access, the data power down characteristics such as promptly loses, common volatile memory has SRAM, DRAM, SDRAM, DDR, RAMBUS etc.Nonvolatile memory has the data power down can preserve, can repeat characteristics such as erasable, write time is long for a long time, and common nonvolatile memory has FLASH, EPROM, EEPROM etc.
The DRAM storer utilizes the characteristic of capacitive charge storage to store digital signal, that its storage unit has is simple in structure, cost is low, access speed is fast, can unordered random access etc. characteristics.The structure of DRAM basic unit of storage is made of a transistor and a capacitor as shown in Figure 1, and the state of capacitor has determined that the logic state of this DRAM unit is " 1 " or " 0 ".Capacitor can be stored certain amount of electrons or electric charge, and the capacitor of charging is considered to " 1 " in logic in digital and electronic, and the capacitor of " sky " is then thought " 0 " in logic.The unendurable maintenance charge stored of capacitor, so need regularly charging to replenish the electric charge that leaks, this is refreshing of DRAM storage unit.This storage unit needs continuous periodic refreshing, could keep temporary data, generally refreshes to have taken 6% of the working time.Simultaneously, the impulse electricity of capacitor needs the regular hour, though for capacitor this time very short, have only about 0.2-0.18 delicate, during this in this storage unit can not carry out accessing operation, this can cause the delay of data read.
The SRAM storer has not to be needed to refresh, access does not have characteristics such as time-delay, its basic structure as shown in Figure 2, constitute a storage unit by six transistors of T1-T6, form a rest-set flip-flop, make rest-set flip-flop be turned to the R attitude by data line then or the S attitude is represented data " 0 " or " 1 " respectively, thereby reach the purpose of storage data.The SRAM storage unit equally after power down data can't preserve, and need six transistors, the cost height, the circuit complexity, capacity improves difficulty.
The Flash storer has that the power down data are not lost, access does not have characteristics such as time-delay.The basic storage organization of Flash is shown in Fig. 3 A and 3B, the Flash storage unit has been used special floating boom field effect transistor, utilize high voltage (12V) that electric charge is sucked floating boom or from floating boom, remove " 1 " or " 0 " state express the storage data, thus the storage of the information of realization.Under the situation of power down, the electric charge on this field effect transistor floating boom can not disappear, so information still can be preserved.But the write cycle of Flash is very long, must wipe earlier before writing, and causes random writing very slow, and is slower more than 1000 times than DRAM.
Summary of the invention
The technical problem to be solved in the present invention is, at above-mentioned the deficiencies in the prior art, proposes a kind of Nonvolatile storage unit in high speed, keeps quick, the random-access characteristics of similar DRAM when powering on, can the long preservation data after power down.
The technical solution adopted for the present invention to solve the technical problems is: propose a kind of Nonvolatile storage unit in high speed, it is characterized in that, comprise first field effect transistor, second field effect transistor and the 3rd floating boom field effect transistor; The grid of first field effect transistor is connected with the row route selection, among both one of the source electrode of first field effect transistor and drain electrode is connected with the column selection line, and another grid with second field effect transistor is connected and is connected with the source electrode of the 3rd floating boom field effect transistor and of draining among both; The source electrode of second a field effect transistor and drain electrode grid with the 3rd floating boom field effect transistor among both is connected, and another is drawn and form to programme holds; The source electrode of the 3rd floating boom field effect transistor and drain electrode among both is not connected one with first field effect transistor draw formation precharge end; By described programming end and the external different conditions of precharge end, carry out the transfer of canned data between described second field effect transistor and described the 3rd floating boom field effect transistor.
In above-mentioned Nonvolatile storage unit in high speed, when described programming end ground connection and described precharge termination working voltage source, by the control signal in the row route selection first field effect transistor is disconnected, if store then the 3rd floating boom field effect transistor conducting of electric charge, make the grid source electrode/grid leak electrode capacitance charging of second field effect transistor in the floating boom of the 3rd floating boom field effect transistor.
In above-mentioned Nonvolatile storage unit in high speed, when described programming termination negative high voltage source and described precharge end ground connection, by the control signal in the row route selection first field effect transistor is disconnected, if store the then second field effect transistor conducting of electric charge, remove the interior electric charge of floating boom of the 3rd floating boom field effect transistor on the grid source electrode/grid leak electrode capacitance of second field effect transistor.
In above-mentioned Nonvolatile storage unit in high speed, when described programming end ground connection and described precharge end are unsettled, the 3rd floating boom field effect transistor disconnects, and the grid source electrode of first field effect transistor and second field effect/grid leak electrode capacitance constitutes the DRAM unit and comes storing data information.
In above-mentioned Nonvolatile storage unit in high speed, when described programming termination positive high voltage source and described precharge end ground connection, by the control signal in the row route selection first field effect transistor is disconnected, if store the then second field effect transistor conducting of electric charge, electric charge is entered in the floating boom of the 3rd floating boom field effect transistor on the grid source electrode/grid leak electrode capacitance of second field effect transistor.
In above-mentioned Nonvolatile storage unit in high speed, described first field effect transistor and second field effect transistor are enhancement mode N-channel MOS field effect transistor or enhancement mode P channel MOS field effect transistor.
The present invention also proposes a kind of non-volatile high-speed memory, comprising:
Each storage unit in the memory cell array, described memory cell array comprises first field effect transistor, second field effect transistor and the 3rd floating boom field effect transistor; The grid of first field effect transistor is connected with the row route selection, among both one of the source electrode of first field effect transistor and drain electrode is connected with the column selection line, and another grid with second field effect transistor is connected and is connected with the source electrode of the 3rd floating boom field effect transistor and of draining among both; The source electrode of second a field effect transistor and drain electrode grid with the 3rd floating boom field effect transistor among both is connected, and another is drawn and form to programme holds; The source electrode of the 3rd floating boom field effect transistor and drain electrode among both is not connected one with first field effect transistor draw formation precharge end;
The programming end of all storage unit is connected in parallel respectively with the precharge end and is in the same place in the described memory cell array, by described programming end and the external different conditions of precharge end, carry out the transfer of canned data between described second field effect transistor and described the 3rd floating boom field effect transistor.
In above-mentioned non-volatile high-speed memory, when described programming end ground connection and described precharge termination working voltage source, by the control signal in the row route selection first field effect transistor in the described storage unit is disconnected, if store then the 3rd floating boom field effect transistor conducting of electric charge, make the grid source electrode/grid leak electrode capacitance charging of second field effect transistor in the floating boom of the 3rd floating boom field effect transistor.
In above-mentioned non-volatile high-speed memory, when described programming termination negative high voltage source and described precharge end ground connection, by the control signal in the row route selection first field effect transistor in the described storage unit is disconnected, if store the then second field effect transistor conducting of electric charge, remove the interior electric charge of floating boom of the 3rd floating boom field effect transistor on the grid source electrode/grid leak electrode capacitance of second field effect transistor.
In above-mentioned non-volatile high-speed memory, when described programming end ground connection and described precharge end are unsettled, the 3rd floating boom field effect transistor in the described storage unit disconnects, and the grid source electrode of first field effect transistor and second field effect/grid leak electrode capacitance constitutes the DRAM unit and comes storing data information.
In above-mentioned non-volatile high-speed memory, when described programming termination positive high voltage source and described precharge end ground connection, by the control signal in the row route selection first field effect transistor in the described storage unit is disconnected, if store the then second field effect transistor conducting of electric charge, electric charge is entered in the floating boom of the 3rd floating boom field effect transistor on the grid source electrode/grid leak electrode capacitance of second field effect transistor.
The storer of implementing Nonvolatile storage unit in high speed of the present invention and constituting by this storage unit, have following beneficial effect: non-volatile high-speed memory of the present invention possesses the random access speed identical with DRAM under power-up state, possesses the characteristic of nonvolatile memory long preservation data after the power down; Precharge time from the power-down state to the power-up state is extremely short, the time compole of preserving mass data during power down is short, can in the time of Millisecond, preserve data, therefore can under the unsettled situation of power supply, improve the reliability of communication system or computer system greatly; Non-volatile high-speed memory cost of the present invention is low, and its use cost only is half of SRAM of same capability, and the quantity of equal chip area storage available is then Duoed one times than SRAM.
Description of drawings
The invention will be further described below in conjunction with drawings and Examples, in the accompanying drawing:
Fig. 1 is the structural representation of existing DRAM storage unit;
Fig. 2 is the structural representation of existing SRAM storage unit;
Fig. 3 A is the structural representation of the floating boom field effect transistor of existing Flash storer use;
Fig. 3 B be the floating boom field effect transistor used of existing Flash storer circuit diagram;
Fig. 4 is the structural representation of Nonvolatile storage unit in high speed of the present invention;
Fig. 5 is the synoptic diagram of an embodiment of Nonvolatile storage unit in high speed of the present invention at pre-charge state (Charge);
Fig. 6 is an embodiment shown in Figure 5 synoptic diagram at erase status (Erase);
Fig. 7 is an embodiment shown in Figure 5 synoptic diagram at the state of working on power (DRAM);
Fig. 8 is an embodiment shown in Figure 5 synoptic diagram at power down preservation state (BURN).
Embodiment
The non-volatile high-speed memory that the present invention proposes a kind of Nonvolatile storage unit in high speed and uses described storage unit, each storage unit is used two common field effect transistor and a floating boom field effect transistor, quick, the random-access characteristics that have similar DRAM when working on power can the long preservation data after power down.
Fig. 4 is the structural representation of Nonvolatile storage unit in high speed of the present invention.As shown in Figure 4, this storage singly comprises the first field effect transistor Q1, the second field effect transistor Q2 and the 3rd floating boom field effect transistor Q3.The grid of the first field effect transistor Q1 is connected with row route selection 20, among both one is connected with column selection line 10 for the source electrode of the first field effect transistor Q1 and drain electrode, another grid with the second field effect transistor Q2 is connected, and is connected with among both one of the source electrode of the 3rd floating boom field effect transistor Q3 and drain electrode.The source electrode of the second a field effect transistor Q2 and drain electrode grid with the 3rd floating boom field effect transistor Q3 among both is connected, and another is drawn and form to programme holds 30.The source electrode of the 3rd floating boom field effect transistor Q3 and drain electrode is not connected among both with first field effect transistor another draw formation precharge end 40.As shown in Figure 4, the programming end (30 and 30 ') of a plurality of storage unit and precharge end (40 and 40 ') are connected in parallel respectively and are in the same place, and constitute the memory cell array of the non-volatile high-speed memory of the present invention.During use, described programming end (30 and 30 ') and precharge end (40 and 40 ') can external different voltage sources or unsettled, thereby change the field effect transistor state in each storage unit, the storage organization of the similar DRAM that realization is made of the first field effect transistor Q1 and the second field effect transistor Q2, or realize the storage organization of the similar Flash that constitutes by the 3rd floating boom field effect transistor Q3, and realize powering on and power-down state under the transfer of information between these two kinds of storage organizations.Wherein, the first field effect transistor Q1 and the second field effect transistor Q2 are common field effect transistor, for example, can be enhancement mode N-channel MOS field effect transistor or enhancement mode P channel MOS field effect transistor.The 3rd floating boom field effect transistor Q3 is identical with the floating boom field effect transistor of use in the existing Flash storer, and the floating boom in it can be preserved electric charge when power down.Row route selection 20 is used to carry out the selection of basic unit of storage, and column selection line 10 is used to input or output data, interior identical of both functions and existing DRAM storer.Programming end (30 and 30 ') provides program voltage for this storage unit, and precharge end (40 and 40 ') is the charging control end of this storage unit.Specifically introduce each duty of Nonvolatile storage unit in high speed of the present invention below with reference to an embodiment.
When storage unit of the present invention powers on, at first need electric capacity precharge, in the electric capacity with information transfer to the second field effect transistor Q2 of the 3rd floating boom field effect transistor Q3 stored to the second field effect transistor Q2.Fig. 5 is the synoptic diagram of an embodiment of Nonvolatile storage unit in high speed of the present invention at pre-charge state (Charge).Among the embodiment shown in Figure 5, the first field effect transistor Q1 and the second field effect transistor Q2 all adopt enhancement mode N-channel MOS field effect transistor, and the 3rd floating boom field effect transistor Q3 also is a N raceway groove floating boom field effect transistor.As shown in Figure 5, the grid G 1 of the first field effect transistor Q1 is connected with row route selection 20, and the drain D 1 of the first field effect transistor Q1 is connected with column selection line 10, and source S 1 is connected with the grid G 2 of the second field effect transistor Q2 and the drain D 3 of the 3rd floating boom field effect transistor Q3.The source S 2 of the second field effect transistor Q2 is connected with the grid G 3 of the 3rd floating boom field effect transistor Q3, and drain D 2 is drawn and formed programming end 30.The drain D 3 of the 3rd floating boom field effect transistor Q3 is drawn and is formed precharge end 40.By prior art as can be known, under the situation that source electrode and substrate do not link together, the source electrode of metal-oxide-semiconductor field effect transistor and drain electrode can be exchanged, so the connected mode of the source electrode of three field effect transistor in the storage unit of the present invention and drain electrode is not limited to shown in Figure 5.
As shown in Figure 5, during pre-charge state, 30 ground connection are held in the programming of this storage unit, and precharge end 40 meets working voltage source Vcc.Under this state, utilize the control signal of row route selection 20 that the field effect transistor Q1 that wins is disconnected.If on the floating boom of the 3rd floating boom field effect transistor Q3 electric charge (promptly preserving data message) is arranged at this moment, then the 3rd floating boom field effect transistor Q3 is with conducting, operating voltage Vcc will be added on the grid G 2 of the second field effect transistor Q2, thereby make grid leak electrode capacitance (G2-D2) charging of the second field effect transistor Q2; If neutral on the floating boom of the 3rd floating boom field effect transistor Q3, then the 3rd not conducting of floating boom field effect transistor Q3, the electric capacity of the second field effect transistor Q2 does not charge.The information that so just can realize the floating boom stored of the 3rd floating boom field effect transistor Q3 shifts to the second field effect transistor Q2.
After information transfer in the 3rd floating boom field effect transistor Q3 is given the second field effect transistor Q2, need be with the information erasing in the Q3.Fig. 6 is an embodiment shown in Figure 5 synoptic diagram at erase status (Erase).As shown in Figure 6, under erase status, the programming end 30 of this storage unit meets negative polarity high pressure program voltage Vp-, and precharge end 40 ground connection utilize the control signal of row route selection 20 that the first field effect transistor Q1 is disconnected.At this moment, if store electric charge (the floating boom internal memory of promptly representing Q3 contains informational needs and wipes) on the grid leak electrode capacitance (G2-D2) of the second field effect transistor Q2, the then second field effect transistor Q2 conducting, negative high voltage Vp-is added in the grid G 3 of the 3rd floating boom field effect transistor Q3, thereby the interior electric charge of floating boom of the 3rd floating boom field effect transistor Q3 was eliminated in the time of Millisecond, reaches the purpose of wiping.
Fig. 7 is an embodiment shown in Figure 5 synoptic diagram at the state of working on power (DRAM).As shown in Figure 7, under the DRAM duty, the precharge end 40 of this storage unit is unsettled, programming end 30 ground connection.At this moment, the 3rd floating boom field effect transistor Q3 is disconnected, and cuts little ice.The grid leak electrode capacitance (G2-D2) of the first field effect transistor Q1 and the second field effect transistor Q2 constitutes an existing DRAM storage unit, by grid leak electrode capacitance (G2-D2) stored charge of the second field effect transistor Q2, represents stored data " 1 " or " 0 ".Effect and the transistor in existing DRAM storage unit of the first field effect transistor Q1 under this state is identical.At this moment, this storage unit possesses the quick access characteristic identical with the DRAM storage unit, and its working method is identical with existing DRAM storage unit.
Because the information of the grid leak utmost point (G2-D2) capacitor memory of second field effect transistor Q2 storage can be lost after power down, during storage unit power down therefore of the present invention, in need floating boom, so that long preservation with information transfer to the three floating boom field effect transistor Q3 of the second field effect transistor Q2 stored.Fig. 8 is an embodiment shown in Figure 5 synoptic diagram at power down preservation state (BURN).As shown in Figure 8, under the BURN state, the programming end 30 of this storage unit meets positive polarity high pressure program voltage Vp+, precharge end 40 ground connection, and utilize the control signal of row route selection 20 that Q1 is disconnected.At this moment, if preserve electric charge on the grid leak electrode capacitance (G2-D2) of the second field effect transistor Q2, then the second field effect transistor Q2 makes positive high voltage Vp+ be added on the 3rd floating boom field effect transistor Q3 conducting, thereby electric charge is entered in the floating boom of the 3rd floating boom field effect transistor Q3; Otherwise if do not have electric charge on the grid leak electrode capacitance (G2-D2) of the second field effect transistor Q2, then the second field effect transistor Q2 can conducting, and electric charge can not enter the floating boom of the 3rd floating boom field effect transistor Q3.Like this, the last canned data of the grid leak electrode capacitance (G2-D2) of the second field effect transistor Q2 is transferred in the floating boom of the 3rd floating boom field effect transistor Q3 in the time of just can realizing power down, and this information can not lost yet after the power down.
Among another embodiment of Nonvolatile storage unit in high speed of the present invention, the first field effect transistor Q1 and the second field effect transistor Q2 can adopt enhancement mode P channel MOS field effect transistor, and the 3rd floating boom field effect transistor Q3 can adopt P raceway groove floating boom field effect transistor.In this case, annexation and the embodiment shown in Fig. 5-8 between three field effect transistor are roughly the same, and just the programming end is just in time opposite with the access of precharge end under each state.For example, under the pre-charge state, the programming termination working voltage source Vcc of this storage unit, precharge end ground connection; Under the erase status, the programming termination positive polarity high pressure program voltage Vp+ of this storage unit, precharge termination working power Vcc; Under the DRAM duty, the precharge end of this storage unit is unsettled, programming termination working power Vcc; Under the BURN state, the programming termination negative polarity high pressure program voltage Vp-of this storage unit, precharge termination working power Vcc.
Because the programming end of all storage unit and precharge end are in parallel respectively in the storer of the present invention, so writing simultaneously of all storage unit carried out, the information write time of whole storer will finish in the time that writes a Flash unit.If the storage chip capacity that is made of storage unit of the present invention is greater than 1MB, then its writing speed will be more than 100 ten thousand times of equal capacity Flash unit.
Claims (11)
1, a kind of Nonvolatile storage unit in high speed is characterized in that, comprises first field effect transistor, second field effect transistor and the 3rd floating boom field effect transistor; The grid of first field effect transistor is connected with the row route selection, among both one of the source electrode of first field effect transistor and drain electrode is connected with the column selection line, and another grid with second field effect transistor is connected and is connected with the source electrode of the 3rd floating boom field effect transistor and of draining among both; The source electrode of second a field effect transistor and drain electrode grid with the 3rd floating boom field effect transistor among both is connected, and another is drawn and form to programme holds; The source electrode of the 3rd floating boom field effect transistor and drain electrode among both is not connected one with first field effect transistor draw formation precharge end; By described programming end and the external different conditions of precharge end, carry out the transfer of canned data between described second field effect transistor and described the 3rd floating boom field effect transistor.
2, Nonvolatile storage unit in high speed according to claim 1, it is characterized in that, when described programming end ground connection and described precharge termination working voltage source, by the control signal in the row route selection first field effect transistor is disconnected, if store then the 3rd floating boom field effect transistor conducting of electric charge, make the grid source electrode/grid leak electrode capacitance charging of second field effect transistor in the floating boom of the 3rd floating boom field effect transistor.
3, Nonvolatile storage unit in high speed according to claim 1, it is characterized in that, when described programming termination negative high voltage source and described precharge end ground connection, by the control signal in the row route selection first field effect transistor is disconnected, if store the then second field effect transistor conducting of electric charge, remove the interior electric charge of floating boom of the 3rd floating boom field effect transistor on the grid source electrode/grid leak electrode capacitance of second field effect transistor.
4, Nonvolatile storage unit in high speed according to claim 1, it is characterized in that, when described programming end ground connection and described precharge end are unsettled, the 3rd floating boom field effect transistor disconnects, and the grid source electrode of first field effect transistor and second field effect/grid leak electrode capacitance constitutes the DRAM unit and comes storing data information.
5, Nonvolatile storage unit in high speed according to claim 1, it is characterized in that, when described programming termination positive high voltage source and described precharge end ground connection, by the control signal in the row route selection first field effect transistor is disconnected, if store the then second field effect transistor conducting of electric charge, electric charge is entered in the floating boom of the 3rd floating boom field effect transistor on the grid source electrode/grid leak electrode capacitance of second field effect transistor.
6, Nonvolatile storage unit in high speed according to claim 1 is characterized in that, described first field effect transistor and second field effect transistor are enhancement mode N-channel MOS field effect transistor or enhancement mode P channel MOS field effect transistor.
7, a kind of non-volatile high-speed memory is characterized in that, comprising:
Each storage unit in the memory cell array, described memory cell array comprises first field effect transistor, second field effect transistor and the 3rd floating boom field effect transistor; The grid of first field effect transistor is connected with the row route selection, among both one of the source electrode of first field effect transistor and drain electrode is connected with the column selection line, and another grid with second field effect transistor is connected and is connected with the source electrode of the 3rd floating boom field effect transistor and of draining among both; The source electrode of second a field effect transistor and drain electrode grid with the 3rd floating boom field effect transistor among both is connected, and another is drawn and form to programme holds; The source electrode of the 3rd floating boom field effect transistor and drain electrode among both is not connected one with first field effect transistor draw formation precharge end;
The programming end of all storage unit is connected in parallel respectively with the precharge end and is in the same place in the described memory cell array, by described programming end and the external different conditions of precharge end, carry out the transfer of canned data between described second field effect transistor and described the 3rd floating boom field effect transistor.
8, non-volatile high-speed memory according to claim 7, it is characterized in that, when described programming end ground connection and described precharge termination working voltage source, by the control signal in the row route selection first field effect transistor in the described storage unit is disconnected, if store then the 3rd floating boom field effect transistor conducting of electric charge, make the grid source electrode/grid leak electrode capacitance charging of second field effect transistor in the floating boom of the 3rd floating boom field effect transistor.
9, non-volatile high-speed memory according to claim 7, it is characterized in that, when described programming termination negative high voltage source and described precharge end ground connection, by the control signal in the row route selection first field effect transistor in the described storage unit is disconnected, if store the then second field effect transistor conducting of electric charge, remove the interior electric charge of floating boom of the 3rd floating boom field effect transistor on the grid source electrode/grid leak electrode capacitance of second field effect transistor.
10, non-volatile high-speed memory according to claim 7, it is characterized in that, when described programming end ground connection and described precharge end are unsettled, the 3rd floating boom field effect transistor in the described storage unit disconnects, and the grid source electrode of first field effect transistor and second field effect/grid leak electrode capacitance constitutes the DRAM unit and comes storing data information.
11, non-volatile high-speed memory according to claim 7, it is characterized in that, when described programming termination positive high voltage source and described precharge end ground connection, by the control signal in the row route selection first field effect transistor in the described storage unit is disconnected, if store the then second field effect transistor conducting of electric charge, electric charge is entered in the floating boom of the 3rd floating boom field effect transistor on the grid source electrode/grid leak electrode capacitance of second field effect transistor.
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Citations (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN1098221A (en) * | 1993-03-31 | 1995-02-01 | 三星电子株式会社 | The nonvolatile semiconductor memory that has memory cell structure |
| CN1164926A (en) * | 1995-08-04 | 1997-11-12 | 爱特梅尔股份有限公司 | High speed, low voltage non-volatile memory |
| CN1211077A (en) * | 1997-09-05 | 1999-03-17 | 三菱电机株式会社 | Storage unit and anonvolatile semiconductor storage having said storage unit |
| CN1228600A (en) * | 1998-02-18 | 1999-09-15 | 日本电气株式会社 | Nonvolatile semiconductor memory device having program area |
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Patent Citations (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN1098221A (en) * | 1993-03-31 | 1995-02-01 | 三星电子株式会社 | The nonvolatile semiconductor memory that has memory cell structure |
| CN1164926A (en) * | 1995-08-04 | 1997-11-12 | 爱特梅尔股份有限公司 | High speed, low voltage non-volatile memory |
| CN1211077A (en) * | 1997-09-05 | 1999-03-17 | 三菱电机株式会社 | Storage unit and anonvolatile semiconductor storage having said storage unit |
| CN1228600A (en) * | 1998-02-18 | 1999-09-15 | 日本电气株式会社 | Nonvolatile semiconductor memory device having program area |
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