CN100430947C - 基于边的倒序树扫描线算法优化层次版图验证方法 - Google Patents
基于边的倒序树扫描线算法优化层次版图验证方法 Download PDFInfo
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- CN100430947C CN100430947C CNB031264972A CN03126497A CN100430947C CN 100430947 C CN100430947 C CN 100430947C CN B031264972 A CNB031264972 A CN B031264972A CN 03126497 A CN03126497 A CN 03126497A CN 100430947 C CN100430947 C CN 100430947C
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CNB031264972A CN100430947C (zh) | 2003-09-29 | 2003-09-29 | 基于边的倒序树扫描线算法优化层次版图验证方法 |
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CNB031264972A CN100430947C (zh) | 2003-09-29 | 2003-09-29 | 基于边的倒序树扫描线算法优化层次版图验证方法 |
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CN1604089A CN1604089A (zh) | 2005-04-06 |
CN100430947C true CN100430947C (zh) | 2008-11-05 |
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Families Citing this family (7)
Publication number | Priority date | Publication date | Assignee | Title |
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CN101452493B (zh) * | 2007-11-29 | 2010-09-08 | 北京华大九天软件有限公司 | 一种提高版图验证中图形扩展速度的方法 |
CN101464916B (zh) * | 2007-12-21 | 2010-09-08 | 北京华大九天软件有限公司 | 集成电路版图的器件属性计算方法 |
CN102411643B (zh) * | 2010-09-26 | 2014-06-25 | 北京华大九天软件有限公司 | 集成电路版图验证自适应扫描线计算方法 |
CN102622456B (zh) * | 2011-01-28 | 2014-02-05 | 北京华大九天软件有限公司 | 集成电路版图验证图形拓扑命令并发计算方法 |
CN102890730B (zh) * | 2011-07-20 | 2016-08-10 | 清华大学 | 一种集成电路版图验证中矩形包含规则的验证方法 |
CN104573149A (zh) * | 2013-10-17 | 2015-04-29 | 北京华大九天软件有限公司 | 一种平板显示版图设计规则检查的去除重复报错方法 |
CN106649897B (zh) * | 2015-10-28 | 2019-11-15 | 北京华大九天软件有限公司 | 一种子单元阵列拼接预处理方法 |
Citations (6)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US5956257A (en) * | 1993-03-31 | 1999-09-21 | Vlsi Technology, Inc. | Automated optimization of hierarchical netlists |
US5974243A (en) * | 1997-10-31 | 1999-10-26 | Hewlett-Packard Company | Adjustable and snap back design-rule halos for computer aided design software |
US6045584A (en) * | 1997-10-31 | 2000-04-04 | Hewlett-Packard Company | Multilevel and beveled-corner design-rule halos for computer aided design software |
WO2003021499A1 (en) * | 2001-08-29 | 2003-03-13 | Morphics Technology Inc. | Integrated circuit chip design |
CN1430265A (zh) * | 2001-12-28 | 2003-07-16 | 恩益禧电子股份有限公司 | 设计系统大规模集成电路的方法 |
CN1441481A (zh) * | 2002-02-14 | 2003-09-10 | 松下电器产业株式会社 | 半导体集成电路的设计方法和测试方法 |
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Patent Citations (6)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US5956257A (en) * | 1993-03-31 | 1999-09-21 | Vlsi Technology, Inc. | Automated optimization of hierarchical netlists |
US5974243A (en) * | 1997-10-31 | 1999-10-26 | Hewlett-Packard Company | Adjustable and snap back design-rule halos for computer aided design software |
US6045584A (en) * | 1997-10-31 | 2000-04-04 | Hewlett-Packard Company | Multilevel and beveled-corner design-rule halos for computer aided design software |
WO2003021499A1 (en) * | 2001-08-29 | 2003-03-13 | Morphics Technology Inc. | Integrated circuit chip design |
CN1430265A (zh) * | 2001-12-28 | 2003-07-16 | 恩益禧电子股份有限公司 | 设计系统大规模集成电路的方法 |
CN1441481A (zh) * | 2002-02-14 | 2003-09-10 | 松下电器产业株式会社 | 半导体集成电路的设计方法和测试方法 |
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