CN100428447C - 芯片封装的信号传输结构及基板 - Google Patents
芯片封装的信号传输结构及基板 Download PDFInfo
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Abstract
本发明提供一种芯片封装的信号传输结构及基板,该基板包括多层绝缘层及多层金属层,绝缘层系叠层接合,而每一金属层分别位于绝缘层的其中之一上,金属层的其中两层分别定义为一第一金属层及一第二金属层,第一金属层位于基板的表层,第二金属层位于基板内,且为最靠近第一金属层的金属层,第一金属层具有一接垫,而第二金属层具有一开洞,实质上对准接垫的位置。
Description
技术领域
本发明涉及一种芯片封装的信号传输结构及基板,且特别是涉及一种具有高电性效能的芯片封装的信号传输结构及基板。
背景技术
在现今的信息社会中,均追求高速度、高品质、多功能性的产品,而就产品外观而言,朝向轻、薄、短、小的趋势迈进。一般电子产品均具有半导体芯片及与半导体芯片电连接的承载器,现今业界大致上利用三种技术使芯片与承载器电连接,第一种是引线接合工艺(wire-bonding);第二种是倒装片工艺(flip-chip);第三种是柔性带自动连接工艺(tape-automated-bonding,TAB)。当承载器采用导线架时,一般是利用引线接合的方式使芯片与导线架的管脚电连接。
然而,芯片与导线架间的信号传输品质会受到引线接合导线的阻抗与系统阻抗之间的差异性的影响,如果引线接合导线的阻抗与系统阻抗之间有差异性存在时,便会导致阻抗不匹配的现象,以致产生信号反射的情形。一般在传输高频信号时,引线接合导线的阻抗大于系统阻抗,此时会反射正相位的信号。当引线接合导线的阻抗与系统阻抗之间差异很大时,便会导致半导体芯片运算错误。
接下来,介绍一种公知的利用引线接合方式使芯片与导线架电连接的芯片封装结构,如图1A及图1B所示。请参照图1A及图1B,芯片封装结构100包括芯片110、导线架120、引线接合导线130、接地引线接合导线140及绝缘材料150,而导线架120一般具有一芯片座122及多个形状一致的管脚124,管脚124环绕在芯片座122的周围区域。芯片110利用粘着材料172贴附在芯片座122上,并通过引线接合工艺使信号引线接合导线130a及接地引线接合导线130b分别与管脚124a及管脚124b电连接,芯片座122可以通过基板190的引线194与管脚124b电连接,作为电性接地之用。绝缘材料150包覆芯片110、导线架120、信号引线接合导线130a及接地引线接合导线130b。芯片封装结构100的芯片座122及管脚124可以分别通过粘着材料174、176与基板190接合。
如图1B所示,芯片110经由引线接合导线130、管脚124及粘着材料176才能与基板190的引线192电连接,接地引线接合导线130b位于用于信号传输的信号引线接合导线130a的两侧,作为屏蔽之用,以减少信号引线接合导线130a在传输信号时受到干扰的程度,同时亦可以减少信号引线接合导线130a在传输信号时干扰到外界线路的程度。然而由于信号引线接合导线130a的截面积很小且长度很长,因此在传输高频信号时,信号引线接合导线130a呈现电感性的状态,且会产生很高的阻抗,使得经由信号引线接合导线130a的传输线路会反射正相位的信号,当此传输线路的阻抗偏离系统阻抗很大时,很至会导致芯片110运算错误。
接下来,再介绍另一种公知的利用引线接合方式使芯片与导线架电连接的芯片封装结构,如图2A及图2B所示。请参照图2A及图2B,其结构大致上与图1A及图1B所示的芯片封装结构相同,唯一不同之处在于在芯片110与芯片座122之间还连接有接地引线接合导线140。
为了改善上述的状况,在威盛专利申请案第VIT03-0128号中提出下列的技术概念,图3示出威盛专利申请案第VIT03-0128号所提出的一优选实施例的技术内容。请先参照图3,导线架220具有一芯片座222、多个形状一致的一般管脚224及至少一特征管脚结构226,特征管脚结构226由两个特征管脚226a、226b所构成,而特征管脚226a、226b的形状与位于特征管脚226a、226b两侧的一般管脚224的形状相同,特征管脚226a、226b的宽度w1与位于特征管脚226a、226b两侧的一般管脚224的宽度w2相同。一般管脚224及特征管脚226a、226b排列在芯片座222的周围区域,而特征管脚226a、226b排列在一般管脚224之间,其中二特征管脚226a、226b垂直于信号传输方向的截面积之和大于每一个一般管脚224垂直于信号传输方向的截面积,也即特征管脚结构226垂直于信号传输方向的截面积大于每一个一般管脚224垂直于信号传输方向的截面积。就体积而言,二特征管脚226a、226b的体积之和大于每一个一般管脚224的体积,也即特征管脚结构226的体积大于每一个一般管脚224的体积。芯片210的一接点212利用两条特征引线接合导线232a、232b分别与二特征管脚226a、226b电连接,也即与基板的接垫292之间通过两条特征引线接合导线232a、232b及二特征管脚226a、226b传输同一信号。
如图3所示,芯片210经由特征引线接合导线232a、232b、特征管脚226a、226b及粘着材料278与基板290的引线292电连接。接地引线接合导线240位于用于信号传输的特征引线接合导线232a、232b的两侧,作为屏蔽之用,以减少特征引线接合导线232a、232b在传输信号时受到干扰的程度,同时亦可以减少特征引线接合导线232a、232b在传输信号时干扰到外界线路的程度。
由于特征引线接合导线232a、232b的截面积很小且长度很长,因此在传输信号时,会呈现电感性的状态,但是为补偿特征引线接合导线232a、232b呈现电感性的状态,在威盛专利申请案第VIT03-0128号中,特别针对导线架220设计有特征管脚结构226,其总体积大于每一个一般管脚224的体积,由于特征管脚结构226垂直于信号传输方向的截面积很大,因此特征管脚结构226呈现电容性的状态,以补偿特征引线接合导线232a、232b呈现电感性的状态。再者,利用两条特征引线接合导线232a、232b作为芯片210与导线架220之间的电连接,如此亦可以补偿仅使用单一引线接合导线作信号传输而呈现电感性的状态。
另外,请参照图4,其示出威盛专利申请案第VIT03-0128号所提出的另一优选实施例的技术内容。芯片310经由二特征引线接合导线332a、332b、特征管脚结构326及粘着材料378与基板390的接垫392电连接。特征管脚结构326的形状为单一块状的形式,一般管脚324及特征管脚结构326系排列在芯片座322的周围区域,而特征管脚结构326排列在一般管脚324之间,其中特征管脚结构326垂直于信号传输方向的截面积大于每一个一般管脚324垂直于信号传输方向的截面积。就体积而言,特征管脚结构326的体积大于每一个一般管脚324的体积。芯片310的一接点312利用两条特征引线接合导线332a、332b与单一块状形式的特征管脚结构326电连接,也即与基板的接垫392之间通过两条特征引线接合导线332a、332b及一特征管脚结构326传输同一信号。由于特征管脚结构326垂直于信号传输方向的截面积很大,因此特征管脚结构326呈现电容性的状态,以补偿特征引线接合导线332a、332b呈现电感性的状态。
此外,请参照图5,其示出威盛专利申请案第VIT03-0128号所提出的再一优选实施例的技术内容。芯片410的一接点412亦可以仅利用一条特征引线接合导线432与单一块状形式的特征管脚结构426电连接,也即与基板的接垫492之间通过一条特征引线接合导线432及一特征管脚结构426传输同一信号。
请参照图3、图4及图5,在威盛专利申请案第VIT03-0128号所提出的技术内容中,如果特征管脚结构226、326、426垂直于信号传输方向的截面积过大,则由特征引线接合导线232a、232b、332a、332b、432及特征管脚结构226、326、426所构成的传输线路会呈现偏电容性的状态,而反射负相位的信号。
发明内容
有鉴于此,本发明的目的之一是提出一种芯片封装结构及基板,可以补偿由特征引线接合导线及特征管脚结构所构成的传输线路呈现偏电容性的状态,使得此传输线路的阻抗与系统阻抗之间具有更佳的匹配。
在叙述本发明之前,先对空间介词的用法做以界定,所谓空间介词“上”是指两物体的空间关系系为相接触或不接触均可。举例而言,A物在B物上,其所表达的意思为A物可以直接配置在B物上,A物与B物接触;或者A物配置在B物上的空间中,A物没有与B物接触。
为达本发明的上述目的,提出一种芯片封装结构,包括一导线架、一芯片、多条引线接合导线、至少一特征引线接合导线、一绝缘材料、一基板及一导电粘着材料。导线架具有一芯片座、多个一般管脚及一特征管脚结构,一般管脚及特征管脚结构排列在芯片座的周围,特征管脚结构排列在一般管脚之间,其中特征管脚结构垂直于信号传输方向的截面积大于每一一般管脚垂直于信号传输方向的截面积。芯片位于芯片座上,而引线接合导线连接于芯片与一般管脚之间,特征引线接合导线连接于芯片与特征管脚结构之间,芯片与特征管脚结构之间利用特征引线接合导线传输同一信号。绝缘材料包覆导线架、芯片、引线接合导线及特征引线接合导线。基板具有多层金属层及多层绝缘层,绝缘层为叠层接合,每一金属层分别位于绝缘层的其中之一上,金属层的其中两层分别定义为一第一金属层及一第二金属层,第一金属层位于基板的表层,第二金属层位于基板内,且为最靠近第一金属层的金属层,第一金属层具有一芯片座接垫、多个一般接垫及一特征接垫,一般接垫及特征接垫排列在芯片座接垫的周围,特征接垫排列在一般接垫之间,第二金属层具有一开洞,实质上对准特征接垫的位置。利用导电粘着材料接合芯片座与芯片座接垫、接合一般管脚与一般接垫、及接合特征管脚结构与特征接垫。
本发明提供一种基板,适于与一信号传输线路连接,其中该信号传输线路的寄生电容过大,该基板至少包括:多层绝缘层,为叠层接合;以及多层金属层,每一该些金属层分别位于该些绝缘层的其中之一上,该些金属层的其中两层分别定义为一第一金属层及一第二金属层,该第一金属层位于该基板的表层,该第二金属层位于该基板内,且为最靠近该第一金属层的金属层,该第一金属层具有一接垫,适于与该信号传输线路连接,且该第二金属层具有一开洞,实质上对准该接垫的位置,以补偿该信号传输线路的过大的寄生电容。
本发明一种用于导线架封装的信号传输结构,适于使一芯片通过一导线架电连接于一基板,该基板具有一第一金属层,位于该基板的表层,该信号传输结构包括:一高频传输线路,具有至少一高频引线接合导线、一高频信号管脚结构及至少一高频信号接垫,该芯片经由该高频引线接合导线及该高频信号管脚结构电连接于该高频信号接垫,该高频信号管脚结构由该导线架所提供,该高频信号接垫由该基板的该第一金属层所提供;以及多条一般传输线路,每一该些一般传输线路分别具有一一般引线接合导线、一一般管脚及一一般接垫,该芯片经由该些一般引线接合导线及该些一般管脚电连接于该些一般接垫,该些一般管脚由该导线架所提供,该些一般接垫由该基板的该第一金属层所提供,该高频信号管脚结构位于该些一般管脚之间,该高频信号接垫位于该些一般接垫之间,其中该高频传输线路的电容值大于该些一般传输线路的电容值,且该基板具有一第二金属层,位于该基板内,且为最靠近该第一金属层的金属层,该第二金属层具有一开洞,实质上对准该高频信号接垫的位置,用以补偿该高频传输线路过大的电容值。
根据本发明的一优选实施例,芯片封装结构包括多条特征引线接合导线,而特征管脚结构包括多个特征管脚,特征管脚的形状与位于特征管脚结构两侧的一般管脚的形状相同,特征引线接合导线分别连接于芯片的同一接点与特征管脚之间。而根据本发明的另一优选实施例,特征管脚结构的形状为单一块状的形式。此外,第二金属层可以是接地平面或是电源平向。
综上所述,本发明的芯片封装结构及芯片与基板间的电连接结构,由于特征管脚结构的体积很大,因此特征管脚结构呈现电容性的状态,以补偿特征引线接合导线呈现电感性的状态。若是在补偿之后,特征管脚结构垂直于信号传输方向的截面积过大,则由特征引线接合导线及特征管脚结构所构成的传输线路会呈现偏电容性的状态,而反射负相位的信号。此时,为了修正此传输线路的阻抗,在本发明中将金属层在对准特征接垫的位置,配置有开洞,以补偿此传输线路呈现偏电容性的状态,由于金属层的开洞可以利用光刻蚀刻的方式形成,因此开洞的尺寸及形状能够被精准地定义,从而使得此传输线路的阻抗能更趋近于系统阻抗。
附图说明
为使本发明的上述目的、特征、和优点能更明显易懂,下文特举一优选实施例,并配合附图,作详细说明如下:
图1A示出公知的利用引线接合方式使芯片与导线架电连接的芯片封装结构的剖视图;
图1B示出图1A中公知的芯片与基板间的电连接结构的立体图;
图2A示出另一公知的利用引线接合方式使芯片与导线架电连接的芯片封装结构的剖视图;
图2B示出图2A中另一公知的芯片与基板间的电连接结构的立体图;
图3示出威盛专利申请案第VIT03-0128号所提出的一优选实施例的技术内容;
图4示出威盛专利申请案第VIT03-0128号所提出的另一优选实施例的技术内容;
图5示出威盛专利申请案第VIT03-0128号所提出的再一优选实施例的技术内容;
图6示出根据本发明一优选实施例的芯片封装结构的剖视图;
图7示出根据本发明一优选实施例中基板的俯视图;
图8示出根据本发明一优选实施例中基板的其中二金属层的俯视图;
图9示出表一中每一情形的S22的频率响应示意图;
图10示出表一中每一情形的S21的频率响应示意图;
图11示出表一中每一情形的史密斯圆图(Smith chart)的频率响应示意图;
图12示出表二中每一情形的S22的频率响应示意图;
图13示出表二中每一情形的S21的频率响应示意图;
图14示出表二中每一情形的史密斯圆图的频率响应示意图。
附图标记说明
100:芯片封装结构 110:芯片
120:导线架 122:芯片座
124a:管脚 124b:管脚
130a:信号引线接合导线 130b:接地引线接合导线
140:接地引线接合导线 150:绝缘材料
172:粘着材料 174:粘着材料
176:粘着材料 190:基板
192:引线 194:引线
210:芯片 212:接点
222:芯片座 224:一般管脚
226:特征管脚结构 226a:特征管脚
226b:特征管脚 232a:特征引线接合导线
232b:特征引线接合导线 240:接地引线接合导线
278:粘着材料 292:引线
310:芯片 312:接点
322:芯片座 324:一般管脚
326:特征管脚结构 332a:特征引线接合导线
332b:特征引线接合导线 378:粘着材料
392:接垫
410:芯片 412:接点
426:特征管脚结构 432:特征引线接合导线
492:接垫
500:芯片封装结构 510:芯片
512:接点 520:导线架
522:芯片座 524:一般管脚
526:特征管脚结构 530:引线接合导线
532:特征引线接合导线 540:接地引线接合导线
550:绝缘材料 570:导电粘着材料
572:粘着材料 590:基板
592a:金属层 592b:金属层
592c:金属层 592d:金属层
594a:绝缘层 594b:绝缘层
594c:绝缘层 594d:绝缘层
594e:绝缘层 595:芯片座接垫
596:一般接垫 597:特征接垫
598:开洞
w1:特征管脚的宽度
w2:一般管脚的宽度
具体实施方式
图6示出根据本发明一优选实施例的芯片封装结构的剖视图;图7示出根据本发明一优选实施例中基板的俯视图;图8示出根据本发明一优选实施例中基板的其中二金属层的俯视图。
请先参照图6,芯片封装结构500包括芯片510、导线架520、引线接合导线530、特征引线接合导线532、接地引线接合导线540、绝缘材料550、基板590及导电粘着材料570,而导线架520具有一芯片座522、多个形状一致的一般管脚524及至少一特征管脚结构526,其中特征管脚结构526可以是具有二特征管脚,而每一特征管脚的形状与一般管脚的形状一致,如图3所示;或者特征管脚结构526亦可以是单一块状的形式、如图4及图5所示。特征管脚结构的配置及形状在前述的现有技术中及威盛专利申请案第VIT03-0128号中均有详尽的叙述,在此便不再赘述。
请继续参照图6,芯片510利用粘着材料572贴附在芯片座522上,并通过引线接合工艺使引线接合导线530、特征引线接合导线532及接地引线接合导线540分别与一般管脚524、特征管脚结构526及芯片座522电连接,芯片座522及接地引线接合导线540为电性接地。在本实施例中,芯片510的一接点512可以利用二特征引线接合导线分别与具有二特征管脚的特征管脚结构电连接,如图3所示;或者可以利用二特征引线接合导线与单一块状形式的特征管脚结构电连接,如图4所示;或者可以利用一条特征引线接合导线与单一块状形式的特征管脚结构电连接,如图5所示。接地引线接合导线540电连接芯片与芯片座,作为电性接地,且接地引线接合导线540位于特征引线接合导线532的两侧,可以作为屏蔽特征引线接合导线532之用,其相关叙述可以参照前述的现有技术或威盛专利申请案第VIT03-0128号。请参照图6,绝缘材料550包覆芯片510、导线架520、引线接合导线530、特征引线接合导线532及接地引线接合导线540。
请参照图6、图7及图8,基板590具有多层金属层592a、592b、592c、592d及多层绝缘层594a、594b、594c、594d、594e,绝缘层594a、594b、594c、594d、594e为叠层接合,而每一金属层592a、592b、592c、592d分别位于绝缘层594a、594b、594c、594d、594e的其中之一上。其中金属层592a位于基板590的表层,而金属层592b位于基板590内,且为最靠近金属层592a的金属层。金属层592a具有芯片座接垫595、多个一般接垫596及一特征接垫597,一般接垫596及特征接垫597排列在芯片座接垫595的周围,特征接垫597排列在一般接垫596之间。金属层592b例如为接地平面或电源平面,且金属层592b具有一开洞598,实质上对准特征接垫597的位置。
请参照图6,利用导电粘着材料570可以接合芯片座522与芯片座接垫595、接合一般管脚524与一般接垫596、及接合特征管脚结构526与特征接垫597。
由于特征引线接合导线532的截面积很小且长度很长,因此在传输信号时,会呈现电感性的状态,此时会反射正相位的信号。而为补偿特征引线接合导线532呈现电感性的状态,在威盛专利申请案第VIT03-0128号中,特别针对导线架520设计有特征管脚结构526,其总体积大于每一个一般管脚524的体积,由于特征管脚结构526垂直于信号传输方向的截面积很大,因此特征管脚结构526呈现电容性的状态,以补偿特征引线接合导线532呈现电感性的状态。但是在补偿之后,如果特征管脚结构526垂直于信号传输方向的截面积过大,则由特征引线接合导线532及特征管脚结构526所构成的传输线路会呈现偏电容性的状态,而反射负相位的信号。此时,为了修正此传输线路的阻抗,在本发明中将金属层592b在对准特征接垫597的位置处,配置有开洞598,藉以补偿此传输线路呈现偏电容性的状态,由于金属层592b的开洞598可以利用光刻蚀刻的方式形成,因此开洞598的尺寸及形状能够被精准地定义,而使得此传输线路的阻抗能更趋近于系统阻抗。
实验结果
在本发明中,分别针对现有技术与本发明作实验,从实验数据中可以得知本发明的芯片与基板间的电连接结构明显地优于公知的芯片与基板间的电连接结构。
表一为在2.5GHz、5GHz及10GHz的频率下,情形A、情形B、情形B1及情形B2的结构所呈现的频率响应值。其中情形A代表图1A及图1B所示的结构,情形B代表图3所示的结构且特征接垫下的金属层并不具有如图8所示的开洞,情形B1代表图3所示的结构且特征接垫下的金属层具有如图8所示的开洞,情形B2代表图3所示的结构且特征接垫下的金属层具有如图8所示的开洞,其中在情形B2中的开洞大于在情形B1中的开洞。
表一
另外,在图9中,示出表一中每一情形的S22的频率响应示意图,在图10中,示出表一中每一情形的S21的频率响应示意图,在图11中,示出表一中每一情形的史密斯圆图的频率响应示意图。
表二为在2.5GHz、5GHz及10GHz的频率下,情形A、情形C、情形C1、情形C2及情形C3的结构所呈现的频率响应值。其中情形A代表图1A图及图1B所示的结构,情形C代表图4所示的结构且特征接垫下的金属层并不具有如图8所示的开洞,情形C1代表图4所示的结构且特征接垫下的金属层具有如图8所示的开洞,情形C2代表图4所示的结构且特征接垫下的金属层具有如图8所示的开洞,情形C3代表图4所示的结构且特征接垫下的金属层具有如图8所示的开洞,其中在情形C3中的开洞大于在情形C2中的开洞,而在情形C2中的开洞大于在情形C1中的开洞。
表二
另外,在图12中,示出表二中每一情形的S22的频率响应示意图,在图13中,示出表二中每一情形的S21的频率响应示意图,在图14中,示出表二中每一情形的史密斯圆图的频率响应示意图。
结论
在实际应用上,由特征引线接合导线、特征管脚结构及特征接垫所构成的传输线路可以传输高频信号。而本发明的特征之一为基板,利用位于接垫下的金属层形成开洞的设计,可以补偿传输线路呈现电容性的状态,任何其他各种形式的芯片封装结构均可以与此种基板接合,并不限于实施例所述的样式。
虽然本发明已以一优选实施例披露如上,然其并非用以限定本发明,任何本领域技术人员,在不脱离本发明的精神和范围内,当可以作出各种改动与润饰,因此本发明的保护范围应当以后所附的权利要求书所界定的为准。
Claims (10)
1.一种基板,适于与一信号传输线路连接,其中该信号传输线路的寄生电容过大,该基板至少包括:
多层绝缘层,为叠层接合;以及
多层金属层,每一上述这些金属层分别位于上述这些绝缘层的其中之一上,上述这些金属层的其中两层分别定义为一第一金属层及一第二金属层,该第一金属层位于该基板的表层,该第二金属层位于该基板内,且为最靠近该第一金属层的金属层,该第一金属层具有一接垫,适于与该信号传输线路连接,且该第二金属层具有一开洞,实质上对准该接垫的位置,以补偿该信号传输线路的过大的寄生电容。
2.如权利要求1所述的基板,其中该接垫传输高频信号。
3.一种用于导线架封装的信号传输结构,适于使一芯片通过一导线架电连接于一基板,该基板具有一第一金属层,位于该基板的表层,该信号传输结构包括:
一高频传输线路,具有至少一高频引线接合导线、一高频信号管脚结构及至少一高频信号接垫,该芯片经由该高频引线接合导线及该高频信号管脚结构电连接于该高频信号接垫,该高频信号管脚结构由该导线架所提供,该高频信号接垫由该基板的该第一金属层所提供;以及
多条一般传输线路,每一上述这些一般传输线路分别具有一一般引线接合导线、一一般管脚及一一般接垫,该芯片经由上述这些一般引线接合导线及上述这些一般管脚电连接于上述这些一般接垫,上述这些一般管脚由该导线架所提供,上述这些一般接垫由该基板的该第一金属层所提供,该高频信号管脚结构位于上述这些一般管脚之间,该高频信号接垫位于上述这些一般接垫之间,
其中该高频传输线路的电容值大于上述这些一般传输线路的电容值,且该基板具有一第二金属层,位于该基板内,且为最靠近该第一金属层的金属层,该第二金属层具有一开洞,实质上对准该高频信号接垫的位置,用以补偿该高频传输线路过大的电容值。
4.如权利要求3所述的用于导线架封装的信号传输结构,其中该高频信号管脚结构的宽度大于每一上述这些一般管脚的宽度。
5.如权利要求3所述的用于导线架封装的信号传输结构,其中该高频信号管脚结构垂直于信号传输方向的截面积大于每一上述这些一般管脚垂直于信号传输方向的截面积。
6.如权利要求3所述的用于导线架封装的信号传输结构,其中该高频信号管脚结构包括多个高频信号管脚,上述这些高频信号管脚为电性并联,上述这些高频信号管脚的形状与上述这些一般管脚的形状相同,且该高频传输线路包括多条高频引线接合导线,分别连接于上述这些高频信号管脚。
7.如权利要求6所述的用于导线架封装的信号传输结构,其中上述这些高频引线接合导线与上述这些高频信号管脚共同传输一高频信号。
8.如权利要求3所述的用于导线架封装的信号传输结构,其中该高频信号管脚结构包括多个高频信号管脚,上述这些高频信号管脚为电性并联,上述这些高频信号管脚的宽度与上述这些一般管脚的宽度相同,且该高频传输线路包括多条高频引线接合导线,分别连接于上述这些高频信号管脚。
9.如权利要求8所述的用于导线架封装的信号传输结构,其中上述这些高频引线接合导线与上述这些高频信号管脚共同传输一高频信号。
10.如权利要求3所述的用于导线架封装的信号传输结构,其中该高频信号管脚结构的总体积大于每一上述这些一般管脚的体积。
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