CN100424875C - Semiconductor element - Google Patents

Abstract

The present invention relates to a semiconductor element. The semiconductor element comprises a substrate which is provided with a well region, a drain electrode diffusing region and a source electrode diffusing region which are arranged in the well region, a grid insulating layer which is arranged on the surface of the well region, a grid electrode which is arranged on the grid insulating layer, a substrate contact diffusing region which is arranged in the well region, and an insulating groove, wherein the conductive form of the substrate contact diffusing region is opposite to the conductive form of the well region. The semiconductor element of the present invention can be composed of an MOS transistor, a junction diode and a resistor which is electrically connected with the MOS transistor and the junction diode, wherein the junction diode can be composed of the substrate contact diffusing region and the well region; the resistor is an intrinsic resistor of the well region.

Description

Semiconductor element

Technical field

The invention relates to a kind of semiconductor element, particularly about a kind of semiconductor element that comprises the metal oxide semiconductor transistor of dynamic cut-in voltage.

Background technology

Metal oxide semiconductcor field effect transistor (MOSFET) since possess low in energy consumption, reliability is high and advantage such as flexible circuit design, be widely used on the integrated circuit at present.In order to have best service behaviour, transistorized cut-in voltage all designs only has very low leakage current when closing, then keep the very high full electric current that closes when conducting.Full the close electric current of transistor when conducting represented with following formula:

$I_D=\frac{1}{2}{k}_n^{\′}\left(\frac{W}{L}\right){(V_{\mathrm{GS}}-V_t)}^2$

Wherein, V _tRepresent cut-in voltage, V _GSRepresent voltage difference, the k ' of grid and source electrode _nRepresent transconductance parameters, L to represent channel length, and W represent channel width.Generally speaking, transistor design becomes to have higher cut-in voltage, to reduce or to avoid the leakage current of transistor when closing.Yet according to following formula, the full current value that closes when higher cut-in voltage will make transistor turns reduces.Transistorized cut-in voltage can be represented by following formula:

$V_t={\mathrm{<figure-callout\; id="0"\; label="V\; t"\; filenames="C0314970600121.png,C0314970600122.png"\; state="\{\{state\}\}">V</figure-callout>}}_t\&PlusMinus;\mathrm{\&gamma;}[\sqrt{2{\mathrm{\&phi;}}_f-V_{\mathrm{SB}}}-\sqrt{{2\mathrm{\&phi;}}_f}]$

Wherein, V _T0The bias voltage of representing source electrode and base stage is 0 o'clock a cut-in voltage, V _SBRepresent the bias value of source electrode and substrate, and 2 φ _fThe surperficial potential energy of expression source electrode when strong counter-rotating (strong inversion).By following formula as can be known, by changing the bias voltage of source electrode and substrate, can adjust transistorized cut-in voltage.

Fig. 1 is a United States Patent (USP) the 6th, 166, the cutaway view of the nmos pass transistor 10 that No. 584 (' 584 patent to call in the following text) discloses.As shown in Figure 1, nmos pass transistor 10 comprises a P type substrate 24, one source pole diffusion region 14, a drain diffusion regions 16, a grid 20 and a raceway groove 28.The current potential of P type substrate 24 is the external voltage control by P+ type substrate contact diffusion zone 26.That is ' 584 patent is to utilize an external control circuit to control the current potential of P type substrate 24, and then adjusts the cut-in voltage of nmos pass transistor 10.

Fig. 2 is a United States Patent (USP) the 6th, 124, the transistorized schematic diagram of the dynamic cut-in voltage of a tool that No. 618 (' 618 patent to call in the following text) discloses.As shown in Figure 2, nmos pass transistor 100 is the current potentials that utilize a biasing device 200 control substrates 130, and then adjusts the cut-in voltage of nmos pass transistor 100.

Though the technology that ' 584 patent and ' 618 patent disclose all can be adjusted transistorized cut-in voltage.Yet the technology that ' 584 patent and ' 618 patent disclose all must use outside voltage control circuit to come the underlayer voltage of oxide-semiconductor control transistors, will make that the transistor circuit with dynamic cut-in voltage is more complicated.

Summary of the invention

Main purpose of the present invention provides a kind of semiconductor element that comprises the metal oxide semiconductor transistor of dynamic cut-in voltage.

For achieving the above object, the present invention discloses a kind of semiconductor element.This semiconductor element comprises a substrate, with a well region and is arranged on gate insulation layer, that drain diffusion regions in this well region and source diffusion region, be arranged on this well region surface and is arranged on grid, on this gate insulation layer and is arranged on substrate contact diffusion zone and in this well region and is arranged on insulation tank in the well region.This well region can belong to the P-type conduction kenel, and this substrate contact diffusion zone then belongs to N type conductivity.This insulation tank is arranged between this substrate contact diffusion zone and this drain diffusion regions or between this substrate contact diffusion zone and this source diffusion region.The degree of depth of this insulation tank is greater than the junction depth of this drain diffusion regions or this source diffusion region.It is that resistance by a metal oxide semiconductor transistor, a junction diode and are electrically connected this metal oxide semiconductor transistor and this junction diode constitutes that semiconductor element of the present invention can be considered.Junction diode can be considered by this substrate contact diffusion zone and this well region and constitutes, and this resistance then is the intrinsic resistance (Intrinsic resistance) of this well region.

Compared to existing skill, the present invention has following advantage:

1. semiconductor element of the present invention has quite simple structure, and does not need to use external circuit to control the substrate of its metal oxide semiconductor transistor and the bias voltage of source electrode.

2. metal oxide semiconductcor field effect transistor of the present invention maintains very low leakage current when closing, and can improve 13% drain current when conducting.

Description of drawings

Fig. 1 is a United States Patent (USP) the 6th, 166, the cutaway view of a nmos pass transistor of No. 584 announcements;

Fig. 2 is a United States Patent (USP) the 6th, 124, the schematic diagram of the dynamic cut-in voltage semiconductor device of a tool of No. 618 announcements.

Fig. 3 is the cutaway view of the semiconductor element of first embodiment of the invention;

The equivalent circuit diagram of Fig. 4 example semiconductor element of the present invention;

Fig. 5 A and Fig. 5 B are the graphs of a relation that shows existing skill and drain current of the present invention and grid voltage;

Fig. 6 is the cutaway view of the semiconductor element of second embodiment of the invention.

Component symbol explanation among the figure:

40 semiconductor elements

42 N type substrates

50 P type traps

52 source diffusion region

54 drain diffusion regions

56 gate oxides

58 grids

60,62 insulation tanks

64 substrate contact diffusion zones

70 nmos pass transistors

80 junction diodes

90 resistance

140 semiconductor elements, 142 P type substrates

150 N type traps, 152 source diffusion region, 154 drain diffusion regions, 156 gate oxides, 158 grids

160 insulation tanks, 162 insulation tanks, 164 substrate contact diffusion zones

200 biasing devices, 201,203,205,207 curves

210 P transistor npn npn switches

Embodiment

Fig. 3 is the cutaway view of the semiconductor element 40 of first embodiment of the invention.As shown in Figure 3, this semiconductor element 40 comprises a N type substrate 42, and is arranged on P type well region 50, in this N type substrate 42 and is arranged on gate insulation layer 56, that N+ type drain diffusion regions 54 and N+ type source diffusion region 52, in this P type well region 50 be arranged on these P type well region 50 surfaces and is arranged on grid 58, on this gate insulation layer 56 and is arranged on N+ type substrate contact diffusion zone 64 and in this P type well region 64 and is arranged on insulation tank 62 in this P type well region 64.

This insulation tank 62 is arranged between this N+ type substrate contact diffusion zone 64 and this drain diffusion regions 54, and the degree of depth of this insulation tank 62 is greater than the junction depth of this drain diffusion regions 54.Though the semiconductor element 40 of Fig. 3 example is that N+ type substrate contact diffusion zone 64 and insulation tank 62 are arranged on drain diffusion regions 54 sides, is familiar with this technical staff and should be appreciated that this N+ type substrate contact diffusion zone 64 and this insulation tank 62 also can be arranged on this source diffusion region 52 sides.

The equivalent circuit diagram of Fig. 4 example semiconductor element 40 of the present invention.As shown in Figure 4, semiconductor element 40 can be considered the resistance 90 that is electrically connected this nmos pass transistor 70 and this junction diode 80 by a nmos pass transistor 70, a junction diode 80 and and is constituted.Please refer to Fig. 3, junction diode 80 can be considered by this N+ type substrate contact diffusion zone 64 and this P type well region 50 and constitutes, and this resistance 90 then is the intrinsic resistance of this P type well region 50.

When nmos pass transistor 70 conductings, the electric current that drain diffusion regions 54 and source diffusion region are 52 will produce electron-hole pair because of hot carrier's effect.Electronics will flow to drain diffusion regions 52, and semiconductor element 40 will be flowed out through N+ type substrate contact diffusion zone 64 in the hole, force junction diode 80 conducting slightly, and make P type well region 50 present about 0.3 to 0.4 volt positive voltage.Therefore, 52 of P type well region 50 and source diffusion region will produce 0.3 to 0.4 volt bias voltage, make the cut-in voltage of nmos pass transistor 70 descend.When nmos pass transistor 70 is closed, 52 of drain diffusion regions 54 and source diffusion region without any the conducting electric current, cut-in voltage will remain unchanged.

Fig. 5 A and Fig. 5 B show the graph of a relation of prior art and drain current of the present invention and grid voltage, and wherein curve 201 and 205 is represented semiconductor element 40 of the present invention, and curve 203 and 207 is the element of representative graph 1 then.Please refer to the curve 201 and 203 of Fig. 5 A, when the present invention and prior art were zero at grid voltage, drain current was all less than 10 ^-9Ampere, that is semiconductor element of the present invention 40 only has very low leakage current when closing.Please refer to Fig. 5 B, the curve 207 of representing prior art just begins to produce drain current when about 0.6 volt of grid voltage.And curve 205 of the present invention promptly produced drain current, that is the cut-in voltage of semiconductor element of the present invention 40 has been reduced to 0.4 volt when about 0.4 volt of grid voltage.In addition, curve 205 increases by 13% at the drain current of linear zone than curve 207, i.e. the present invention has the effect that improves drain current.

Fig. 6 is the cutaway view of the semiconductor element 140 of second embodiment of the invention.As shown in Figure 6, this semiconductor element 140 comprises a P type substrate 142, and is arranged on N type well region 150, in this P type substrate 142 and is arranged on gate insulation layer 156, that P+ type drain diffusion regions 154 and P+ type source diffusion region 152, in this N type well region 150 be arranged on these N type well region 150 surfaces and is arranged on grid 158, on this gate insulation layer 156 and is arranged on a P+ type substrate contact diffusion zone 164 in this N type well region 150 and an insulation tank 162 that is arranged in this N type well region 150.

This insulation tank 162 is arranged between this P+ type substrate contact diffusion zone 164 and this drain diffusion regions 154, and the degree of depth of this insulation tank 162 is greater than the junction depth of this drain diffusion regions 154.Though the semiconductor element 140 of Fig. 6 example is that P+ type substrate contact diffusion zone 164 and insulation tank 162 are arranged on this drain diffusion regions 154 sides, the personnel that are familiar with this technology should be appreciated that this P+ type substrate contact diffusion zone 164 and this insulation tank 162 also can be arranged on this source diffusion region 152 sides.

Compared to existing skill, the present invention has following advantage:

1. semiconductor element of the present invention has quite simple structure, and does not need to use external circuit to control the substrate of its metal oxide semiconductor transistor and the bias voltage of source electrode.

2. metal oxide semiconductor transistor of the present invention maintains very low leakage current when closing, and can improve 13% drain current when conducting.

Technology contents of the present invention and technical characterstic disclose as above, yet the personage who is familiar with this technology still may be based on teaching of the present invention and announcement and done all replacement and modifications that does not deviate from spirit of the present invention.Therefore, protection scope of the present invention should be not limited to the content that embodiment discloses, and should comprise various do not deviate from replacement of the present invention and modifications, and is contained by the present patent application claim.

Claims (15)

1. semiconductor element, comprise: a substrate, is arranged on well region, in this substrate and is arranged on gate insulation layer, that drain diffusion regions in this well region and source diffusion region, be arranged on this well region surface and is arranged on grid, on this gate insulation layer and is arranged on substrate contact diffusion zone in this well region, and is arranged at least one insulation tank in this well region; The conductivity of this substrate contact diffusion zone is opposite with the conductivity of this well region.

2. semiconductor element according to claim 1 it is characterized in that described well region belongs to the P-type conduction kenel, and this substrate contact diffusion zone belongs to N type conductivity.

3. semiconductor element according to claim 1 is characterized in that described well region belongs to N type conductivity, and this substrate contact diffusion zone is to belong to the P-type conduction kenel.

4. semiconductor element according to claim 1 is characterized in that described insulation tank is arranged between this substrate contact diffusion zone and this drain diffusion regions.

5. semiconductor element according to claim 4 is characterized in that the junction depth of the degree of depth of described insulation tank greater than this drain diffusion regions.

6. semiconductor element according to claim 1 is characterized in that described insulation tank is arranged between this substrate contact diffusion zone and this source diffusion region.

7. semiconductor element according to claim 6 is characterized in that the junction depth of the degree of depth of described insulation tank greater than this source diffusion region.

8. semiconductor element, comprise: a substrate, is arranged on well region, in this substrate and is arranged on the resistance that junction diode that substrate contact diffusion zone in this well region, is made of this well region and this substrate contact diffusion zone, is made of the intrinsic resistance of this well region, and a metal oxide half field effect transistor that is electrically connected in this resistance.

9. semiconductor element according to claim 8, it is characterized in that described metal oxide half field effect transistor comprises: one is arranged on the surperficial gate insulation layer that drain diffusion regions in this well region and source diffusion region, are arranged on this well region, and a grid that is arranged on this gate insulation layer;

10. semiconductor element according to claim 9 is characterized in that it comprises an insulation tank that is arranged between this substrate contact diffusion zone and this drain diffusion regions in addition.

11. semiconductor element according to claim 10 is characterized in that the junction depth of the degree of depth of described insulation tank greater than this drain diffusion regions.

12. semiconductor element according to claim 9 is characterized in that the junction depth of the degree of depth of described insulation tank greater than this source diffusion region.

13. semiconductor element according to claim 10 is characterized in that the junction depth of the degree of depth of described insulation tank greater than this source diffusion region.

14. semiconductor element according to claim 9 it is characterized in that described well region belongs to the P-type conduction kenel, and this substrate contact diffusion zone belongs to N type conductivity.

15. semiconductor element according to claim 9 it is characterized in that described well region belongs to N type conductivity, and this substrate contact diffusion zone belongs to the P-type conduction kenel.

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