CN100424875C - Semiconductor device with a plurality of semiconductor chips - Google Patents

Abstract

The semiconductor element comprises a substrate with a well region, a drain diffusion region and a source diffusion region which are arranged in the well region, a gate insulating layer arranged on the surface of the well region, a gate arranged on the gate insulating layer, a substrate contact diffusion region arranged in the well region and an insulating groove. The substrate contact diffusion region has a conductivity type opposite to that of the well region. The semiconductor device of the present invention can be regarded as being composed of a metal oxide semiconductor transistor, a junction diode, and a resistor electrically connected to the metal oxide semiconductor transistor and the junction diode. The junction diode can be regarded as being formed by the substrate contact diffusion region and the well region, and the resistance is the intrinsic resistance of the well region.

Description

semiconductor element

technical field

The present invention relates to a semiconductor element, in particular to a semiconductor element including a metal-oxide-semiconductor transistor with a dynamic turn-on voltage.

Background technique

Metal Oxide Semiconductor Field Effect Transistors (MOSFETs) have been widely used in integrated circuits due to their advantages of low power consumption, high reliability and flexible circuit design. In order to have the best working performance, the turn-on voltage of the transistor is designed to have a very low leakage current when it is turned off, and maintain a high saturation current when it is turned on. The saturation current of the transistor when it is turned on is expressed by the following formula:

${\mathrm{<span\; class="notranslate">\; I</span>}}_{\mathrm{<span\; class="notranslate">\; D.</span>}}<span\; class="notranslate">\; =</span>\frac{\mathrm{<span\; class="notranslate">\; 1</span>}}{\mathrm{<span\; class="notranslate">\; 2</span>}}{\mathrm{<span\; class="notranslate">\; k</span>}}_{\mathrm{<span\; class="notranslate">\; no</span>}}^{<span\; class="notranslate">\; \&prime;</span>}<span\; class="notranslate">\; (</span>\frac{\mathrm{<span\; class="notranslate">\; W</span>}}{\mathrm{<span\; class="notranslate">\; L</span>}}<span\; class="notranslate">\; )</span>{<span\; class="notranslate">\; (</span>{\mathrm{<span\; class="notranslate">\; V</span>}}_{\mathrm{<span\; class="notranslate">\; GS</span>}}<span\; class="notranslate">\; -</span>{\mathrm{<span\; class="notranslate">\; V</span>}}_{\mathrm{<span\; class="notranslate">\; t</span>}}<span\; class="notranslate">\; )</span>}^{\mathrm{<span\; class="notranslate">\; 2</span>}}$

Among them, V _t represents the turn-on voltage, V _GS represents the voltage difference between the gate and the source, k' _n represents the transconductance parameter, L represents the channel length, and W represents the channel width. Generally speaking, transistors are designed to have a higher turn-on voltage to reduce or avoid leakage current when the transistor is turned off. However, according to the above formula, a higher turn-on voltage will reduce the saturation current value when the transistor is turned on. The turn-on voltage of the transistor can be expressed as:

${\mathrm{<span\; class="notranslate">\; V</span>}}_{\mathrm{<span\; class="notranslate">\; t</span>}}<span\; class="notranslate">\; =</span>{\mathrm{<span\; class="notranslate">\; <figure-callout\; id="0"\; label="V\; t"\; filenames="C0314970600121.png,C0314970600122.png"\; state="\{\{state\}\}">V</figure-callout></span><figure-callout\; id="0"\; label="V\; t"\; filenames="C0314970600121.png,C0314970600122.png"\; state="\{\{state\}\}">\; </figure-callout>}}_{\mathrm{<span\; class="notranslate">\; </span>}}<span\; class="notranslate">\; \&PlusMinus;</span>\mathrm{<span\; class="notranslate">\; \&gamma;</span>}<span\; class="notranslate">\; [</span>\sqrt{\mathrm{<span\; class="notranslate">\; 2</span>}{\mathrm{<span\; class="notranslate">\; \&phi;</span>}}_{\mathrm{<span\; class="notranslate">\; f</span>}}<span\; class="notranslate">\; -</span>{\mathrm{<span\; class="notranslate">\; V</span>}}_{\mathrm{<span\; class="notranslate">\; SB</span>}}}<span\; class="notranslate">\; -</span>\sqrt{{\mathrm{<span\; class="notranslate">\; 2</span>}\mathrm{<span\; class="notranslate">\; \&phi;</span>}}_{\mathrm{<span\; class="notranslate">\; f</span>}}}<span\; class="notranslate">\; ]</span>$

Among them, V _t0 represents the turn-on voltage when the bias voltage of the source and the base is 0, V _SB represents the bias value of the source and the substrate, and 2φ _f represents the surface of the source in strong inversion potential energy. It can be seen from the above formula that the turn-on voltage of the transistor can be adjusted by changing the bias voltage of the source and the substrate.

FIG. 1 is a cross-sectional view of an NMOS transistor 10 disclosed in US Patent No. 6,166,584 (hereinafter referred to as the '584 patent). As shown in FIG. 1 , the NMOS transistor 10 includes a P-type substrate 24 , a source diffusion region 14 , a drain diffusion region 16 , a gate 20 and a channel 28 . The potential of the P-type substrate 24 is controlled by the external voltage of the P+-type substrate contacting the diffusion region 26 . That is, the '584 patent uses an external control circuit to control the potential of the P-type substrate 24, thereby adjusting the turn-on voltage of the NMOS transistor 10.

FIG. 2 is a schematic diagram of a transistor with a dynamic turn-on voltage disclosed in US Patent No. 6,124,618 (hereinafter referred to as the '618 patent). As shown in FIG. 2 , the NMOS transistor 100 uses a bias device 200 to control the potential of the substrate 130 to adjust the turn-on voltage of the NMOS transistor 100 .

Although the techniques disclosed in the '584 patent and the '618 patent can both adjust the turn-on voltage of the transistor. However, both the techniques disclosed in the '584 patent and the '618 patent must use an external voltage control circuit to control the substrate voltage of the transistor, which will make the transistor circuit with a dynamic turn-on voltage more complicated.

Contents of the invention

The main object of the present invention is to provide a semiconductor device including a metal-oxide-semiconductor transistor with a dynamic turn-on voltage.

To achieve the above purpose, the present invention discloses a semiconductor device. The semiconductor element comprises a substrate with a well region, a drain diffused region and a source diffused region arranged in the well region, a gate insulating layer arranged on the surface of the well region, a gate insulating layer arranged on the gate insulating layer A gate on the well, a substrate contact diffusion region arranged in the well region, and an insulating groove arranged in the well region. The well region can be of P-type conductivity, while the substrate contact diffusion region is of N-type conductivity. The insulation groove is arranged between the substrate contact diffusion region and the drain diffusion region or between the substrate contact diffusion region and the source diffusion region. The depth of the insulating groove is greater than the junction depth of the drain diffusion region or the source diffusion region. The semiconductor device of the present invention can be regarded as composed of a metal oxide semiconductor transistor, a junction diode and a resistor electrically connecting the metal oxide semiconductor transistor and the junction diode. The junction diode can be regarded as composed of the substrate contact diffusion region and the well region, and the resistance is the intrinsic resistance of the well region.

Compared with the prior art, the present invention has the following advantages:

1. The semiconductor element of the present invention has a relatively simple structure, and does not need to use an external circuit to control the bias voltages of the substrate and the source of the metal oxide semiconductor transistor thereof.

2. The metal oxide semiconductor field effect transistor of the present invention maintains a very low leakage current when it is turned off, and can increase the drain current by 13% when it is turned on.

Description of drawings

FIG. 1 is a cross-sectional view of an NMOS transistor disclosed in US Patent No. 6,166,584;

FIG. 2 is a schematic diagram of a semiconductor device with a dynamic turn-on voltage disclosed in US Pat. No. 6,124,618.

3 is a cross-sectional view of a semiconductor element according to a first embodiment of the present invention;

Fig. 4 illustrates the equivalent circuit diagram of the semiconductor element of the present invention;

5A and 5B are graphs showing the relationship between drain current and gate voltage in the prior art and the present invention;

6 is a cross-sectional view of a semiconductor element according to a second embodiment of the present invention.

Explanation of component symbols in the figure:

40 semiconductor components

42 N-type substrate

50 P-well

52 source diffusion area

54 drain diffusion area

56 Gate Oxide

58 grid

60, 62 insulation groove

64 substrate contact diffusion area

70 NMOS transistors

80 junction diode

90 resistors

140 semiconductor element, 142 P type substrate

150 N-type well, 152 source diffusion region, 154 drain diffusion region, 156 gate oxide layer, 158 gate

160 insulation groove, 162 insulation groove, 164 substrate contact diffusion area

200 bias device, 201, 203, 205, 207 curves

210 P-type transistor switch

Detailed ways

FIG. 3 is a cross-sectional view of a semiconductor element 40 according to a first embodiment of the present invention. As shown in FIG. 3 , the semiconductor element 40 includes an N-type substrate 42, a P-type well region 50 disposed in the N-type substrate 42, and an N+ type drain disposed in the P-type well region 50. Diffusion region 54 and N+ type source diffusion region 52, a gate insulating layer 56 arranged on the surface of the P-type well region 50, a gate 58 arranged on the gate insulating layer 56, a gate insulating layer 58 arranged on the surface of the P-type well region The N+ type substrate in 64 is in contact with the diffusion region 64 and an insulating trench 62 disposed in the P type well region 64 .

The insulating trench 62 is disposed between the N+ type substrate contact diffusion region 64 and the drain diffusion region 54 , and the depth of the insulating trench 62 is greater than the junction depth of the drain diffusion region 54 . Although the semiconductor element 40 shown in FIG. 3 is that the N+ type substrate contact diffusion region 64 and the insulating groove 62 are arranged on the drain diffusion region 54 side, those skilled in the art should understand that the N+ type substrate contact diffusion region 64 and the insulating groove 62 Grooves 62 may also be provided on the source diffusion region 52 side.

FIG. 4 illustrates an equivalent circuit diagram of a semiconductor element 40 of the present invention. As shown in FIG. 4 , the semiconductor device 40 can be considered to be composed of an NMOS transistor 70 , a junction diode 80 and a resistor 90 electrically connecting the NMOS transistor 70 and the junction diode 80 . Please refer to FIG. 3 , the junction diode 80 can be regarded as composed of the N+ type substrate contact diffusion region 64 and the P-type well region 50 , and the resistor 90 is the intrinsic resistance of the P-type well region 50 .

When the NMOS transistor 70 is turned on, the current between the drain diffusion region 54 and the source diffusion region 52 will generate electron-hole pairs due to the hot carrier effect. Electrons will flow to the drain diffusion region 52, and holes will flow out of the semiconductor element 40 through the N+ type substrate contact diffusion region 64, forcing the junction diode 80 to conduct slightly, and making the P type well region 50 exhibit a voltage of about 0.3 to 0.4 volts. positive voltage. Therefore, a bias voltage of 0.3 to 0.4 volts is generated between the P-type well region 50 and the source diffusion region 52 , so that the turn-on voltage of the NMOS transistor 70 drops. When the NMOS transistor 70 is turned off, there is no conduction current between the drain diffusion region 54 and the source diffusion region 52 , and the turn-on voltage remains unchanged.

5A and 5B show the relationship diagrams of drain current and gate voltage in the prior art and the present invention, wherein curves 201 and 205 represent the semiconductor device 40 of the present invention, and curves 203 and 207 represent the device of FIG. 1 . Please refer to the curves 201 and 203 of FIG. 5A. When the gate voltage of the present invention and the prior art is zero, the drain current is less than ^10-9 amperes, that is, the semiconductor element 40 of the present invention has only a very low current when it is turned off. leakage current. Please refer to FIG. 5B , the curve 207 representing the prior art begins to generate drain current when the gate voltage is about 0.6 volts. On the curve 205 of the present invention, when the gate voltage is about 0.4 volts, the drain current has already been generated, that is, the turn-on voltage of the semiconductor device 40 of the present invention has dropped to 0.4 volts. In addition, the drain current of the curve 205 in the linear region is 13% higher than that of the curve 207, that is, the present invention has the effect of increasing the drain current.

FIG. 6 is a cross-sectional view of a semiconductor device 140 according to a second embodiment of the present invention. As shown in FIG. 6, the semiconductor element 140 includes a P-type substrate 142, an N-type well region 150 disposed in the P-type substrate 142, and a P+ type drain disposed in the N-type well region 150. Diffusion region 154 and P+ type source diffusion region 152, a gate insulating layer 156 disposed on the surface of the N-type well region 150, a gate 158 disposed on the gate insulating layer 156, a gate insulating layer 158 disposed on the N-type well region The P+ type substrate in 150 is in contact with the diffusion region 164 and an insulating trench 162 disposed in the N type well region 150 .

The insulating trench 162 is disposed between the P+ type substrate contact diffusion region 164 and the drain diffusion region 154 , and the depth of the insulating trench 162 is greater than the junction depth of the drain diffusion region 154 . Although the semiconductor element 140 illustrated in FIG. 6 is that the P+ type substrate contact diffusion region 164 and the insulating groove 162 are arranged on the drain diffusion region 154 side, those skilled in the art should understand that the P+ type substrate contact diffusion region 164 and the The insulating trench 162 can also be disposed on the side of the source diffusion region 152 .

Compared with the prior art, the present invention has the following advantages:

1. The semiconductor element of the present invention has a relatively simple structure, and does not need to use an external circuit to control the bias voltages of the substrate and the source of the metal oxide semiconductor transistor thereof.

2. The metal oxide semiconductor transistor of the present invention maintains a very low leakage current when it is turned off, and can increase the drain current by 13% when it is turned on.

The technical content and technical features of the present invention have been disclosed above, but those skilled in the art may still make various substitutions and modifications based on the teaching and disclosure of the present invention without departing from the spirit of the present invention. Therefore, the protection scope of the present invention should not be limited to the contents disclosed in the embodiments, but should include various replacements and modifications that do not depart from the present invention, and are covered by the claims of this patent application.

Claims (15)

1. semiconductor element, comprise: a substrate, is arranged on well region, in this substrate and is arranged on gate insulation layer, that drain diffusion regions in this well region and source diffusion region, be arranged on this well region surface and is arranged on grid, on this gate insulation layer and is arranged on substrate contact diffusion zone in this well region, and is arranged at least one insulation tank in this well region; The conductivity of this substrate contact diffusion zone is opposite with the conductivity of this well region.

2. semiconductor element according to claim 1 it is characterized in that described well region belongs to the P-type conduction kenel, and this substrate contact diffusion zone belongs to N type conductivity.

3. semiconductor element according to claim 1 is characterized in that described well region belongs to N type conductivity, and this substrate contact diffusion zone is to belong to the P-type conduction kenel.

4. semiconductor element according to claim 1 is characterized in that described insulation tank is arranged between this substrate contact diffusion zone and this drain diffusion regions.

5. semiconductor element according to claim 4 is characterized in that the junction depth of the degree of depth of described insulation tank greater than this drain diffusion regions.

6. semiconductor element according to claim 1 is characterized in that described insulation tank is arranged between this substrate contact diffusion zone and this source diffusion region.

7. semiconductor element according to claim 6 is characterized in that the junction depth of the degree of depth of described insulation tank greater than this source diffusion region.

8. semiconductor element, comprise: a substrate, is arranged on well region, in this substrate and is arranged on the resistance that junction diode that substrate contact diffusion zone in this well region, is made of this well region and this substrate contact diffusion zone, is made of the intrinsic resistance of this well region, and a metal oxide half field effect transistor that is electrically connected in this resistance.

9. semiconductor element according to claim 8, it is characterized in that described metal oxide half field effect transistor comprises: one is arranged on the surperficial gate insulation layer that drain diffusion regions in this well region and source diffusion region, are arranged on this well region, and a grid that is arranged on this gate insulation layer;

10. semiconductor element according to claim 9 is characterized in that it comprises an insulation tank that is arranged between this substrate contact diffusion zone and this drain diffusion regions in addition.

11. semiconductor element according to claim 10 is characterized in that the junction depth of the degree of depth of described insulation tank greater than this drain diffusion regions.

12. semiconductor element according to claim 9 is characterized in that the junction depth of the degree of depth of described insulation tank greater than this source diffusion region.

13. semiconductor element according to claim 10 is characterized in that the junction depth of the degree of depth of described insulation tank greater than this source diffusion region.

14. semiconductor element according to claim 9 it is characterized in that described well region belongs to the P-type conduction kenel, and this substrate contact diffusion zone belongs to N type conductivity.

15. semiconductor element according to claim 9 it is characterized in that described well region belongs to N type conductivity, and this substrate contact diffusion zone belongs to the P-type conduction kenel.

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