CN100424707C - Method for controlling circuit layout to execute error-correcting program - Google Patents
Method for controlling circuit layout to execute error-correcting program Download PDFInfo
- Publication number
- CN100424707C CN100424707C CNB2004100692070A CN200410069207A CN100424707C CN 100424707 C CN100424707 C CN 100424707C CN B2004100692070 A CNB2004100692070 A CN B2004100692070A CN 200410069207 A CN200410069207 A CN 200410069207A CN 100424707 C CN100424707 C CN 100424707C
- Authority
- CN
- China
- Prior art keywords
- error correction
- circuit layout
- option
- error
- content
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Expired - Fee Related
Links
Images
Landscapes
- Design And Manufacture Of Integrated Circuits (AREA)
Abstract
The present invention relates to a method for controlling a circuit layout to execute error-correcting programs, the method provides a user operation interface for users to open a circuit layout file to be edited and displays error correcting options which are not executed, and controls the execution of each error-correcting program through predetermined alarm content, so that each error-correcting program in the design of the circuit layout can be carried out automatically in time to maintain the quality of the design of the circuit layout.
Description
Technical field
The present invention relates to the method that a kind of circuit layout (layout) error correcting routine is carried out, particularly a kind of carrying out according to the main design phase of circuit layout automatically performs the method for the control error correcting routine execution of error correcting routine.
Background technology
The life of popularizing to people of electronic installation has brought many facilities and has become indispensable article, and as electronic package assign with link interface circuit board (as, printed circuit board (printed circuitboard, PCB), surface-mounted integrated circuit, soft printed circuit board (flexible print circuit, FPC)) are the basic spare parts that is widely used in the various electronic correlation products.
Along with existing market compact and requirement at a high speed to electronic installation, so each manufacturer there's no one who doesn't or isn't wishes to dwindle the area of circuit board to satisfy the demand in market, and along with the restriction of manufacturer to board area, make the also relative increase of the degree of difficulty of design (as circuit layout (layout)) of circuit board and even more important, wherein the quality of circuit layout can directly influence the quality and increase production cost of electronic installation, or even the reputation of enterprise and business opportunity.
Therefore for instance, when circuit layout had flaw, the electronic installation of producing by this circuit layout may have many unacceptable products, needed many times of doing over again of waste and caused the increase of production cost, or directly influence product quality.And all can understand the reference of product evaluation at any time by network as shopping goods the present buyer of network prosperity, therefore the instability quality product spreads through the internet and may influence its sales volume, or even releases also relative being affected of possibility of reputation of the enterprise of this product.
Designing program of general circuit layout mainly is divided into four-stage, and this four-stage is respectively the location and arranges (placement) stage, circuit layout (routing) stage, measuring point layout (test point) stage and distribution (release) stage.Wherein the capital of each design phase directly has influence on the quality of product.
Circuit common layout application program all provides the error correction option, when providing circuit layout personnel (layoutengineer) to finish in each design phase, utilizes the error correction option to find out the design disappearance and revise timely.But convenient inadequately because of the use operation-interface that is provided, therefore the execution error correcting routine is forgotten because of carelessness by regular meeting when the circuit layout personnel are busy, and causes many losses.
For instance, common error correcting routine also fails to propose caution after each stage finishes, which allowing the circuit layout personnel carry out error correcting routine in good time, therefore when wrong the generation, will be difficult to be confirmed to be the stage produce, and relevant design content all may produce mistake in the lump and need redesign.
Therefore, how to control error correcting routine in good time execution in the design phase of circuit layout, reducing wrong the generation and the time and keep quality of design of doing over again, real be each enterprise and circuit layout personnel look forward to jointly.
Summary of the invention
The objective of the invention is to for addressing the above problem, propose a kind of circuit layout (layout) and carry out the control method of error correcting routine, by confirming finishing of each design phase of circuit layout, in time allow each error correcting routine automatically perform, with the mistake that prevents that circuit layout personnel carelessness from being caused, and minimizing circuit layout personnel's workload.
The method comprises the following steps: to provide has the user's operation-interface that opens beginning option and error correction option; Open desire editor's circuit layout archives by the aforesaid beginning option that opens, have the program that to confirm the executing state of each error correction option in these circuit layout archives.According to the executing state of being noted down on the program, unenforced error correction option is shown on user's operation-interface then.
Confirm whether the caution content that unenforced each error correction option had is identical with its pairing detection content; When affirmation is identical, makes a default error correcting routine carry out, and will impel the executing state of the error correction option of this error correcting routine execution to switch to executed; According to the switching of executing state, change the content of program again; Confirm whether to also have unenforced error correction option again, if there is not unenforced error correction option, the design that then is considered as circuit layout is all finished.
Description of drawings
Fig. 1 is a method flow diagram of the present invention; And
Fig. 2 is the use synoptic diagram of user's operation-interface of the present invention.
Wherein, Reference numeral is as follows:
10--user's operation-interface
11--opens the beginning option
12--location error correction option
13--circuit error correction option
14--measuring point error correction option
15--distribution error correction option
Step 200 provides has the user's operation-interface that opens beginning option and error correction option
Step 210 is opened the circuit layout archives with program by opening the beginning option
Step 220 is that unenforced each error correction option is shown on user's operation-interface according to program with executing state
Whether the caution content that unenforced each the error correction option of step 230 affirmation is had is identical with its pairing detection content
The default error correcting routine of step 240 order begins to carry out, and the executing state of error correction option is switched to executed
Step 250 changes the content of program according to the switching of executing state
Step 260 confirms whether to have unenforced test option
Embodiment
For making purpose of the present invention, feature and function thereof are had further understanding, conjunction with figs. is described as follows:
Fig. 1 carries out the method flow diagram of the control method of error correcting routine for circuit layout of the present invention (layout).The main process step of present embodiment is as follows as shown in the figure:
At first, provide and have the user's operation-interface (step 200) that opens beginning option and several error correction options; But open circuit diagram in the beginning option open circuit html Layout Files HTML continuing repairing volume work, and the error correction option is according to four main design phases in the general circuit layout and corresponding setting.
These four design phases are respectively location layout (placement) stage, circuit layout (routing) stage, measuring point layout (test point) stage and distribution (release) stage, and the option of institute's relative set is for locating error correction (placement check) option, circuit error correction (routing check) option, measuring point error correction (test point check) option and issuing error correction (release check) option.
Wherein, error correction option in location is in order to confirm whether assembly is put to circuit diagram fully; Whether circuit error correction option all has and has drawn suitable cabling (trace) in order to confirm to put each assembly in the circuit diagram; Measuring point error correction option then is to be used for confirming whether measuring point is set.This measuring point is the gauge point of production unit in order to basic signal and function in the affirmation circuit board.
In addition, distribution error correction option is the situation in order to confirm whether cabling has short circuit or open circuit then, and whether egative film (artwork) shelves complete.The egative film file is to generate by circuit diagram conversion to be used for transferring to other unit and to carry out the required archives of system work afterwards that continue.
Then, open circuit layout archives (step 210) by opening the beginning option with program; Writing down the executing state (as, executed or do not carry out) of each error correction option in the program.Circuit diagram and egative film file except program, have more been comprised in these circuit layout archives ... Deng.But and circuit layout files title be provided with need comprise a version of display information (as, study version, formal version or distribution version) representative number.Wherein, the difference that studies version and formal version is: formal version is set up measuring point in circuit diagram, and the difference of formal in addition version and distribution version edition has increased the egative film shelves for issuing.
Then, according to program unenforced each error correction option is shown on user's operation-interface (step 220).Then, confirm caution content that unenforced each error correction option had and its pairing detection content whether identical (step 230) in regular turn; Each is warned content and is used for confirming whether each pairing design phase of error correction option finish, and respectively detecting content then is to select according to each pairing design phase of error correction option.
For example, the location error correction pairing design phase of option is the location arrangement stage, and confirm that method that the location arrangement stage finishes is zero for the value of confirming not put in the circuit diagram in the circuit layout archives assembly, therefore warn content and will be set at zero, and the value of not putting assembly will be considered as detecting content.Therefore when the caution content is same as the detection content, represent that promptly each assembly all put to circuit diagram (value of not putting assembly equals zero).
The pairing design phase of circuit error correction option is the circuit arrangement stage, and confirms that the method that the circuit arrangement stage is finished is zero for confirming that cabling (trace) value of (drawing) is finished in not setting.Therefore warn content and will be set at zero, and uncompleted cabling value will be considered as detecting content.And when the caution content is same as the detection content, represent that promptly the cabling of each assembly is set all.
The pairing design phase of measuring point error correction option is the measuring point arrangement stage, and confirms that method that the measuring point arrangement stage finishes number is an official release for the representative of represent version in the file name of confirming the circuit layout archives.Therefore warn the representative number that content will be set at official release, and the representative of file name number will be as detecting content.And be same as when detecting content when the caution content, promptly measuring point has been set and has been finished in the representative circuit schematic.
The distribution error correction pairing design phase of option is a distribution phase, and confirms that the method that distribution phase is finished has had the egative film shelves for confirming in the circuit layout archives.Therefore warn extension name or shelves name that content will be set at the egative film shelves, and the extension name of file name mediella shelves or a shelves star are considered as detecting content.Therefore when the caution content is same as the detection content, had egative film shelves (the egative film shelves complete) in the indication circuit html Layout Files HTML.
Then, when comparison result when being identical, then impel default error correcting routine to begin to carry out, and the executing state of error correction option is switched to executed (step 240); When the comparison result of each error correction option is identical, represent its institute to finish corresponding each design phase, can impel the circuit layout application program to begin to carry out corresponding error correcting routine this moment, to confirm the mistake in the design.
Then, according to the switching of executing state, the content (step 250) of change program; After each error correction option was finished respectively, it was shown in executing state on user's operation-interface with change, with the up-to-date error correction state of alert circuit layout personnel, and the program of each error correction option executing state of record in the circuit layout archives was upgraded relatively.
At last, confirm whether to have unenforced error correction option (step 260); When on confirming user's operation-interface, not having unenforced error correction option, then represent all design phases all to finish and then finish all programs.In addition when confirming still to have unenforced error correction option, then re-execute step 230 to allow the execution that continues of unenforced error correction option.
In addition, when the comparison result of step 230 when being inequality, the execution in step 260 that then can continue is to confirm whether to have unenforced error correction option.
Please consult the use synoptic diagram of Fig. 2 again for user's operation-interface.Show in user's operation-interface 10 as shown in the figure have open beginning option one 1 and several error correction options (as, location error correction option one 2, circuit error correction option one 3, measuring point error correction option one 4 and distribution error correction option one 5), wherein each error correction option can be by with thickness font, font bottom line or in modes such as change color, as the executing state of prompting mode with each error correction option of cue circuit layout personnel.
For instance, open beginning option one 1 and location error correction option one 2 and show, represent that these two options carried out (finishing) with thin font; And circuit error correction option one 3 shows with boldface type and represents that promptly this option carrying out; Measuring point error correction option one 4 and distribution error correction option one 5 show with boldface type demonstration and hypographous mode in addition, then represent these two options not carry out (not finishing as yet) as yet.The executing state of each error correction option represents that mode does not limit in the application of reality, as long as be able to allow the various states of circuit layout personnel identification.
By control method of the present invention, not only can allow the circuit layout personnel when the design of circuit layout, the whole error correcting routine of certain execution more can and then increase the stability of product with the quality of holding circuit topological design.
The above only is the present invention's preferred embodiment wherein, is not to be used for limiting practical range of the present invention; All according to equivalence variation and modification that the present invention did, be all the present invention and contain.
Claims (12)
1. the control method of a circuit layout to execute error-correcting program comprises the following steps:
One user's operation-interface is provided, and this user's operation-interface has and opens beginning option and more than one error correction option;
Open the beginning option by this and open circuit layout archives, these circuit layout archives have a program, and this program record is the executing state of this error correction option respectively;
Confirm that a caution content that is had in this shown on this user's operation-interface error correction option is identical with its pairing detection content;
Carry out and to have the corresponding error correcting routine of error correction option of identical content, and the executing state that will have this error correction option of identical content switches to executed with this;
According to the switching of the executing state of this error correction option, change the content of this program; And
Confirm not show on this user's operation-interface unenforced this error correction option.
2. the control method of circuit layout to execute error-correcting program as claimed in claim 1, it is characterized in that, when showing this error correction option on this user's operation-interface, promptly re-execute and confirm that this caution content that this shown error correction option is had on this user's operation-interface is identical step with its pairing this detection content.
3. the control method of circuit layout to execute error-correcting program as claimed in claim 1, it is characterized in that, when this caution content this detection content pairing with it that this shown error correction option is had on confirming user's operation-interface in regular turn is inequality, then reaffirm the step that does not show this error correction option on this user's operation-interface.
4. the control method of circuit layout to execute error-correcting program as claimed in claim 1, it is characterized in that, open the beginning option by this and open circuit layout archives, these circuit layout archives have a program, this program record is respectively after the step of the executing state of this error correction option, also can be included in to show on this user's operation-interface that executing state is unenforced respectively this this detection option.
5. the control method of circuit layout to execute error-correcting program as claimed in claim 1 is characterized in that, this error correcting routine is a circuit layout application program.
6. the control method of circuit layout to execute error-correcting program as claimed in claim 1 is characterized in that, this error correction option is a location error correction option, a circuit error correction option, a measuring point error correction option and a distribution error correction option.
7. the control method of circuit layout to execute error-correcting program as claimed in claim 6 is characterized in that, pairing this detection content of this caution content of this location error correction option is the shown value of not putting assembly of these circuit layout archives.
8. the control method of circuit layout to execute error-correcting program as claimed in claim 7 is characterized in that, this caution content of this location error correction option is zero.
9. the control method of circuit layout to execute error-correcting program as claimed in claim 6 is characterized in that, the pairing content that should detect of this caution content of this circuit error correction option is the shown cabling values that are not provided with as yet of these circuit layout archives.
10. the control method of circuit layout to execute error-correcting program as claimed in claim 9 is characterized in that, this caution content of this circuit error correction option is zero.
11. the control method of circuit layout to execute error-correcting program as claimed in claim 6 is characterized in that, this caution content of this measuring point error correction option is pairing, and should to detect content be to represent the representative number of official release in this circuit layout file name.
12. the control method of circuit layout to execute error-correcting program as claimed in claim 11 is characterized in that, the shelves name/extension name of the egative film shelves that pairing this detection content of this caution content of this distribution error correction option is had for these circuit layout archives.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CNB2004100692070A CN100424707C (en) | 2004-07-14 | 2004-07-14 | Method for controlling circuit layout to execute error-correcting program |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CNB2004100692070A CN100424707C (en) | 2004-07-14 | 2004-07-14 | Method for controlling circuit layout to execute error-correcting program |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| CN1722142A CN1722142A (en) | 2006-01-18 |
| CN100424707C true CN100424707C (en) | 2008-10-08 |
Family
ID=35912448
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| CNB2004100692070A Expired - Fee Related CN100424707C (en) | 2004-07-14 | 2004-07-14 | Method for controlling circuit layout to execute error-correcting program |
Country Status (1)
| Country | Link |
|---|---|
| CN (1) | CN100424707C (en) |
Citations (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US20030229862A1 (en) * | 2002-06-10 | 2003-12-11 | Sun Microsystems, Inc. | Patching technique for correction of minimum area and jog design rule violations |
| US20040019861A1 (en) * | 2002-07-23 | 2004-01-29 | Sun Microsystems, Inc. | Automated design rule violation correction when adding dummy geometries to a design layout |
-
2004
- 2004-07-14 CN CNB2004100692070A patent/CN100424707C/en not_active Expired - Fee Related
Patent Citations (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US20030229862A1 (en) * | 2002-06-10 | 2003-12-11 | Sun Microsystems, Inc. | Patching technique for correction of minimum area and jog design rule violations |
| US20040019861A1 (en) * | 2002-07-23 | 2004-01-29 | Sun Microsystems, Inc. | Automated design rule violation correction when adding dummy geometries to a design layout |
Also Published As
| Publication number | Publication date |
|---|---|
| CN1722142A (en) | 2006-01-18 |
Similar Documents
| Publication | Publication Date | Title |
|---|---|---|
| US6557002B1 (en) | Data management system for storing structural element data management program | |
| US7290182B2 (en) | Software tool for monitoring faults in an automation device | |
| WO1998015908A1 (en) | A product design production system and method | |
| JP6019316B2 (en) | Label printer and program | |
| JP2002091677A (en) | Input device and information terminal equipment | |
| CN100424707C (en) | Method for controlling circuit layout to execute error-correcting program | |
| JP2005085201A (en) | Article information processor | |
| JP2004318208A (en) | Product data management system and program | |
| JP2014086044A (en) | Design support program, method, and device | |
| CN108351633A (en) | The operation module of machine in food industry | |
| US8521622B2 (en) | Computer system for managing part order placement | |
| JP3794044B2 (en) | Parts information output method and parts selected by the parts information output method | |
| CN101770527A (en) | Method for modifying data of circuit components | |
| JPH11240210A (en) | Label-issuing machine | |
| JP2011170587A (en) | Software development support apparatus and method | |
| CN101556657A (en) | System and method for self-defining attribute | |
| JPH0667783A (en) | Menu type data input system | |
| JP2004178170A (en) | Design-manufacture data management system, and program | |
| JP2006195751A (en) | Design support system, and design support method | |
| US20110037715A1 (en) | Touch panel correcting apparatus and the method therefor | |
| JP2630888B2 (en) | Automatic equipment design equipment using CAD drawings | |
| CN116126331B (en) | Interactive flow chart generation method and device | |
| JPH11328536A (en) | Merchandise processor | |
| CN101174279A (en) | Method for comparing part information of different circuit diagram | |
| CN110039282B (en) | Disassembling method, device and equipment |
Legal Events
| Date | Code | Title | Description |
|---|---|---|---|
| C06 | Publication | ||
| PB01 | Publication | ||
| C10 | Entry into substantive examination | ||
| SE01 | Entry into force of request for substantive examination | ||
| C14 | Grant of patent or utility model | ||
| GR01 | Patent grant | ||
| C17 | Cessation of patent right | ||
| CF01 | Termination of patent right due to non-payment of annual fee |
Granted publication date: 20081008 Termination date: 20100714 |