CN100423229C - Method for forming contact window - Google Patents
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- CN100423229C CN100423229C CNB2005101316182A CN200510131618A CN100423229C CN 100423229 C CN100423229 C CN 100423229C CN B2005101316182 A CNB2005101316182 A CN B2005101316182A CN 200510131618 A CN200510131618 A CN 200510131618A CN 100423229 C CN100423229 C CN 100423229C
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Abstract
The invention is concerned with the method of forming the touching window, it is: first, provides the underlay, the underlay is with at least two conductive elements that are with clearance; forms the first dielectric layer to cover the conductive element and the clearance on the underlay, the first dielectric layer is with rift in the clearance; moves part of the first dielectric layer in the clearance to form a opening in order to extend the width of the rift; forms the second dielectric layer on the first dielectric layer, and fill in the opening; moves part of the second dielectric layer and part of the first dielectric layer in the clearance until emerge part of the underlay surface in order to form a touching window at the correspond opening; fills the conductive layer in the touching window.
Description
Technical field
The present invention relates to a kind of formation method of semiconductor element, relate in particular to a kind of formation method of contact hole.
Background technology
In the evolution of integrated circuit component, can reach the purpose of high speed operation and low power consumption by dwindling size of component.Yet owing to dwindle the restriction that the technology of component size is subjected to factors such as technology bottleneck, cost costliness at present, other are different from the technology of dwindling element so need development, to improve the drive current of element.Therefore, the someone proposes to utilize at transistorized channel region the mode of stress (stress) control, overcomes the limit of element downsizing.The method is the spacing that changes silicon (Si) lattice by applied stress, with the mobility (mobility) in increase electronics and hole, and then the usefulness of raising element.
Present a kind of method of utilizing the Stress Control mode to increase element efficiency, be to utilize silicon nitride layer to produce stress as contact hole etching stop layer (contact etch stop layer), improve the drive current (drive current) of element, to reach the purpose that increases element efficiency.Yet said method still has some problems and can't solve in technology, and has influence on the usefulness of element.
Figure 1A to Fig. 1 E is the flow process generalized section of existing contact hole formation method.
At first, please refer to Figure 1A, on substrate 100, form a plurality of metal oxide semiconductor transistors 102, and between the two adjacent metal oxide semiconductor transistors 102 gap 104 is arranged.
Then, please refer to Figure 1B, form one deck silicon nitride layer 106 above substrate 100, being used as is stressor layers, and this silicon nitride layer 106 covers entire substrate 100 and metal oxide semiconductor transistor 102.Because the thickness of silicon nitride layer 106 is relevant with its stress value, that is be that the thickness of silicon nitride layer 106 is thicker, then its stress value is bigger.So, when utilizing the thicker silicon nitride layer of formation thicknesses of layers, can produce slot (seam) 108 in the silicon nitride layer 106 in gap 104 usually, and it can badly influence the reliability of subsequent technique with the increase element efficiency.
Then, please refer to Fig. 1 C, on silicon nitride layer 106, form one dielectric layer 110.Because, produce slot 108 in the silicon nitride layer 106, so dielectric layer 110 can't cover silicon nitride layer 106 fully, and only cause in the slot 108 part to insert dielectric layer 110.Shown in the transmission electron microscope photo of Fig. 2, can find by the label among Fig. 2 200 can't be filled up by dielectric layer 110 fully in the slot 108 of silicon nitride layer 106.
Subsequently, please refer to Fig. 1 D, carry out an etch process, in silicon nitride layer 106 and dielectric layer 110, form a contact window 114.It should be noted that, owing to have the problem of slot 108 in the silicon nitride layer 106, therefore after carrying out etches both silicon nitride layer 106 and dielectric layer 110, can cause residue (residue) 112 in contact window 114 bottoms, shown in the label 300 in the transmission electron microscope photo of Fig. 3.
Afterwards, please refer to Fig. 1 E, in contact window 114, insert metal material layer, to form contact hole 116.Yet the residue 112 of contact window 114 bottoms can make the resistance of formed contact hole 116 be enhanced, even can cause contact hole 116 and 102 of metal oxide semiconductor transistors to produce short circuit, and has a strong impact on the reliability and the usefulness of element.
Hold above-mentionedly, how, can avoid influencing technology reliability and element efficiency, become the task of top priority of present semiconductor technology because of the rete defective that silicon nitride layer produced in the technology utilizing silicon nitride layer to produce stress with when increasing element efficiency.
Summary of the invention
In view of this, the purpose of this invention is to provide a kind of formation method of contact hole, can avoid because of producing defective in the rete, produce residue bottom the contact window, influence the usefulness of element and cause.
Another object of the present invention provides a kind of formation method of contact hole, can avoid the rete defective of generation in the stress layer, and influences the problem of element efficiency.
The present invention proposes a kind of formation method of contact hole, and the method provides a substrate, has been formed with at least two conductor elements on the substrate, and has the gap between two conductor elements.Then, above substrate, form first dielectric layer, cover above-mentioned two conductor elements, and insert in the gap.Wherein, be formed in first dielectric layer in the gap and have a slot.Then, remove part of first dielectric layer in the gap forming an opening, to enlarge the width of slot.Subsequently, on first dielectric layer, form second dielectric layer, and fill up opening.Afterwards, remove part second dielectric layer and part of first dielectric layer in the gap,, form a contact window with position in corresponding opening until exposing the part substrate surface.Then, in contact window, insert conductor layer.
Described according to embodiments of the invention, the material of the first above-mentioned dielectric layer for example is a silicon nitride.The thickness of first dielectric layer for example is between 100 to 2000 dusts.Preferably, the thickness of first dielectric layer for example is between 500 to 1500 dusts.More preferably, the thickness of first dielectric layer for example is the 1000 Izod right sides
Described according to embodiments of the invention, the above-mentioned part of first dielectric layer that removes in the gap to form hatch method for example is, prior to forming a photoresist layer on first dielectric layer, then, the photoresist layer is carried out a photoetching process, form the photoresist layer of a patterning, to expose the slot in first dielectric layer.Then, be etching mask with the photoresist layer of patterning, etching part first dielectric layer is to form opening.Afterwards, remove the photoresist layer of patterning.In one embodiment, before the photoresist layer forms, also can be included in and form a bottom anti-reflection layer on first dielectric layer.
Described according to embodiments of the invention, the material of the second above-mentioned dielectric layer for example is a silica.For example be phosphorosilicate glass, Pyrex, boron-phosphorosilicate glass or undoped silicon glass.
The present invention also proposes a kind of formation method of contact hole, and the method provides a substrate, has been formed with at least two metal oxide semiconductor transistors on the substrate, and has the gap between two metal oxide semiconductor transistors.Then, above substrate, form stressor layers, cover above-mentioned two metal oxide semiconductor transistors, and insert in the gap.Wherein, be formed in the stressor layers in the gap and have a slot.Then, remove part stressor layers in the gap forming an opening, to enlarge the width of slot.Afterwards, on stressor layers, form dielectric layer, and fill up opening.Subsequently, remove part electricity layer and part stressor layers in the gap,, form a contact window with position in corresponding opening until exposing the part substrate surface.Then, in contact window, insert conductor layer.
According to the formation method of the described contact hole of embodiments of the invention, the material of above-mentioned stressor layers for example is a silicon nitride.The stress of stressor layers for example is between 1 to 50GPa.Preferably, the stress of stressor layers for example is between 1 to 10GPa.In addition, the thickness of stressor layers for example is between 100 to 2000 dusts.Preferably, the thickness of stressor layers for example is between 500 to 1500 dusts.More preferably, the thickness of stressor layers for example is 1000 dusts.
Formation method according to the described contact hole of embodiments of the invention, the above-mentioned part stressor layers that removes in the gap for example is prior to forming a photoresist layer on the stressor layers with the method that forms opening, then, the photoresist layer is carried out a photoetching process, form the photoresist layer of a patterning, to expose the slot in the stressor layers.Then, be etching mask with the photoresist layer of patterning, the etching part stressor layers removes the photoresist layer of patterning to form after the opening.In one embodiment, before the photoresist layer forms, also can be included in and form a bottom anti-reflection layer on first dielectric layer.
According to the formation method of the described contact hole of embodiments of the invention, the material of above-mentioned dielectric layer for example is a silica.For example be phosphorosilicate glass, Pyrex, boron-phosphorosilicate glass or undoped silicon glass.
The present invention utilizes the width that enlarges slot in first dielectric layer (or stressor layers), can avoid thus causing residue in the contact window bottom, therefore formed contact hole does not just have resistance and is enhanced, or even causes short circuit and problem generations such as the reliability that has influence on element and usefulness.
For above-mentioned and other purposes, feature and advantage of the present invention can be become apparent, preferred embodiment cited below particularly, and conjunction with figs. are described in detail below.
Description of drawings
Figure 1A to Fig. 1 E is the flow process generalized section of existing contact hole formation method;
Fig. 2 is for having the transmission electron microscope photo of slot in the existing silicon nitride layer;
The transmission electron microscope photo that Fig. 3 has defective for existing contact hole bottom;
Fig. 4 A to Fig. 4 F is the flow process generalized section according to the contact hole formation method that one embodiment of the invention illustrated;
Fig. 5 A to Fig. 5 F is the flow process generalized section according to the contact hole formation method that another embodiment of the present invention illustrated;
Fig. 6 is the starting current gain percentage of element and the graph of a relation of stressor layers thickness.
The main element symbol description
100,400,500: substrate
102,502: metal oxide semiconductor transistor
104,404,504: the gap
106: silicon nitride layer
108,408,508: slot
110,406,412,512: dielectric layer
112: residue
114,414,514: contact window
116,416,516: contact hole
200,300: label
402: conductor element
402a, 502a: grid
402b, 502b: gate dielectric layer
402c, 502c: clearance wall
402d, 502d: source/drain regions
407,507: bottom anti-reflection layer
409,509: patterning photoresist layer
410,510: opening
506: stressor layers
512a: undoped silicon glass layer
512b: phosphorosilicate glass layer
600,602,604: curve
Embodiment
Fig. 4 A to Fig. 4 F is the flow process generalized section according to the contact hole formation method that one embodiment of the invention illustrated.
At first, please refer to Fig. 4 A, a substrate 400 that is formed with at least two conductor elements 402 is provided, and have a gap 404 between two adjacent conductor elements 402.Wherein, conductor element 402 can for example be a metal oxide semiconductor transistor, and metal oxide semiconductor transistor is made up of grid 402a, gate dielectric layer 402b, clearance wall 402c and source/drain regions 402d.
Then, please refer to Fig. 4 B, form dielectric layer 406 in substrate 400 tops, this dielectric layer 406 covers entire substrate 400 and conductor element 402, and inserts in the gap 404.The formation method of dielectric layer 406 for example is a chemical vapour deposition technique, and its material for example is silicon nitride or other suitable dielectric materials.In addition, the thickness of dielectric layer 406 for example is between 100 to 2000 dusts.Preferably, the thickness of dielectric layer 406 for example is between 500 to 1500 dusts.More preferably, the thickness of dielectric layer 406 for example is the 1000 Izod right sides.Because the thickness of dielectric layer 406 is thicker, therefore the dielectric layer 406 in the gap 404 of adjacent two conductor elements 402 is easy to generate slot (seam) 408, can have a strong impact on follow-up technology thus, and then reduces the reliability of element.
Then, please refer to Fig. 4 C, remove the part dielectric layer 406 in the gap 404, in dielectric layer 406, to form opening 410.Above-mentioned, the formation method of opening 410 for example is to form photoresist layer (not illustrating) on dielectric layer 406, then the photoresist layer is carried out a photoetching process, to form a patterning photoresist layer 409, to expose the slot 408 in the dielectric layer 406.Afterwards, be etching mask with this patterning photoresist layer 409, etching part dielectric layer 406 is to form opening 410.Then, remove this patterning photoresist layer 409.
Certainly, in one embodiment, before the photoresist layer forms, can also on dielectric layer 406, form one deck bottom anti-reflection layer 407.Wherein, acting as of this bottom anti-reflection layer 407 provides a smooth surface, is beneficial to follow-up photoetching process.
What deserves to be mentioned is, remove part dielectric layer 406, can enlarge the width of slot 408, and the rete that can avoid follow-up desire to form produces the problem that can't insert fully in the slot 408 to form the step of opening 410.
In another embodiment, the method that enlarges slot 408 width also can for example be to form photoresist layer (not illustrating) on dielectric layer 406, then the photoresist layer is carried out a photoetching process, to form a patterning photoresist layer 409, to expose the slot 408 in the dielectric layer 406.Then, be etching mask with patterning photoresist layer 409, etching part dielectric layer 406 is to exposing substrate 400 surfaces (not illustrating).Afterwards, remove patterning photoresist layer 409 again.In addition, before forming the photoresist layer, also can on dielectric layer 406, form one deck bottom anti-reflection layer 407 certainly.
Afterwards, please refer to Fig. 4 D, on dielectric layer 406, form another layer dielectric layer 412, and dielectric layer 412 fills up opening 410.Wherein, the material of dielectric layer 412 for example is a silica.For example be, phosphorosilicate glass, Pyrex, boron-phosphorosilicate glass or undoped silicon glass or other suitable dielectric materials, and its formation method for example is chemical vapour deposition technique or other suitable methods.
Subsequently, please refer to Fig. 4 E, remove part dielectric layer 412 and part dielectric layer 406 in the gap 404,, form contact window 414 with position in corresponding opening 410 until the surface that exposes part substrate 400.Wherein, the formation method of contact window 414 for example is to carry out an etch process.
Then, please refer to Fig. 4 F, in contact window 414, insert conductor layer, with as contact hole 416.Above-mentioned, the material of conductor layer for example is doped polysilicon layer, aluminium, copper or tungsten, and its formation method for example is chemical vapour deposition technique or other suitable methods.
It should be noted that owing to before forming contact window 414, remove part dielectric layer 406 earlier,, therefore can not cause residue in formed contact window 414 bottoms to enlarge the width of slot 408.In other words, when follow-up formation contact hole 416, can be because of residue is not arranged at contact window 414 bottoms, and produce that resistance improves and problems such as element short circuit.
Fig. 5 A to Fig. 5 F is the flow process generalized section according to the contact hole formation method that another embodiment of the present invention illustrated
At first, please refer to Fig. 5 A, a substrate 500 that forms two metal oxide semiconductor transistors 502 at least is provided, and have a gap 504 between two adjacent metal oxide semiconductor transistors 502.Metal oxide semiconductor transistor 502 is made up of grid 502a, gate dielectric layer 502b, clearance wall 502c and source/drain regions 502d.
Then, please refer to Fig. 5 B, form stressor layers 506 in substrate 500 tops, this stressor layers 506 covers entire substrate 500 and metal oxide semiconductor transistor 502, and inserts in the gap 504.The formation method of stressor layers 506 for example is chemical vapour deposition technique or other suitable methods, and its material for example is silicon nitride or other suitable stress materials.In the present invention, the stress of stressor layers 506 for example is between 1 to 50GPa, and preferably, the stress of stressor layers 506 for example is between 1 to 10GPa.In addition, the thickness of stressor layers 506 for example is between 100 to 2000 dusts.Preferably, the thickness of stressor layers 506 for example is between 500 to 1500 dusts.More preferably, the thickness of stressor layers 506 for example is 1000 dusts.
It should be noted that stressor layers 506 can be to transistorized channel region generation effect, with drive current that improves element and the usefulness that increases element, and the stress value of stressor layers 506 is relevant with its thicknesses of layers.If the thickness of stressor layers 506 is thicker, then its stress value is bigger, and the drive current of element also can be bigger, therefore can improve the usefulness of element.Below, be the relation that stressor layers thickness and element efficiency are described with Fig. 6.Please refer to Fig. 6, it is the starting current gain percentage (Ion gain%) of element and the graph of a relation of stressor layers thickness (dust).In Fig. 6, curve 600,602 and 604 is respectively that the stress value of expression stressor layers is 1.2GPa, 1.5GPa and 1.8GPa, and stressor layers thickness is between 200～1100 dusts.By the curve 600,602 and 604 of Fig. 6 as can be known, under the condition of the stress value of fixed stress layer, stressor layers thickness is thick more, and then the starting current of element gain percentage is big more, and the drive current of its representation element is big more, that is to say that the usefulness of element is good more.Because element efficiency is relevant with stressor layers thickness, therefore in order to improve element efficiency, can form the thicker stressor layers of thickness usually, cause the problem that produces slot 508 in the stressor layers 506 thus easily, and then influence follow-up technology.
Then, please refer to Fig. 5 C, remove part stressor layers 506 in the gap 504 to form opening 510, to enlarge the width of slot 508.Above-mentioned, the formation method of opening 510 for example is to form one deck photoresist layer (not illustrating) on stressor layers 506.Then, carry out a photoetching process, to form patterning photoresist layer 509, to expose the slot 508 in the stressor layers 506.Afterwards, be etching mask with patterning photoresist layer 509 again, etching part stressor layers 506 is to form opening 510.Then, remove patterning photoresist layer 509.
Certainly, in one embodiment, before forming the photoresist layer, can also on stressor layers 506, form one deck bottom anti-reflection layer 507.Wherein, acting as of this bottom anti-reflection layer 507 provides a smooth surface, is beneficial to follow-up photoetching process.
In another embodiment, the method for expansion slot 508 width also can for example be to form one deck photoresist layer (not illustrating) on stressor layers 506.Then, carry out a photoetching process, to form patterning photoresist layer 509, to expose the slot 508 in the stressor layers 506.Then, be etching mask with patterning photoresist layer 509, etching part stressor layers 506 is to exposing substrate 500 surfaces (not illustrating).Afterwards, remove patterning photoresist layer 509.In addition, certainly before the photoresist layer, also can on stressor layers 506, form one deck bottom anti-reflection layer 507.
Afterwards, please refer to Fig. 5 D, on stressor layers 506, form dielectric layer 512, and fill up opening 510.In the present embodiment, dielectric layer 512 for example is in being made up of one deck undoped silicon glass layer 512a and one deck phosphorosilicate glass layer 512b, and for example being the following aumospheric pressure cvd method (SACVD), its formation method on stressor layers 506, forms undoped silicon glass 512a, on undoped silicon glass layer 512a, be that reacting gas source forms phosphorosilicate glass layer 512b then with tetraethoxysilane (TEOS).In addition, the material of dielectric layer 512 can for example be a silica, for example is phosphorosilicate glass, Pyrex or boron-phosphorosilicate glass or undoped silicon glass, and its formation method for example is chemical vapour deposition technique or other methods that is fit to.
Then, please refer to Fig. 5 E, remove part dielectric layer 512 and part stressor layers 506 in the gap 504,, form contact window 514 with position in corresponding opening 510 until exposing part substrate 500 surfaces.Wherein, the formation method of contact window 514 for example is to carry out an etch process.
Subsequently, please refer to Fig. 5 F, in contact window 514, insert conductor layer, to form contact hole 516.The material of conductor layer for example is doped polysilicon layer or tungsten metal, and its formation method for example is a chemical vapour deposition technique.
It should be noted that owing to before forming contact window 514, remove the width that part stressor layers 506 enlarges slot 508 earlier, therefore can avoid formed contact window 514 bottoms to produce residue.So, when follow-up formation contact hole 516, can not produce that resistance improves and problem such as element short circuit, and then influence the reliability of technology.
In sum, contact hole formation method of the present invention has following advantage at least:
1. method of the present invention can be avoided producing slot because of being formed at interelement rete, and has influence on the reliability of technology and the usefulness of element.
2. method of the present invention is the width that utilize to enlarge slot in the stressor layers, avoiding the causing contact window bottom to produce residue in the subsequent technique, and causes formed contact hole resistance to improve or or even problem such as short circuit.
3. method of the present invention can be avoided producing slot in the stress layer, and influence the element reliability forming the thicker stressor layers of thickness with when improving element efficiency.
4. method of the present invention only needs to increase a step in technology, can reach simultaneously to form the thicker stressor layers of thickness improving element efficiency, and avoid producing slot in the stress layer and the purpose that influences the element reliability.
Though the present invention discloses as above with preferred embodiment; right its is not in order to limit the present invention; any those skilled in the art; under the premise without departing from the spirit and scope of the present invention; can do a little change and retouching, so protection scope of the present invention is as the criterion when looking the claims person of defining.
Claims (20)
1. the formation method of a contact hole comprises:
One substrate is provided, has been formed with at least two conductor elements on this substrate, and have a gap between this two conductor element;
Formation one first dielectric layer covers this two conductor element, and inserts in this gap above this substrate, wherein is formed in this first dielectric layer in this gap to have a slot;
Remove this first dielectric layer of part in this gap to form an opening, to enlarge the width of this slot;
On this first dielectric layer, form one second dielectric layer, and fill up this opening;
Remove this second dielectric layer of part and this first dielectric layer of part in this gap,, form a contact window with position in corresponding this opening until exposing this substrate surface of part; And
In this contact window, insert a conductor layer.
2. the formation method of contact hole as claimed in claim 1, wherein the material of this first dielectric layer comprises silicon nitride.
3. the formation method of contact hole as claimed in claim 1, wherein the thickness of this first dielectric layer is between 100 to 2000 dusts.
4. the formation method of contact hole as claimed in claim 1, wherein the thickness of this first dielectric layer is between 500 to 1500 dusts.
5. the formation method of contact hole as claimed in claim 1, wherein the thickness of this first dielectric layer is 1000 dusts.
6. the formation method of contact hole as claimed in claim 1, this first dielectric layer of part that wherein removes in this gap comprises with the method that forms an opening:
On this first dielectric layer, form a photoresist layer;
This photoresist layer is carried out a photoetching process, form the photoresist layer of a patterning, to expose this slot in this first dielectric layer;
Photoresist layer with this patterning is an etching mask, and this first dielectric layer of etching part is to form this opening; And
Remove the photoresist layer of this patterning.
7. the formation method of contact hole as claimed in claim 6 wherein before this photoresist layer forms, also is included in and forms a bottom anti-reflection layer on this first dielectric layer.
8. the formation method of contact hole as claimed in claim 1, wherein the material of this second dielectric layer comprises silica.
9. the formation method of contact hole as claimed in claim 1, wherein the material of this second dielectric layer comprises phosphorosilicate glass, Pyrex, boron-phosphorosilicate glass or undoped silicon glass.
10. the formation method of a contact hole comprises:
One substrate is provided, has been formed with at least two metal oxide semiconductor transistors on this substrate, and have a gap between this two metal oxide semiconductor transistor;
Formation one stressor layers covers this two metal oxide semiconductor transistor, and inserts in this gap above this substrate, wherein is formed in this stressor layers in this gap to have a slot;
Remove this stressor layers of part in this gap to form an opening, to enlarge the width of this slot;
On this stressor layers, form a dielectric layer, and fill up this opening;
Remove this dielectric layer of part and this stressor layers of part in this gap,, form a contact window with position in corresponding this opening until exposing this substrate surface of part; And
In this contact window, insert a conductor layer.
11. the formation method of contact hole as claimed in claim 10, wherein the material of this stressor layers comprises silicon nitride.
12. the formation method of contact hole as claimed in claim 10, wherein the stress of this stressor layers is between 1 to 50GPa.
13. the formation method of contact hole as claimed in claim 10, wherein the stress of this stressor layers is between 1 to 10GPa.
14. the formation method of contact hole as claimed in claim 10, wherein the thickness of this stressor layers is between 100 to 2000 dusts.
15. the formation method of contact hole as claimed in claim 10, wherein the thickness of this stressor layers is between 500 to 1500 dusts.
16. the formation method of contact hole as claimed in claim 10, wherein the thickness of this stressor layers is 1000 dusts.
17. the formation method of contact hole as claimed in claim 10, this stressor layers of part that wherein removes in this gap comprises with the method that forms an opening:
On this stressor layers, form a photoresist layer;
This photoresist layer is carried out a photoetching process, form the photoresist layer of a patterning, to expose this slot in this stressor layers;
Photoresist layer with this patterning is an etching mask, and this stressor layers of etching part is to form this opening; And
Remove the photoresist layer of this patterning.
18. the formation method of contact hole as claimed in claim 17 wherein before this photoresist layer forms, also is included in and forms a bottom anti-reflection layer on this stressor layers.
19. the formation method of contact hole as claimed in claim 10, wherein the material of this dielectric layer comprises silica.
20. the formation method of contact hole as claimed in claim 10, wherein the material of this dielectric layer comprises phosphorosilicate glass, Pyrex, boron-phosphorosilicate glass or undoped silicon glass.
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| CNB2005101316182A CN100423229C (en) | 2005-12-15 | 2005-12-15 | Method for forming contact window |
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| CNB2005101316182A CN100423229C (en) | 2005-12-15 | 2005-12-15 | Method for forming contact window |
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Citations (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US6180515B1 (en) * | 1997-10-20 | 2001-01-30 | United Microelectronics Corp. | Method of fabricating self-align contact window with silicon nitride side wall |
| US20040021160A1 (en) * | 1996-05-28 | 2004-02-05 | Kohei Eguchi | Semiconductor device, a method of manufacturing the semiconductor device and a method of deleting information from the semiconductor device |
| US20050260810A1 (en) * | 2004-05-21 | 2005-11-24 | Taiwan Semiconductor Manufacturing Co., Ltd. | Method for selectively forming strained etch stop layers to improve FET charge carrier mobility |
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- 2005-12-15 CN CNB2005101316182A patent/CN100423229C/en active Active
Patent Citations (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US20040021160A1 (en) * | 1996-05-28 | 2004-02-05 | Kohei Eguchi | Semiconductor device, a method of manufacturing the semiconductor device and a method of deleting information from the semiconductor device |
| US6180515B1 (en) * | 1997-10-20 | 2001-01-30 | United Microelectronics Corp. | Method of fabricating self-align contact window with silicon nitride side wall |
| US20050260810A1 (en) * | 2004-05-21 | 2005-11-24 | Taiwan Semiconductor Manufacturing Co., Ltd. | Method for selectively forming strained etch stop layers to improve FET charge carrier mobility |
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