CN100418206C - Method of manufacturing semiconductor components, and nonvolatile memory - Google Patents
Method of manufacturing semiconductor components, and nonvolatile memory Download PDFInfo
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- CN100418206C CN100418206C CNB2005100921055A CN200510092105A CN100418206C CN 100418206 C CN100418206 C CN 100418206C CN B2005100921055 A CNB2005100921055 A CN B2005100921055A CN 200510092105 A CN200510092105 A CN 200510092105A CN 100418206 C CN100418206 C CN 100418206C
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- 238000004519 manufacturing process Methods 0.000 title claims abstract description 68
- 239000004065 semiconductor Substances 0.000 title claims abstract description 43
- 238000000034 method Methods 0.000 claims abstract description 99
- 239000004020 conductor Substances 0.000 claims abstract description 59
- 239000000758 substrate Substances 0.000 claims abstract description 35
- 238000005530 etching Methods 0.000 claims abstract description 6
- 239000000463 material Substances 0.000 claims description 34
- VYPSYNLAJGMNEJ-UHFFFAOYSA-N Silicium dioxide Chemical compound O=[Si]=O VYPSYNLAJGMNEJ-UHFFFAOYSA-N 0.000 claims description 31
- 238000003860 storage Methods 0.000 claims description 22
- 229910052581 Si3N4 Inorganic materials 0.000 claims description 19
- HQVNEWCFYHHQES-UHFFFAOYSA-N silicon nitride Chemical compound N12[Si]34N5[Si]62N3[Si]51N64 HQVNEWCFYHHQES-UHFFFAOYSA-N 0.000 claims description 19
- 239000002131 composite material Substances 0.000 claims description 18
- 230000008569 process Effects 0.000 claims description 18
- 230000015572 biosynthetic process Effects 0.000 claims description 15
- 229910021420 polycrystalline silicon Inorganic materials 0.000 claims description 14
- 239000000377 silicon dioxide Substances 0.000 claims description 14
- 238000000059 patterning Methods 0.000 claims description 9
- 229920002120 photoresistant polymer Polymers 0.000 claims description 8
- 229920005591 polysilicon Polymers 0.000 claims description 4
- 238000003475 lamination Methods 0.000 abstract 1
- 229910052814 silicon oxide Inorganic materials 0.000 description 3
- 238000005229 chemical vapour deposition Methods 0.000 description 2
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 description 1
- 230000009471 action Effects 0.000 description 1
- 230000008901 benefit Effects 0.000 description 1
- 230000008859 change Effects 0.000 description 1
- 238000010586 diagram Methods 0.000 description 1
- 230000008034 disappearance Effects 0.000 description 1
- 230000006870 function Effects 0.000 description 1
- 239000012774 insulation material Substances 0.000 description 1
- 239000002184 metal Substances 0.000 description 1
- 239000000203 mixture Substances 0.000 description 1
- 230000003647 oxidation Effects 0.000 description 1
- 238000007254 oxidation reaction Methods 0.000 description 1
- 238000001259 photo etching Methods 0.000 description 1
- 238000012163 sequencing technique Methods 0.000 description 1
- 229910052710 silicon Inorganic materials 0.000 description 1
- 239000010703 silicon Substances 0.000 description 1
- 239000011232 storage material Substances 0.000 description 1
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- Non-Volatile Memory (AREA)
Abstract
The method for manufacturing semiconductor component includes following steps: first, providing a substrate; forming multiple first grid lines arranged in parallel, and first virtual grid line perpendicular to the direction of the first grid lines; there is gap between first virtual grid line and first grid line, and there is second gap between adjacent two first grid lines; next, forming second lamination layer and conductor layer on the substrate in sequence; then, carrying out procedure of etching back for the conductor layer to form multiple second component structures of filling in the second gap; finally, removing the conductor layer in the first gap.
Description
Technical field
The present invention relates to a kind of manufacture method of semiconductor element, particularly relate to the manufacture method of a kind of semiconductor element and non-volatility memorizer.
Background technology
Non-volatility memorizer is a kind of memory that can not make the data disappearance that is stored in wherein because of the power supply supply discontinuity, and the non-volatility memorizer of action such as have the sequencing that to carry out repeatedly data at present, read, erase, for example flash memory (flash memory), silicon nitride memory (NROM) or the like have been widely used in various personal computers and electronic equipment.
Figure 1A is the upper viewing view of existing a kind of non-volatility memorizer.Figure 1B is among Figure 1A, by the generalized section of the directions X of I-I ' section gained.Fig. 1 C is among Figure 1A, by the generalized section of the Y direction of II-II ' section gained.Existing flow process of making this kind non-volatility memorizer for example provides substrate 100.In substrate 100, form the multiple-grid polar curve 102 that sidewall has clearance wall 104.Gate line 102 comprises dielectric layer 103, grid 105 and cap layer 107.Then, in substrate 100, form dielectric layer 106 and conductor layer (not illustrating) in regular turn.
Then, remove the segment conductor layer, fill up a plurality of grids 110 in the gap between the gate line 102, and grid 110 constitutes a column of memory cells 113 with gate line 102 with formation, and when forming grid 110, can form conductor clearance wall (not illustrating) at the sidewall of outermost gate line 102.Then, form one deck silicon oxide layer 115 in grid 110 surfaces.Afterwards, in substrate 100, form the photoresist layer (not illustrating) of patterning, and carry out etch process, to remove the conductor clearance wall.Then, in the substrate 100 of column of memory cells 113 2 sides, form source/drain regions 114 again.
Yet, in above-mentioned technology, because be formed with one deck silicon oxide layer at the conductor clearance wall, so when removing the conductor clearance wall with etch process, often the conductor clearance wall can't be removed fully, and stay polysilicon residue (poly residue) 116, and then cause semiconductor element to produce the phenomenon of short circuit.
Summary of the invention
Purpose of the present invention is exactly that a kind of manufacture method of semiconductor element is being provided, and can avoid forming unnecessary kish, and cause the semiconductor element short circuit.
Another object of the present invention provides a kind of manufacture method of non-volatility memorizer, can save the step that removes the residue conductor layer, and avoid forming unnecessary kish, and cause the semiconductor element short circuit.
The present invention proposes a kind of manufacture method of semiconductor element, at first, provides a substrate.Then, a plurality of first grid polar curves that formation is arranged in parallel in substrate and the first dummy gate line vertical with the orientation of first grid polar curve, and have first gap between the first dummy gate line and first grid polar curve, and have second gap between adjacent two first grid polar curves.Then, in substrate, form second composite bed.Afterwards, on second composite bed, form conductor layer.Conductor layer is carried out etch back process, fill up a plurality of second component structures in second gap with formation.Then, remove second component structure in first gap.
Manufacture method according to the described semiconductor element of the embodiment of the invention, the above-mentioned method that removes second component structure in first gap for example is prior to forming patterning photoresist layer in the substrate, exposing first gap, and then carry out anisotropic etching process.
Manufacture method according to the described semiconductor element of the embodiment of the invention, can also when forming the first dummy gate line, form the second dummy gate line parallel, and have third space between the second dummy gate line and first grid polar curve with the orientation of first grid polar curve.
According to the manufacture method of the described semiconductor element of the embodiment of the invention, can also when forming conductor layer, conductor layer be inserted third space.
According to the manufacture method of the described semiconductor element of the embodiment of the invention, can also in the time of the conductor layer in removing first gap, remove the conductor layer in the third space.
According to the manufacture method of the described semiconductor element of the embodiment of the invention, the above-mentioned first grid polar curve and the first dummy gate line respectively comprise first composite bed, grid and cap layer.
According to the manufacture method of the described semiconductor element of the embodiment of the invention, the material of above-mentioned cap layer for example is silica or silicon nitride.
According to the manufacture method of the described semiconductor element of the embodiment of the invention, the first above-mentioned composite bed and second composite bed respectively comprise end dielectric layer, electric charge storage layer and top dielectric layer.
According to the manufacture method of the described semiconductor element of the embodiment of the invention, the above-mentioned end dielectric layer and the material of top dielectric layer for example are silica.
According to the manufacture method of the described semiconductor element of the embodiment of the invention, the material of above-mentioned electric charge storage layer for example is silicon nitride or doped polycrystalline silicon.
According to the manufacture method of the described semiconductor element of the embodiment of the invention, the material of above-mentioned conductor layer for example is a doped polycrystalline silicon.
According to the manufacture method of the described semiconductor element of the embodiment of the invention, can also form clearance wall in the sidewall of the first grid polar curve and the first dummy gate line.
According to the manufacture method of the described semiconductor element of the embodiment of the invention, the material of above-mentioned clearance wall for example is a silicon nitride.
According to the manufacture method of the described semiconductor element of the embodiment of the invention, the first above-mentioned dummy gate line is formed on the not element district in the first grid polar curve and second component structure outside.
The present invention also proposes a kind of manufacture method of non-volatility memorizer, at first, provides a substrate.Then, a plurality of gate lines that formation is arranged in parallel in substrate and the first dummy gate line vertical with the orientation of gate line, and has first gap between the first dummy gate line and gate line, and have second gap between adjacent two gate lines, wherein the gate line and the first dummy gate line comprise one first electric charge storage layer.Then, in substrate, form second composite bed.Next, in substrate, form conductor layer.Afterwards, conductor layer is carried out etch back process, fill up a plurality of second grids in second gap with formation, to form a column of memory cells.Then, remove conductor layer in first gap.Then, in the column of memory cells substrate on two sides, respectively form source/drain regions.
According to the manufacture method of the described non-volatility memorizer of the embodiment of the invention, the above-mentioned method that removes the conductor layer in first gap for example is prior to formation patterning photoresist layer in the substrate, and then carries out anisotropic etching process.
Manufacture method according to the described non-volatility memorizer of the embodiment of the invention, can also when forming the first dummy gate line, form the second dummy gate line parallel, and have third space between the second dummy gate line and outermost first grid polar curve with the orientation of gate line.
According to the manufacture method of the described non-volatility memorizer of the embodiment of the invention, can also when forming conductor layer, conductor layer be inserted third space.
According to the manufacture method of the described non-volatility memorizer of the embodiment of the invention, can also in the time of the conductor layer in removing first gap, remove the conductor layer in the third space.
According to the manufacture method of the described non-volatility memorizer of the embodiment of the invention, above-mentioned gate line comprises a first grid and a cap layer.
According to the manufacture method of the described non-volatility memorizer of the embodiment of the invention, the material of the first above-mentioned electric charge storage layer for example is doped polycrystalline silicon or silicon nitride.
According to the manufacture method of the described non-volatility memorizer of the embodiment of the invention, first above-mentioned electric charge storage layer material up and down comprises silica.
According to the manufacture method of the described non-volatility memorizer of the embodiment of the invention, the material of above-mentioned cap layer for example is silica or silicon nitride.
According to the manufacture method of the described non-volatility memorizer of the embodiment of the invention, the second above-mentioned composite bed comprises end dielectric layer, second electric charge storage layer and top dielectric layer.
According to the manufacture method of the described non-volatility memorizer of the embodiment of the invention, the above-mentioned end dielectric layer and the material of top dielectric layer for example are silica.
According to the manufacture method of the described non-volatility memorizer of the embodiment of the invention, the material of the second above-mentioned electric charge storage layer for example is silicon nitride or doped polycrystalline silicon.
According to the manufacture method of the described non-volatility memorizer of the embodiment of the invention, the material of above-mentioned conductor layer for example is a doped polycrystalline silicon.
According to the manufacture method of the described non-volatility memorizer of the embodiment of the invention, can also form clearance wall in the sidewall of gate line and dummy gate line.
According to the manufacture method of the described non-volatility memorizer of the embodiment of the invention, the material of above-mentioned clearance wall for example is a silicon nitride.
According to the manufacture method of the described non-volatility memorizer of the embodiment of the invention, the first above-mentioned dummy gate line is formed on the not element district in the first grid polar curve and the second grid outside.
The present invention forms the identical dummy gate line of structure simultaneously around first grid polar curve when forming first grid polar curve, utilize the dummy gate line that first grid polar curve is kept apart.Therefore, can after finishing the making of semiconductor element, remove the conductor layer between dummy gate line and the semiconductor element, the residue conductor layer is kept somewhere on the sidewall of dummy gate line, save the step that removes the residue conductor layer forming second component structure.In addition, it is complete to avoid removing the residue conductor layer, and causes the semiconductor element problem of short-circuit.
For above and other objects of the present invention, feature and advantage can be become apparent, embodiment cited below particularly, and conjunction with figs. is described in detail below.
Description of drawings
Figure 1A is the upper viewing view of existing a kind of non-volatility memorizer.
Figure 1B is among Figure 1A, by the generalized section of the directions X of I-I ' section gained.
Fig. 1 C is among Figure 1A, by the generalized section of the Y direction of II-II ' section gained.
Fig. 2 is according to looking schematic diagram on the semiconductor element that the embodiment of the invention illustrated.
Fig. 3 A to Fig. 3 D is among Fig. 2, by the making flow process profile of the directions X of I-I ' section gained.
Fig. 4 A to Fig. 4 D is among Fig. 2, by the making flow process profile of the Y direction of II-II ' section gained.
The simple symbol explanation
100,200: substrate
102,202: gate line
103,106: dielectric layer
104,222: clearance wall
105,110,212,236: grid
107,214: cap layer
108,234: conductor layer
113,238: column of memory cells
114,240: source/drain regions
115: silicon oxide layer
116: the metal residue
204,205: the dummy gate line
206,207,208: the gap
209: patterning photoresist layer
216,226: end dielectric layer
218,228: electric charge storage layer
220,230: the top dielectric layer
224: composite bed
Embodiment
Below be example with the non-volatility memorizer, come semiconductor element manufacture method proposed by the invention is elaborated.
Fig. 2 is the upper viewing view according to the non-volatility memorizer that the embodiment of the invention illustrated.Fig. 3 A to Fig. 3 D is among Fig. 2, by the making flow process profile of the directions X of I-I ' section gained.Fig. 4 A to Fig. 4 D is among Fig. 2, by the making flow process profile of the Y direction of II-II ' section gained.At first, please refer to Fig. 2, Fig. 3 A and Fig. 4 A, a substrate 200 is provided, it for example is a silicon base.Then, in substrate 200, form a plurality of gate lines that are arranged in parallel 202 and the dummy gate line 204 vertical simultaneously with the orientation of gate line 202, and 202 of dummy gate line 204 and gate lines have gap 206, and 202 of adjacent two gate lines have gap 208.Wherein, gate line 202 comprises electric charge storage layer 218, grid 212 and cap layer 214 with dummy gate line 204, its formation method for example is in regular turn after forming charge storage material layer, conductor material layer, insulation material layer in the substrate 200, utilizes photoetching process and etch process that above-mentioned rete patterning is formed again.
The material of electric charge storage layer 218 is doped polycrystalline silicon or silicon nitride for example, and the material of electric charge storage layer about in the of 218 for example is silica.In addition, the rete of electric charge storage layer 218 tops can be described as top dielectric layer 220, and the rete of electric charge storage layer 218 belows can be described as end dielectric layer 216, and the three can be referred to as a composite bed.The material of grid 212 for example is a polysilicon.The material of cap layer 214 for example is silica or silicon nitride.
In addition, can also when forming dummy gate line 204, form the dummy gate line 205 parallel, and dummy gate line 205 and 202 of outermost gate lines has gap 207 with the orientation of gate line 202.Wherein, the composition of dummy gate line 205 is identical with dummy gate line 204, and the two all is positioned at the not element district in gate line 202 outsides, and any function of tool not.In addition, can also on the sidewall of stacked gate line 202, virtual stack gate line 204 and 205, form clearance wall 222.Wherein, the material of clearance wall 222 for example is a silicon nitride.
Then, please refer to Fig. 2, Fig. 3 B and Fig. 4 B, in substrate 200, form composite bed 224.Composite bed 224 for example is made up of end dielectric layer 226, electric charge storage layer 228 and top dielectric layer 230.The material of end dielectric layer 226 for example is a silica, and its formation method for example is a thermal oxidation method.The material of electric charge storage layer 228 for example is a silicon nitride, and its formation method for example is a chemical vapour deposition technique.The material of top dielectric layer 230 for example is a silica, and its formation method for example is a chemical vapour deposition technique.Next, in substrate 200, form conductor layer 234.Wherein, the material of conductor layer 234 for example is a doped polycrystalline silicon.Afterwards, etch-back segment conductor layer 234 up to exposing gate line 202, fills up the grid 236 in gap 208 with formation, and grid 236 is with gate line 202 series connection and form column of memory cells 238.Wherein, the method that removes segment conductor layer 234 for example is the etch-back method.
Then, please refer to Fig. 2, Fig. 3 C and Fig. 4 C, in substrate 200, form patterning photoresist layer 209.Afterwards, please refer to Fig. 2, Fig. 3 D and Fig. 4 D, remove the conductor layer 234 in gap 206 and the gap 207.Wherein, the mode that removes conductor layer 234 for example is to use anisotropic etching process.Then, remove patterning photoresist layer 209.Afterwards, in column of memory cells 238 substrate on two sides 200, form source/drain regions 240.
In sum, the present invention forms the identical dummy gate line 204 and 205 of structure simultaneously around gate line 202 when forming gate line 202.Therefore, can form grid 236 with after gate line 202 is connected into column of memory cells 238, remove dummy gate line 204 and 205 and column of memory cells 238 between conductor layer 234, utilize dummy gate line 204 and 205 that column of memory cells 238 is kept apart, and dummy gate line 204 and 205 is positioned at the not element district in column of memory cells 238 outsides, and residue conductor layer 234 is kept somewhere on the sidewall of dummy gate line 204 and 205, so can after remove the phenomenon generation that the residue conductor layer of avoiding when remaining conductor layer 234 not removing fully 234 causes the semiconductor element short circuit.
Though the present invention discloses as above with preferred embodiment; yet it is not in order to limit the present invention; those skilled in the art can do a little change and retouching without departing from the spirit and scope of the present invention, thus protection scope of the present invention should with accompanying Claim the person of being defined be as the criterion.
Claims (30)
1. the manufacture method of a semiconductor element comprises:
One substrate is provided;
A plurality of first grid polar curves that formation is arranged in parallel in this substrate and the one first dummy gate line vertical with the orientation of those first grid polar curves, and have one first gap between this first dummy gate line and those first grid polar curves, and have second gap between those adjacent first grid polar curves;
In this substrate, form one second composite bed;
On this second composite bed, form a conductor layer;
This conductor layer is carried out an etch back process, fill up a plurality of second component structures in this first gap and those second gaps with formation; And
Remove this second component structure in this first gap.
2. the manufacture method of semiconductor element as claimed in claim 1, the method that wherein removes this second component structure in this first gap comprises:
In this substrate, form a patterning photoresist layer, to expose this first gap; And
Carry out anisotropic etching process.
3. the manufacture method of semiconductor element as claimed in claim 1, also be included in and form the one second dummy gate line parallel when forming this first dummy gate line, and have a third space between this second dummy gate line and outermost this first grid polar curve with the orientation of those first grid polar curves.
4. the manufacture method of semiconductor element as claimed in claim 3 also is included in when forming this conductor layer, and this conductor layer is inserted this third space.
5. the manufacture method of semiconductor element as claimed in claim 4 when also being included in this conductor layer that removes in this first gap, removes this conductor layer in this third space.
6. the manufacture method of semiconductor element as claimed in claim 1, wherein those first grid polar curves and this first dummy gate line respectively comprise one first composite bed, a grid and a cap layer.
7. the manufacture method of semiconductor element as claimed in claim 6, wherein the material of this cap layer comprises silica or silicon nitride.
8. the manufacture method of semiconductor element as claimed in claim 6, wherein this first composite bed and this second composite bed respectively comprise an end dielectric layer, an electric charge storage layer and a top dielectric layer.
9. the manufacture method of semiconductor element as claimed in claim 8, wherein should end dielectric layer and the material of this top dielectric layer comprise silica.
10. the manufacture method of semiconductor element as claimed in claim 8, wherein the material of this electric charge storage layer comprises silicon nitride or doped polycrystalline silicon.
11. the manufacture method of semiconductor element as claimed in claim 1, wherein the material of this conductor layer comprises the polysilicon through mixing.
12. the manufacture method of semiconductor element as claimed in claim 1, the sidewall that also is included in those first grid polar curves and this dummy gate line forms a clearance wall respectively.
13. the manufacture method of semiconductor element as claimed in claim 12, wherein the material of this clearance wall comprises silicon nitride.
14. the manufacture method of semiconductor element as claimed in claim 1, wherein this first dummy gate line is formed on the not element district in those first grid polar curves and those second component structures outside.
15. the manufacture method of a non-volatility memorizer comprises:
One substrate is provided;
A plurality of first grid polar curves that formation is arranged in parallel in this substrate and the one first dummy gate line vertical with the orientation of those first grid polar curves, and has one first gap between this first dummy gate line and those first grid polar curves, and have second gap between those adjacent gate lines, wherein those first grid polar curves and this first dummy gate line comprise one first electric charge storage layer;
In this substrate, form one second composite bed;
In this substrate, form a conductor layer;
This conductor layer is carried out an etch back process, fill up a plurality of second grids in those second gaps with formation, to form a column of memory cells;
Remove this conductor layer in this first gap; And
In this substrate of these column of memory cells both sides, form an one source pole district and a drain region respectively.
16. the manufacture method of non-volatility memorizer as claimed in claim 15, the method that wherein removes this conductor layer in this first gap comprises:
In this substrate, form a patterning photoresist layer; And
Carry out anisotropic etching process.
17. the manufacture method of non-volatility memorizer as claimed in claim 15, also be included in and form the one second dummy gate line parallel when forming this first dummy gate line, and have a third space between this second dummy gate line and outermost this first grid polar curve with the orientation of those first grid polar curves.
18. the manufacture method of non-volatility memorizer as claimed in claim 17 also is included in when forming this conductor layer, and this conductor layer is inserted this third space.
19. the manufacture method of non-volatility memorizer as claimed in claim 18 when also being included in this conductor layer that removes in this first gap, removes this conductor layer in this third space.
20. the manufacture method of non-volatility memorizer as claimed in claim 15, wherein those first grid polar curves comprise a first grid and a cap layer.
21. the manufacture method of non-volatility memorizer as claimed in claim 20, wherein the material of this cap layer comprises silica or silicon nitride.
22. the manufacture method of non-volatility memorizer as claimed in claim 15, wherein the material of this first electric charge storage layer comprises doped polycrystalline silicon or silicon nitride.
23. the manufacture method of non-volatility memorizer as claimed in claim 15, wherein this above first electric charge storage layer and below material comprise silica.
24. the manufacture method of non-volatility memorizer as claimed in claim 15, wherein this second composite bed comprises an end dielectric layer, one second electric charge storage layer and a top dielectric layer.
25. the manufacture method of non-volatility memorizer as claimed in claim 24, wherein should end dielectric layer and the material of this top dielectric layer comprise silica.
26. the manufacture method of non-volatility memorizer as claimed in claim 24, wherein the material of this second electric charge storage layer comprises silicon nitride or doped polycrystalline silicon.
27. the manufacture method of non-volatility memorizer as claimed in claim 15, wherein the material of this conductor layer comprises polysilicon.
28. the manufacture method of non-volatility memorizer as claimed in claim 15, the sidewall that also is included in those first grid polar curves and this first dummy gate line forms a clearance wall respectively.
29. the manufacture method of non-volatility memorizer as claimed in claim 28, wherein the material of this clearance wall comprises silicon nitride.
30. the manufacture method of non-volatility memorizer as claimed in claim 15, wherein this first dummy gate line is formed on the not element district in those first grid polar curves and those second grids outside.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CNB2005100921055A CN100418206C (en) | 2005-08-19 | 2005-08-19 | Method of manufacturing semiconductor components, and nonvolatile memory |
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| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CNB2005100921055A CN100418206C (en) | 2005-08-19 | 2005-08-19 | Method of manufacturing semiconductor components, and nonvolatile memory |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| CN1917174A CN1917174A (en) | 2007-02-21 |
| CN100418206C true CN100418206C (en) | 2008-09-10 |
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| CNB2005100921055A Expired - Fee Related CN100418206C (en) | 2005-08-19 | 2005-08-19 | Method of manufacturing semiconductor components, and nonvolatile memory |
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Citations (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN1322014A (en) * | 2000-04-29 | 2001-11-14 | 双汉科技股份有限公司 | Optical diode complementary metal oxide semiconductor image sensor production method |
| US6878988B1 (en) * | 2004-06-02 | 2005-04-12 | United Microelectronics Corp. | Non-volatile memory with induced bit lines |
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2005
- 2005-08-19 CN CNB2005100921055A patent/CN100418206C/en not_active Expired - Fee Related
Patent Citations (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN1322014A (en) * | 2000-04-29 | 2001-11-14 | 双汉科技股份有限公司 | Optical diode complementary metal oxide semiconductor image sensor production method |
| US6878988B1 (en) * | 2004-06-02 | 2005-04-12 | United Microelectronics Corp. | Non-volatile memory with induced bit lines |
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| CN1917174A (en) | 2007-02-21 |
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