CN100411065C - Process for manufacturing chip resisor in low value of resistance and structure - Google Patents
Process for manufacturing chip resisor in low value of resistance and structure Download PDFInfo
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- CN100411065C CN100411065C CNB2004100707786A CN200410070778A CN100411065C CN 100411065 C CN100411065 C CN 100411065C CN B2004100707786 A CNB2004100707786 A CN B2004100707786A CN 200410070778 A CN200410070778 A CN 200410070778A CN 100411065 C CN100411065 C CN 100411065C
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Abstract
The present invention relates to a chip resistor having a low resistance value, which comprises a baseplate, a pair of conductive layers, a resistance layer, a resistance regulating and trimming slot and insulated protective layers formed on the resistance layer and the resistance regulating and trimming slot. When the chip resistor having low resistance values is produced, at least a pair of conductive layers forms on the prepared base plate, which belongs to the technical field of contrary media. After the baseplate is together burnt with the conductive layers, the surface of the baseplate between the conductive layers form a resistive layer which is burnt, the resistive layer forms the resistance regulating and trimming slot, and a resistance regulating and trimming slot also forms on the resistive layer in order to trim the impedance of the resistor. Finally, the insulated protective layers are formed on the resistance layer and the resistance regulating and trimming slot. The present invention overcomes the defects of the prior art and obtains the effects of reducing laser trimming power, reducing the impedance variation of products due to heating, quantifying effective using process, reducing trimmed impedance precision variance, etc.
Description
Technical field
The present invention relates to a kind of processing procedure and structure of chip resister, particularly about the processing procedure and the structure thereof of low resistance chip resister.
Background technology
Chip resister has been widely used in various electronic equipments, instrument and equipment and the communication apparatus.Chip resister roughly is divided into thick film chip resistor and two kinds of kenels of thin film chip resistor, wherein the electrode of this thick film chip resistor and resistive layer are made by the printing (Printing) or the technology of burning till (Baking), and the electrode of thin film chip resistor and resistive layer are made by the technology of sputter (Sputtering).
In typical chip resister processing procedure (consulting shown in Figure 1), it mainly is that lower surface at a substrate 1 is provided with a pair of backside conductive layer 21,22, and forms a pair of surface conductance layer 31,32 at the upper surface of this substrate 1.After finishing this backside conductive layer 21,22 and surface conductance layer 31,32, burnt till, printing forms a resistive layer 4 on the surface of this substrate 1 again, and gives and burning till.The two ends of this resistive layer 4 are connected in surface conductance layer 31,32.After finishing the burning till of this resistive layer 4, promptly on this resistive layer 4, republish and form one first insulating protective layer 61, and burn till.For example in No. the 436820th, TaiWan, China patent of invention Announcement Number, in disclosed chip resistor and the manufacture method thereof, promptly belong to this type of technology.
And in aforesaid chip resister manufacturing technology; in order to reach the purpose of the resistance value of adjusting this chip resister; so can be after finishing this resistive layer 4 and first insulating protective layer 61, the mode of repairing with laser forms a resistance adjustment trim slots 5 at the suitable section place of this resistive layer 4 and first insulating protective layer 61.At last, on this first insulating protective layer 61, republish formation one second insulating protective layer 62 again.After finishing above-mentioned processing procedure, form a conductive layer 71, a nickel dam 72, a tin layer 73 again at the both ends of this chip resister.
For example in No. the 394962nd, TaiWan, China patent of invention Announcement Number in the technology of disclosed chip resister; promptly be to carry out the resistance adjustment of chip resister in the mode of laser finishing; it is to form on substrate after resistive layer and first insulating protective layer, with this resistive layer of laser beam irradiation and first insulating protective layer with formation resistance adjustment trim slots in this resistive layer and first insulating protective layer.
Again for example in No. the 344826th, TaiWan, China patent of invention Announcement Number in the technology of disclosed chip resister; also be on substrate, to form after the resistive layer and first insulating protective layer, in this resistive layer and first insulating protective layer, form banded fine setting ditch in this resistive layer and first insulating protective layer.
Yet; when adopting above-mentioned technique known; because the resistance adjustment trim slots is after finishing this resistive layer and first insulating protective layer; mode with the laser light boundling forms a resistance adjustment trim slots at the suitable section place of this resistive layer and first insulating protective layer again; so need select laser light for use, the restriction in the time of so will causing industry to utilize with higher-wattage.Moreover the resistance adjustment trim slots of this formation is in this resistive layer and first insulating protective layer, so it is easier to have the problem of finishing back impedance precision variation, and when this chip resister during in practical application, and the situation of the generation impedance variation that is easier to be heated.These disappearances are all demanded urgently improving for the utilization of industry and the chip resister quality that produces out.
Summary of the invention
The technical problem that institute of the present invention desire solves is: the structure that a kind of low resistance chip resister is provided, resistance adjustment trim slots structure by the resistive layer that improves this chip resister, impedance precision after the finishing is improved and controls, and make this chip resister when practical application, more not having is heated produces the disappearance of impedance variation.
Another technical problem that the present invention will solve is: the processing procedure that a kind of low resistance chip resister is provided, it is by the improvement of processing procedure, make that in the chip-resistance production process of reality the laser light boundling that optional usefulness has a lower-wattage forms the resistance adjustment trim slots of this chip resister.
For this reason, the present invention proposes a kind of processing procedure of low resistance chip resister, comprises the following steps:
(a) preparation one substrate;
(b) form the pair of conductive layer at least one surface of this substrate;
(c) this substrate is burnt till together with conductive layer;
(d) surface of this substrate forms a resistive layer between this conductive layer, and gives and burning till;
(e) be formed with a resistance adjustment trim slots at this resistive layer, to repair the impedance of this resistor;
(f) on this resistive layer and resistance adjustment trim slots, form an insulating protective layer.
In addition, the present invention also proposes a kind of structure of low resistance chip resister, comprising:
One substrate;
The pair of conductive layer is formed at least one surface of this substrate;
One resistive layer is formed on the surface of this substrate and conductive layer, and the two ends of this resistive layer are electrically connected on this conductive layer respectively;
One resistance adjustment trim slots is formed on the section of this resistive layer position between these two conductive layers;
One insulating protective layer is covered on this resistive layer and the resistance adjustment trim slots.
Characteristics of the present invention and advantage are as follows:
Low resistance chip resister of the present invention include a substrate, pair of conductive layer, a resistive layer, a resistance adjustment trim slots and be formed on this resistive layer and the resistance adjustment trim slots on insulating protective layer.The present invention is when making this low resistance chip resister; at first on the substrate of a preparation, form the pair of conductive layer at least; after this substrate is burnt till together with conductive layer; surface at this substrate forms a resistive layer between this conductive layer; and give and burning till; and be formed with a resistance adjustment trim slots at this resistive layer, to repair the impedance of this resistor, on this resistive layer and resistance adjustment trim slots, form an insulating protective layer at last.
The present invention contrasts the effect of prior art: compared to prior art, the present invention has effectively overcome and must select for use the laser light with higher-wattage to form the problem of resistance adjustment trim slots in the conventional art, and via architecture advances of the present invention, impedance precision after the feasible finishing is improved and controls, and can make chip resister when practical application, effectively having overcome is heated produces the disappearance of impedance variation.And when adopting processing procedure of the present invention, can reach effective processing procedure that mass production is used.
Description of drawings
Fig. 1 is the structure cutaway view that shows the chip resister of finishing according to the processing procedure of prior art;
Fig. 2 is the structure cutaway view that shows the chip resister of finishing according to processing procedure of the present invention;
Fig. 3 shows making flow chart of the present invention;
Fig. 4 A to Fig. 4 F is the structural representation that shows the present invention's each processing procedure when making chip resister.
The drawing reference numeral explanation:
1 substrate, 71 conductive layers
21,22 backside conductive layers, 72 nickel dams
31,32 surface conductance layers, 73 tin layer
4 resistive layers, 8 insulating protective layers
5 resistance adjustment trim slots, 91 conductive layers
61 first insulating protective layers, 92 nickel dams
62 second insulating protective layers, 93 tin layers
Embodiment
Concrete grammar of the present invention and control flow will be further described by following embodiment and accompanying drawing.
Consult shown in Figure 2ly, it is the structure cutaway view that shows the chip resister of finishing according to processing procedure of the present invention.Its chip resister that shows that processing procedure of the present invention is finished mainly includes a substrate 1, and it is made that this substrate 1 can be alumina material.Back up at this substrate 1 forms a pair of backside conductive layer 21,22, and forms a pair of surface conductance layer 31,32 in the upper surface printing of this substrate 1.
This substrate 1 the surface and between surface conductance layer 31,32 printing be formed with a resistive layer 4, the two ends of resistive layer 4 are electrically connected on this surface conductance layer 31,32.And be formed with a resistance adjustment trim slots 5 at the suitable section position place of this resistive layer 4.Be formed with an insulating protective layer 8 on this resistive layer 4 again, this insulating protective layer 8 for example can be materials such as glass or resin.At last, sequentially form a conductive layer 91, a nickel dam 92, an and tin layer 93 at the both ends of this chip resister.
Consult shown in Figure 3ly, it is to show making flow chart of the present invention, and Fig. 4 A to Fig. 4 F shows the structural representation of the present invention when making chip resister.Now cooperate Fig. 3 and Fig. 4 A to Fig. 4 F simultaneously, processing procedure of the present invention and structure are further described.
Processing procedure of the present invention is at first in step 101, prepare an aluminum oxide substrate 1, again in step 102, back of the body surface printing at this substrate 1 forms a pair of backside conductive layer 21,22 (shown in Fig. 4 A), afterwards in step 103, form a pair of surface conductance layer 31,32 (shown in Fig. 4 B) in the upper surface printing of this substrate 1.
After finishing this backside conductive layer 21,22 and surface conductance layer 31,32, in step 104, burnt till, in step 105, printing forms a resistive layer 4 on the surface of this substrate 1, and gives and burn till (shown in Fig. 4 C) again.
Finish after this resistive layer 4, promptly in step 106, carry out the step of laser finishing, in this resistive layer 4, to form a resistance adjustment trim slots 5 (shown in Fig. 4 D).The formation of this resistance adjustment trim slots 5 can the laser light boundling mode in this resistive layer 4, form the trough body structure of the one about 15-45 μ of width m, so can adjust the resistance value of this resistive layer 4 according to this.
Finish after this resistance adjustment trim slots 5, then in step 107, form an insulating protective layer 8 in the surface of this resistive layer 4, and burnt till (shown in Fig. 4 E).
After finishing above-mentioned processing procedure, in step 108, sequentially form a conductive layer 91, a nickel dam 92 at the both ends of this chip resister, reach a tin layer 93 (shown in Fig. 4 F) again, so promptly finish the making of this chip resister.
By the above-mentioned embodiment of the invention as can be known, seeing through processing procedure of the present invention improves, but really can reach and reduce laser finishing power, reduce effective processing procedure that product uses by thermogenetic impedance variation mass production, reduce effect such as finishing back impedance precision variation, so the present invention has the value on the industry.
Though the present invention discloses with specific embodiment; but it is not in order to limit the present invention; any those skilled in the art; the displacement of the equivalent assemblies of under the prerequisite that does not break away from design of the present invention and scope, having done; or, all should still belong to the category that this patent is contained according to equivalent variations and modification that scope of patent protection of the present invention is done.
Claims (9)
1. the processing procedure of a low resistance chip resister comprises the following steps:
(a) preparation one substrate;
(b) form the pair of conductive layer at least one surface of this substrate;
(c) this substrate is burnt till together with conductive layer;
(d) surface of this substrate forms a resistive layer between this conductive layer, and gives and burning till;
(e) be formed with a resistance adjustment trim slots at this resistive layer, to repair the impedance of this resistor;
(f) on this resistive layer and resistance adjustment trim slots, form an insulating protective layer.
2. the processing procedure of low resistance chip resister as claimed in claim 1 wherein is included in the step that the back of the body surface printing of this substrate forms a pair of backside conductive layer and forms a pair of surface conductance layer in the upper surface printing of this substrate in the step (b).
3. the processing procedure of low resistance chip resister as claimed in claim 1, wherein the conductive layer in the step (b) is the surface that is formed on this substrate with mode of printing, is burnt till and forms.
4. the processing procedure of low resistance chip resister as claimed in claim 1, wherein the resistive layer in the step (d) is the surface that is formed on this substrate with mode of printing, is burnt till and forms.
5. the processing procedure of low resistance chip resister as claimed in claim 1, wherein step (f) afterwards, the both ends that more are included in this chip resister sequentially form a conductive layer, a nickel dam, and the step of a tin layer.
6. the structure of a low resistance chip resister is characterized in that, comprising:
One substrate;
At least one pair of conductive layer is formed at least one surface of this substrate;
One resistive layer is formed on the surface of this substrate and conductive layer, and the two ends of this resistive layer are electrically connected on this conductive layer respectively;
One resistance adjustment trim slots is formed on the section of this resistive layer position between these two conductive layers;
One insulating protective layer is covered on this resistive layer and the resistance adjustment trim slots.
7. the structure of low resistance chip resister as claimed in claim 6 is characterized in that, this conductive layer includes:
The a pair of backside conductive layer that is formed on the back of the body surface of this substrate;
The a pair of surface conductance layer that is formed on the upper surface of this substrate.
8. the structure of low resistance chip resister as claimed in claim 6 is characterized in that, this substrate is an aluminum oxide substrate.
9. the structure of low resistance chip resister as claimed in claim 6 is characterized in that, the both ends of this chip resister more comprise a conductive layer that order forms, a nickel dam, an and tin layer.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CNB2004100707786A CN100411065C (en) | 2004-07-26 | 2004-07-26 | Process for manufacturing chip resisor in low value of resistance and structure |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CNB2004100707786A CN100411065C (en) | 2004-07-26 | 2004-07-26 | Process for manufacturing chip resisor in low value of resistance and structure |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| CN1728292A CN1728292A (en) | 2006-02-01 |
| CN100411065C true CN100411065C (en) | 2008-08-13 |
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| CNB2004100707786A Expired - Fee Related CN100411065C (en) | 2004-07-26 | 2004-07-26 | Process for manufacturing chip resisor in low value of resistance and structure |
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Citations (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US5379017A (en) * | 1993-10-25 | 1995-01-03 | Rohm Co., Ltd. | Square chip resistor |
| CN1106952A (en) * | 1993-11-11 | 1995-08-16 | 松下电器产业株式会社 | Chip resistor and method for producing the same |
| US5815065A (en) * | 1996-01-10 | 1998-09-29 | Rohm Co. Ltd. | Chip resistor device and method of making the same |
| CN1441444A (en) * | 2002-02-25 | 2003-09-10 | 兴亚株式会社 | Chip resistor |
-
2004
- 2004-07-26 CN CNB2004100707786A patent/CN100411065C/en not_active Expired - Fee Related
Patent Citations (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US5379017A (en) * | 1993-10-25 | 1995-01-03 | Rohm Co., Ltd. | Square chip resistor |
| CN1106952A (en) * | 1993-11-11 | 1995-08-16 | 松下电器产业株式会社 | Chip resistor and method for producing the same |
| US5815065A (en) * | 1996-01-10 | 1998-09-29 | Rohm Co. Ltd. | Chip resistor device and method of making the same |
| CN1441444A (en) * | 2002-02-25 | 2003-09-10 | 兴亚株式会社 | Chip resistor |
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| Publication number | Publication date |
|---|---|
| CN1728292A (en) | 2006-02-01 |
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Assignee: Dongguan Huake Electronic Co., Ltd. Assignor: Prosperity Dielectrics Co., Ltd. Contract fulfillment period: 2008.10.9 to 2024.7.25 contract change Contract record no.: 2009990000021 Denomination of invention: Process for manufacturing chip resisor in low value of resistance and structure Granted publication date: 20080813 License type: Exclusive license Record date: 2009.1.7 |
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| LIC | Patent licence contract for exploitation submitted for record |
Free format text: EXCLUSIVE LICENSE; TIME LIMIT OF IMPLEMENTING CONTACT: 2008.10.9 TO 2024.7.25; CHANGE OF CONTRACT Name of requester: DONGGUAN HUAKE ELECTRONICS CO., LTD. Effective date: 20090107 |
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| CF01 | Termination of patent right due to non-payment of annual fee | ||
| CF01 | Termination of patent right due to non-payment of annual fee |
Granted publication date: 20080813 Termination date: 20160726 |