CN100399175C - Active component array substrate - Google Patents
Active component array substrate Download PDFInfo
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- CN100399175C CN100399175C CNB2005101375091A CN200510137509A CN100399175C CN 100399175 C CN100399175 C CN 100399175C CN B2005101375091 A CNB2005101375091 A CN B2005101375091A CN 200510137509 A CN200510137509 A CN 200510137509A CN 100399175 C CN100399175 C CN 100399175C
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Abstract
The present invention relates to an active component array baseplate which comprises a baseplate, a pixel array and a peripheral circuit, wherein the baseplate is provided with a display area and a peripheral circuit area which is adjacent to the display area; the pixel array is arranged in the display area on the baseplate; the peripheral circuit is arranged in the peripheral circuit area on the baseplate and comprises a first signal wire, a second signal wire, a first by-pass line, a second by-pass line, a plurality of chip bonding pads, a first quasi connection pad and a plurality of second quasi connection pads; the by-pass line and the first signal wire transfer identical signals; the second by-pass line and the second signal wire transfer identical signals; the chip bonding pads are arranged between the by-pass lines and the pixel array and are electrically connected with the pixel array; the first quasi connection pad is electrically connected with the first by-pass line; each of the second quasi connection pads is electrically connected with the second by-pass line.
Description
Technical field
The present invention relates to a kind of active assembly array substrate (active matrix substrate), particularly relate to a kind of active assembly array substrate with bypass line (bypass line).
Background technology
In order to cooperate modern life pattern, it is frivolous that the volume of video signal or device for image day by day is tending towards.Though traditional cathode-ray tube (CRT) (cathode ray tube, CRT) display still has its advantage, but because the structure in its internal electron chamber, make the volume of cathode-ray tube display seem huge and take up space, and in the cathode-ray tube display image output, can produce radiant rays, cause problems such as eye injury.Therefore, (flat paneldisplay, FPD), LCD for example becomes the main flow of display product gradually to cooperate the flat-type display that photoelectric technology and semiconductor fabrication developed.
Figure 1A shows the structural representation of a known display panels.Figure 1B shows the partial enlarged drawing of the thin-film transistor array base-plate of region S 10 among Figure 1A.Fig. 1 C shows the partial enlarged drawing of the thin-film transistor array base-plate of region S 20 among Figure 1A.Please earlier with reference to Figure 1A, known display panels 100 comprises a thin-film transistor array base-plate 110, a colored optical filtering substrates 120, a printed circuit board (PCB) 130, a plurality of scanning drive chip 140 and a plurality of data driving chip 150.Wherein, colored optical filtering substrates 120 is disposed at the top of thin-film transistor array base-plate 110.Dispose a plurality of data driving chip 150 on the printed circuit board (PCB) 130, and the data driving chip 150 on the printed circuit board (PCB) 130 is suitable for being connected with the data line DL (being shown among Fig. 1 C) of thin-film transistor array base-plate 110.In addition, scanning drive chip 140 is suitable for being connected with the sweep trace SL of thin-film transistor array base-plate 110 (be shown in Figure 1B with Fig. 1 C in), and printed circuit board (PCB) 130 and the pel array 20 of scanning drive chip 140 in order to drive thin film transistors array base palte 110.
Please continue with reference to Figure 1B and Fig. 1 C, above-mentioned thin-film transistor array base-plate 110 comprises a glass substrate 10, a pel array 20, a peripheral circuit 30, many short- circuit lines 40,50 and many bonding lines 60.Wherein, pel array 20, peripheral circuit 30, short- circuit line 40,50 and bonding line 60 all are disposed on the glass substrate 10.
In order to drive the pel array 20 on the display panels 100, must around display panels 100, make relevant circuit and chip, make voltage and signal can put on the scanning linear SL and the data line DL of pel array 20.Printed circuit board (PCB) 130 as shown in Figure 1A, the data line DL that it is electrically connected thin-film transistor array base-plate 110 makes data signals can put on data line DL.In addition, several scanning drive chips (gate driver IC) 140 are bonded on the glass substrate 10 of thin-film transistor array base-plate 110, it is to cover crystal glass encapsulation technology (chip on glass, COG) be engaged on the glass substrate 10 of thin-film transistor array base-plate 110, and be electrically connected with the sweep trace SL of thin-film transistor array base-plate 110, make the scanning signal can put on sweep trace SL.
It should be noted that, because after colored optical filtering substrates 120 is disposed at thin-film transistor array base-plate 110, the area that thin-film transistor array base-plate 110 left sides expose is comparatively long and narrow, in order on thin-film transistor array base-plate 110, to dispose scanning drive chip 140, therefore scanning drive chip 140 is engaged in (shown as Figure 1A) on the thin-film transistor array base-plate 110 by signal line 32 in the mode of polyphone (cascade).Yet when transmitting associated voltage to each scanning drive chip 140, the impedance meeting of signal line 32 causes voltage attenuation, and this situation is even more serious in large-scale display panels.For avoiding being passed to the voltage difference on the scanning drive chip 140, each scanning drive chip 140 side is equipped with several bypass line 35,36 (shown as Figure 1A), just so can make the voltage that applies on each scanning drive chip 140 identical.Detailed description relevant for this patent can be the patent specification of TW 589598 and US 6844629 with reference to the patent No..
Please continue with reference to Figure 1B, in the manufacture process of active assembly array substrate 110, unavoidable because foreign matter drops or other manufacture process factor and cause the situation of short circuit.For example, in manufacture process, if the some A that has foreign matter to drop in Figure 1B to be indicated is during with some B, the position bonding line 60 meetings at an A and some B place respectively with bypass line 35,36 short circuits that are positioned at below these two bonding lines 60.Yet these two bonding lines 60 are short circuits via short-circuit line 40, therefore can cause to be positioned at an A and two bypass line, 35,36 short circuits of putting below, B place.When array test (array test), test probe can be pressed on the chip joint pad 33 (chip joint pad 33 that is connected with sweep trace SL) of intending joint sheet 34 and part, but because bypass line 35,36 is not electrically connected with plan joint sheet 34 or the chip joint pad 33 that probe was pressed onto (chip joint pad 33 that is connected with sweep trace SL), so the voltage signal of bypass line 35,36 can't record, also just can't measure between each bypass line 35,36 whether short circuit.Generally speaking, after finishing liquid crystal cells manufacture process (cell processes), the short- circuit line 40,50 on the thin-film transistor array base-plate 110 still can be left.When liquid crystal cells test (cell test), because tester table for example adopts winding packaging body (the tape automatic bonding that fits automatically, TAB) probe is tested, probe can directly be pressed on the chip joint pad 33 that is connected with sweep trace SL, and whether therefore can't measure bypass line 35,36 has situation of short circuit.When 120 pairs of groups of 35,36 thin-film transistor array base-plates that are short-circuited of this bypass line 110 and colored optical filtering substrates and injection liquid crystal, and then carry out joint technology (bonging process) afterwards, printed circuit board (PCB) 130 can be engaged on the thin-film transistor array base-plate 110 with scanning drive chip 140, and so display panels 100 is just roughly finished.Yet this display panels 100 because 35,36 of bypass line are short-circuited, makes display quality bad when carrying out module testing.In other words, thin-film transistor array base-plate 110 just can be detected 35,36 of bypass line and is short-circuited when module testing.In addition,, make problematic thin-film transistor array base-plate 110 proceed follow-up technology, not only waste production capacity, also increased the manufacturing cost of display panels 100 owing to fail when array test, to detect in real time the short circuit phenomenon of 35,36 of bypass line.
Summary of the invention
In view of this, purpose of the present invention is exactly that a kind of active assembly array substrate that detects the bypass line short circuit can be in array test the time is being provided.
Based on above-mentioned purpose and other purpose, the present invention proposes a kind of active assembly array substrate, and this active assembly array substrate comprises a substrate, a pel array and a peripheral circuit.Substrate has a viewing area and one and the periphery circuit region of viewing area adjacency.In the viewing area of pixel array configuration on substrate.Peripheral circuit is disposed in the periphery circuit region on the substrate, and this peripheral circuit comprises that one first signal line, one second signal line, one first bypass line, one second bypass line, a plurality of chip joint pad, one first intend joint sheet and a plurality of second and intend joint sheet.Wherein first bypass line is transmitted an identical signal with first signal line, and second bypass line is transmitted an identical signal with second signal line.Chip joint pad is disposed between bypass line and the pel array, and is electrically connected with pel array.First intends joint sheet is electrically connected on first bypass line.Each second plan joint sheet is electrically connected with second bypass line.Many short-circuit lines are disposed at all this first bypass line and this second bypass line outside with this short-circuit line electrical isolation.Many bonding lines connect described short-circuit line and described chip joint pad, and wherein said bonding line is crossed over this first bypass line and this second bypass line.
Described according to one embodiment of the invention, active assembly array substrate also comprises many connecting lines that are disposed in the periphery circuit region, and wherein the first plan joint sheet and each second plan joint sheet are connected to first bypass line and second bypass line by these connecting lines.
According to the described active assembly array substrate of one embodiment of the invention, wherein the first plan joint sheet and each second plan joint sheet are positioned at the outside of these chip joint pads.
According to the described active assembly array substrate of one embodiment of the invention, wherein first bypass line is continuous circuit.
According to the described active assembly array substrate of one embodiment of the invention, wherein second bypass line is discontinuous circuit.
According to the described active assembly array substrate of one embodiment of the invention, also comprise another plan joint sheet, be electrically connected on first bypass line.
Described according to one embodiment of the invention, active assembly array substrate also comprises many short-circuit lines (shorting bar) and many bonding lines.Short-circuit line is disposed at first bypass line and second bypass line outside.Bonding line connects short-circuit line and chip joint pad, and wherein these cross-over connection linear systems are crossed over first bypass line and second bypass line.In addition, first bypass line and second bypass line and short-circuit line electrical isolation.
According to the described active assembly array substrate of one embodiment of the invention, wherein pel array comprises many data lines, multi-strip scanning line, a plurality of driving component and a plurality of pixel electrode.Wherein, sweep trace is electrically connected with chip joint pad respectively.Driving component is electrically connected with corresponding scanning line and data line respectively.Pixel electrode is electrically connected with corresponding active components respectively.In addition, these driving components comprise thin film transistor (TFT).
In sum, in active assembly array substrate of the present invention, first bypass line and second bypass line are connected to corresponding first by connecting line wherein respectively and intend joint sheet and intend joint sheet with second, so the short-circuit conditions between first bypass line and second bypass line can detect in array test.
For above and other objects of the present invention, feature and advantage can be become apparent, preferred embodiment cited below particularly, and be described with reference to the accompanying drawings as follows.
Description of drawings
Figure 1A shows the structural representation of a known display panels.
Figure 1B shows the partial enlarged drawing of the thin-film transistor array base-plate of region S 10 among Figure 1A.
Fig. 1 C shows the partial enlarged drawing of the thin-film transistor array base-plate of region S 20 among Figure 1A.
Fig. 2 A shows the structural representation of the active assembly array substrate of preferred embodiment of the present invention.
Fig. 2 B shows the partial enlarged drawing of region S 30 among Fig. 2 A.
Fig. 2 C shows the partial enlarged drawing of region S 40 among Fig. 2 A.
Fig. 2 D shows the structural representation of the display panels that the active assembly array substrate that utilizes Fig. 2 A assembles.
Fig. 2 E shows the first plan joint sheet and second and intends the synoptic diagram that joint sheet is electrically connected with first bypass line and second bypass line respectively.
The reference numeral explanation
100: display panels
110: thin-film transistor array base-plate
120: colored optical filtering substrates
130: printed circuit board (PCB)
140: scanning drive chip
150: data driving chip
10: glass substrate
20: pel array
22: thin film transistor (TFT)
24: pixel electrode
30: peripheral circuit
32: signal line
33: chip joint pad
34: intend joint sheet
35,36: bypass line
40,50: short-circuit line
60: bonding line
A, B: point
DL: data line
SL: sweep trace
S10, S20: zone
200: active assembly array substrate
210: substrate
212: the viewing area
214: periphery circuit region
220: pel array
222: sweep trace
224: data line
226: driving component
228: pixel electrode
230: peripheral circuit
232a: first signal line
232b: second signal line
234a: first bypass line
234b: second bypass line
236: chip joint pad
238a: first intends joint sheet
238b: second intends joint sheet
240,240a, 240b: connecting line
250,250a, 250b: short-circuit line
260: bonding line
300: display panels
310: colored optical filtering substrates
320: scanning drive chip
330: printed circuit board (PCB)
350: data driving chip
C, D: point
S30, S40, S50: zone
Embodiment
Fig. 2 A shows the structural representation of the active assembly array substrate of preferred embodiment of the present invention.Fig. 2 B shows the partial enlarged drawing of region S 30 among Fig. 2 A.Fig. 2 C shows the partial enlarged drawing of region S 40 among Fig. 2 A.Please earlier with reference to Fig. 2 A and Fig. 2 B, active assembly array substrate 200 comprises a substrate 210, a pel array 220 and a peripheral circuit 230.Wherein, substrate 210 for example is the substrate of glass substrate, quartz base plate or other suitable material, and it has a viewing area 212 and a periphery circuit region 214, and this periphery circuit region 214 is adjacent with viewing area 212.Pel array 220 is disposed in the viewing area 212 on the substrate 210.230 of peripheral circuits are disposed in the periphery circuit region 214 on the substrate 210, and comprise that one first signal line 232a, one second signal line 232b, one first bypass line 234a, one second bypass line 234b, a plurality of chip joint pad 236, at least one first intend joint sheet 238a and a plurality of second and intend joint sheet 238b.Wherein, the first bypass line 234a transmits an identical signal with the first signal line 232a, and the second bypass line 234b transmits an identical signal with the second signal line 232b.Chip joint pad 236 is disposed between bypass line 234a, 234b and the pel array 220 and with pel array 220 and is electrically connected.First intends joint sheet 238a and second intends the outside that joint sheet 238b is positioned at chip joint pad 236.First intends joint sheet 238a is electrically connected on the first bypass line 234a.Each second plan joint sheet 238b is electrically connected with the second bypass line 234b.
In the active assembly array substrate 200 of present embodiment, be manufactured with peripheral circuit 230 in the periphery circuit region 214 of substrate 210, be suitable for and the circuit board and the chip join that drive pel array 220.More specifically, substrate 210 is suitable for engaging a printed circuit board (PCB) (not shown), makes this printed circuit board (PCB) be electrically connected on peripheral circuit 230 in the periphery circuit region 214, to be used to drive the data line 224 of pel array 220.Substrate 210 also is suitable for engaging upward a plurality of scanning drive chip (not shown), these scanning drive chips are to cover crystal glass encapsulation technology (chip on glass, COG) be engaged in the region S 50 of substrate 210 and be electrically connected on peripheral circuit 230 in the periphery circuit region 214, to be used for driving the sweep trace 222 of pel array 220.
Except above-mentioned each member, active assembly array substrate 200 also comprises many connecting lines 240, and these connecting lines 240 are disposed in the periphery circuit region 214, and the material of connecting line 240 for example is indium tin oxide, metal or other suitable conductive material.In the present embodiment, therefore annexation is denoted as connecting line 240a and connecting line 240b respectively with connecting line 240 for convenience of explanation.Wherein, first intends joint sheet 238a is connected to the first bypass line 234a by connecting line 240a, and second intends joint sheet 238b is connected to the second bypass line 234b by connecting line 240b.Fig. 2 E shows the first plan joint sheet 238a and second and intends the synoptic diagram that joint sheet 238b is electrically connected with the first bypass line 234a and the second bypass line 234b respectively.Shown in Fig. 2 E, the first bypass line 234a is continuous circuit, and the second bypass line 234b is discontinuous circuit.In Fig. 2 B, connecting line 240a is electrically connected on first and intends between joint sheet 238a and the first bypass line 234a, and this connecting line 240a crosses over the also second bypass line 234b electrical isolation therewith of the second bypass line 234b.Connecting line 240b is electrically connected on second and intends between the joint sheet 238b and the second bypass line 234b.In addition, active assembly array substrate 200 also comprises many short-circuit lines (shorting bar) 250 and many bonding lines 260.Short-circuit line 250 is disposed at the outside of the first bypass line 234a and the second bypass line 234b, and the first bypass line 234a and the second bypass line 234b all with short-circuit line 250 electrical isolations.Bonding line 260 connects short-circuit line 250 and chip joint pad 236, and bonding line 260 is crossed over the first bypass line 234a and the second bypass line 234b.Annexation for convenience of explanation, short-circuit line 250 will be denoted as short-circuit line 250a and short-circuit line 250b respectively.In Fig. 2 B, short-circuit line 250a connects the bonding line 260 of all odd number bars, and short-circuit line 250b then is electrically connected the bonding line 260 of all even number bars.
Be noted that, intend joint sheet 238a though Fig. 2 B of present embodiment only illustrates one first, active assembly array substrate 200 also comprises another first plan joint sheet 238a, and promptly first quantity of intending joint sheet 238a can be greater than two.Remaining first plan joint sheet 238a lays respectively in the region S 50 of each chip join, and all is electrically connected on the first bypass line 234a.
Please refer to Fig. 2 C, the pel array 220 of active assembly array substrate 200 comprises multi-strip scanning line 222, many data lines 224, a plurality of driving component 226 and a plurality of pixel electrodes 228.Wherein, sweep trace 222 can be aluminium alloy distribution or the formed distribution of other suitable conductor material, 224 of data lines can be chromium metal wiring, aluminium alloy distribution or the formed distribution of other suitable conductor material, and sweep trace 222 is electrically connected with chip joint pad 236 respectively.Driving component 226 for example is a thin film transistor (TFT) or other has the switch module (tri-polar switching device) of three terminals, and is electrically connected with corresponding scanning line 222 and data line 224 respectively.Pixel electrode 228 is electrically connected with corresponding active components 226 respectively, this pixel electrode 228 for example is a transparency electrode (transmissive electrode), reflecting electrode (reflective electrode) or translucent half reflection electrode (transflective electrode), and the material of pixel electrode 228 can be indium tin oxide, indium-zinc oxide (indium zinc oxide, IZO), metal or other transparent or opaque conductive material.
If the some C among Fig. 2 B and the bonding line 260 first bypass line 234a, the second bypass line 234b out of the ordinary and its below at some D place are short-circuited, because short-circuit line 250a connects this two bonding lines 260, therefore put between the first bypass line 234a below C and the some D and the second bypass line 234b and can be short-circuited.But the first bypass line 234a, the second bypass line 234b are connected to the corresponding first plan joint sheet 238a, second by connecting line 240a, 240b respectively and intend joint sheet 238b, and when array test, the probe of tester table can be pressed in first and intend on the chip joint pad 236 (chip joint pad that is connected with sweep trace 222) that joint sheet 238a, second intends joint sheet 238b and part, so the voltage signal of the first bypass line 234a and the second bypass line 234b all can be measured.If cooperate to adjust the array test parameters of machine, just can detect between the first bypass line 234a and the second bypass line 234b whether short circuit.For example, suppose under normal circumstances that the voltage that puts on the first bypass line 234a is V
1, the voltage that puts on the second bypass line 234b is V
2If the first plan joint sheet 238a, second that the array test board measures intends the voltage signal V of joint sheet 238b
1', V
2' and V
1, V
2Difference is little, then can judge the first bypass line 234a and the second bypass line 234b electrical isolation.On the contrary, if the first plan joint sheet 238a, second that measures intends the voltage signal V of joint sheet 23 8b
1', V
2' and V
1, V
2Widely different, then the first bypass line 234a may be short-circuited with the second bypass line 234b.
Above-mentioned active assembly array substrate 200 can be applicable to assemble display panels.Fig. 2 D shows the structural representation of the display panels that the active assembly array substrate that utilizes Fig. 2 A assembles.Please refer to Fig. 2 D, display panels 300 comprises a colored optical filtering substrates 310, a plurality of scanning drive chip 320, a printed circuit board (PCB) 330, a plurality of data driving chip 350 and an above-mentioned active assembly array substrate 200.Wherein, colored optical filtering substrates 310 is disposed at active assembly array substrate 200 tops, and a liquid crystal layer (not shown) is disposed between colored optical filtering substrates 310 and the active assembly array substrate 200.Dispose a plurality of data driving chip 350 on the printed circuit board (PCB) 330, and this printed circuit board (PCB) 330 is connected in active assembly array substrate 200, can be in order to drive the data line 224 of pel array 220.Scanning drive chip 320 is engaged on the active assembly array substrate 200, can be in order to drive the sweep trace 222 of pel array 220.
Because active assembly array substrate 200 can detect to have or not between the first bypass line 234a, the second bypass line 234b when array test and be short-circuited, when between the first bypass line 234a that detects active assembly array substrate 200 and the second bypass line 234b situation about being short-circuited being arranged, then this active assembly array substrate 200 can be repaired or subsequent manufacturing processes is just no longer proceeded in advance, and production capacity therefore can avoid waste.Change speech, can effectively reduce the production cost of display panels 300.
In sum, active assembly array substrate of the present invention has following advantage at least:
One, in active assembly array substrate of the present invention, first bypass line and second bypass line are connected to corresponding first by connecting line wherein respectively and intend the joint sheet and the second plan joint sheet, whether probe can be pressed in first and intends joint sheet, second and intend on joint sheet and the chip joint pad that is connected scanning linear during array test, just can detect between first bypass line and second bypass line after the cooperation adjustment array test parameters of machine to be short-circuited.
Two, for whether short circuit between first bypass line that detects active assembly array substrate of the present invention and second bypass line, only need to change the array test parameters of machine and get final product, need not increase extras.
Three, owing to the short-circuit conditions between first bypass line and second bypass line can detect when array test, active assembly array substrate defective can repair in advance or subsequent manufacturing processes is just no longer proceeded, and the production capacity that therefore can avoid waste also can reduce the production cost of display panels.
Though the present invention discloses as above with preferred embodiment; right its is not in order to limit the present invention; those skilled in the art can do some changes and retouching under the premise without departing from the spirit and scope of the present invention, so protection scope of the present invention is as the criterion with claim of the present invention.
Claims (8)
1. active assembly array substrate comprises:
One substrate has a viewing area and one and the periphery circuit region of this viewing area adjacency;
One pel array is disposed in this viewing area on this substrate; And
One peripheral circuit is disposed in the periphery circuit region on this substrate, and this peripheral circuit comprises:
One first signal line and one second signal line;
One first bypass line and one second bypass line, wherein this first bypass line is transmitted an identical signal with this first signal line, and this second bypass line is transmitted an identical signal with this second signal line;
A plurality of chip joint pads are disposed between described bypass line and this pel array, and are electrically connected with this pel array;
One first intends joint sheet, is electrically connected on this first bypass line; A plurality of second intends joint sheet, and wherein each second plan joint sheet is electrically connected with this second bypass line;
Many short-circuit lines are disposed at all this first bypass line and this second bypass line outside with this short-circuit line electrical isolation; And
Many bonding lines connect described short-circuit line and described chip joint pad, and wherein said bonding line is crossed over this first bypass line and this second bypass line.
2. active assembly array substrate as claimed in claim 1, also comprise many connecting lines that are disposed in this periphery circuit region, wherein this first plan joint sheet and each second plan joint sheet are connected to this first bypass line and this second bypass line by described connecting line respectively.
3. active assembly array substrate as claimed in claim 1, wherein this first plan joint sheet and each second plan joint sheet are positioned at the outside of described chip joint pad.
4. active assembly array substrate as claimed in claim 1, wherein this first bypass line is continuous circuit.
5. active assembly array substrate as claimed in claim 1, wherein this second bypass line is discontinuous circuit.
6. active assembly array substrate as claimed in claim 1 also comprises another first plan joint sheet, is electrically connected on this first bypass line.
7. active assembly array substrate as claimed in claim 1, wherein this pel array comprises:
Many data lines;
Multi-strip scanning line, wherein said sweep trace are electrically connected with described chip joint pad respectively;
A plurality of driving components are electrically connected with corresponding scanning line and data line respectively; And
A plurality of pixel electrodes are electrically connected with corresponding active components respectively.
8. active assembly array substrate as claimed in claim 7, wherein said driving component comprises thin film transistor (TFT).
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CNB2005101375091A CN100399175C (en) | 2005-12-29 | 2005-12-29 | Active component array substrate |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CNB2005101375091A CN100399175C (en) | 2005-12-29 | 2005-12-29 | Active component array substrate |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| CN1794073A CN1794073A (en) | 2006-06-28 |
| CN100399175C true CN100399175C (en) | 2008-07-02 |
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| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| CNB2005101375091A Active CN100399175C (en) | 2005-12-29 | 2005-12-29 | Active component array substrate |
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| CN (1) | CN100399175C (en) |
Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| TWI733500B (en) * | 2020-03-30 | 2021-07-11 | 大陸商友達光電(蘇州)有限公司 | Display apparatus |
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|---|---|---|---|---|
| CN1391132A (en) * | 2001-06-13 | 2003-01-15 | 精工爱普生株式会社 | Substrate devices, its test methods, photoelectric devices and manufacturing methods thereof |
| US6741309B2 (en) * | 2000-07-27 | 2004-05-25 | Samsung Electronics Co., Ltd. | Liquid crystal display |
| CN1503040A (en) * | 2002-11-19 | 2004-06-09 | 三星电子株式会社 | Liquid crystal display and testing method thereof |
| CN1527104A (en) * | 2003-03-07 | 2004-09-08 | ������������ʽ���� | Image display device equipment with checking terminal |
| US6844629B2 (en) * | 2002-09-10 | 2005-01-18 | Au Optronics Corp. | Display panel with bypassing lines |
| CN1621925A (en) * | 2003-11-26 | 2005-06-01 | 三星电子株式会社 | Semiconductor chip, tape carrier package having the same mounted thereon, and liquid crystal display apparatus including the tape carrier package |
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2005
- 2005-12-29 CN CNB2005101375091A patent/CN100399175C/en active Active
Patent Citations (6)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US6741309B2 (en) * | 2000-07-27 | 2004-05-25 | Samsung Electronics Co., Ltd. | Liquid crystal display |
| CN1391132A (en) * | 2001-06-13 | 2003-01-15 | 精工爱普生株式会社 | Substrate devices, its test methods, photoelectric devices and manufacturing methods thereof |
| US6844629B2 (en) * | 2002-09-10 | 2005-01-18 | Au Optronics Corp. | Display panel with bypassing lines |
| CN1503040A (en) * | 2002-11-19 | 2004-06-09 | 三星电子株式会社 | Liquid crystal display and testing method thereof |
| CN1527104A (en) * | 2003-03-07 | 2004-09-08 | ������������ʽ���� | Image display device equipment with checking terminal |
| CN1621925A (en) * | 2003-11-26 | 2005-06-01 | 三星电子株式会社 | Semiconductor chip, tape carrier package having the same mounted thereon, and liquid crystal display apparatus including the tape carrier package |
Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| TWI733500B (en) * | 2020-03-30 | 2021-07-11 | 大陸商友達光電(蘇州)有限公司 | Display apparatus |
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| Publication number | Publication date |
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| CN1794073A (en) | 2006-06-28 |
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