CN100397744C - Power supply device with shunt control - Google Patents

Abstract

The invention relates to a power supply device with shunt control. The power supply device uses the bus end as the shunt control interface. The power circuit supplies an output voltage and an output current to the output terminal, and generates a current sensing signal according to the output current. The feedback control circuit controls the power circuit according to the output of the power supply device. The shunt control unit generates and outputs a bus signal to the bus terminal according to the current sensing signal, and generates and outputs a reference signal to the feedback control circuit according to the reference voltage, the bus signal and the output current, so as to adjust the output of the power supply device through the feedback control circuit. The bus communication circuit monitors the power supply device.

Description

Power supply with shunt control

technical field

The invention relates to a power supply device, in particular to a power supply device which can be connected in parallel with another power supply device to provide a shunt mechanism and a shunt method thereof.

Background technique

Power supplies are commonly used in electronic devices and other products to provide adjustable power. Please refer to FIG. 1 , which is a block diagram illustrating a conventional power supply. As shown in FIG. 1 , it includes an unregulated DC input voltage V _IN , a power circuit 10 , an adjustable DC output voltage V _O and a voltage divider with resistors _RA and _RB . The power supply further includes a feedback control circuit coupled to the power circuit 10 . The feedback control circuit includes a control unit 20, an error amplifier 30 and a reference voltage _VR . The DC output voltage V _O is connected to the feedback control circuit via a voltage divider. Resistors _RA and _RB are connected in series between the adjustable DC output voltage V _O and ground. The voltage dividing point between resistors _RA and _RB is connected to the negative terminal of error amplifier 30 . The reference voltage _VR is connected to the positive terminal of the error amplifier 30 . The output terminal of the error amplifier 30 generates a feedback signal and outputs it to the control unit 20 . The feedback control loop modulates the feedback signal to control the output of the power supply. Regardless of the load condition and the input voltage change, the modulation of the feedback signal can make the power supply output a stable DC voltage. The power circuit 10 is not only a linear power supply, but also a circuit structure of a switching power supply.

Serial buses such as I ² C bus or SM bus (smart bus) are widely used in personal computers and their peripheral circuits for hardware monitoring. Figure 2 illustrates that various devices can talk to each other over the bus. For example, the central processing unit can monitor the voltage of the battery and the on/off of the power supply through the bus, and even read parameters such as the voltage, current, fan speed, and operating temperature of the power supply. Figure 3 shows the waveform timing diagram of the bus in Figure 2. In the bus, the data terminal DATA is used to carry data, and the clock terminal CLK is used to indicate the validity of the data (logic level V _DH or V _DL ) of the data terminal DATA. Because all devices connected to the bus can arbitrate the bus, the data terminal DATA and the clock terminal CLK are usually at a high level, and when the data terminal DATA and the clock terminal CLK are at a low level, it indicates that the bus is transmitting data.

The problem with conventional power supplies is that they cannot be connected in parallel. For high current output and/or fault tolerance systems, parallel power supplies are required. In order to improve reliability, the power supplies connected in parallel must have a shunt function to share the output current and reduce the operating temperature of the power supplies.

Contents of the invention

The purpose of the present invention is to provide a power supply device, which utilizes the existing bus communication interface as the current distribution control interface, so that multiple power supply devices can be connected in parallel arbitrarily to have an automatic current distribution function. The present invention does not require additional connection terminals.

Another object of the present invention is to provide a power supply splitting method, so that multiple power supply devices connected in parallel can automatically adjust their respective outputs to have an automatic splitting function.

The invention proposes a power supply device with shunt control. The power supply device includes an input terminal, an output terminal, a bus terminal, a power circuit, a feedback control circuit, a control unit, a shunt control unit and a bus communication circuit. The bus end is coupled to a bus for providing a bus communication interface and a split control interface. The power circuit receives the input voltage of the input terminal to supply an output voltage and an output current to the output terminal, wherein the power circuit further generates a current sensing signal according to the output current. The feedback control circuit is coupled to the output end and used for generating a feedback signal according to the output of the power supply device and a reference signal. The control unit is coupled to the power circuit and the feedback control circuit, and controls the power circuit according to the feedback signal to stably adjust the output of the power supply device. The shunt control unit is coupled to the bus terminal and the feedback control circuit, and is used for outputting a bus signal according to the current sensing signal and a reference voltage, and outputting a reference signal according to the reference voltage, the bus signal and the current sensing signal, so as to Adjust the feedback signal. The bus communication circuit is coupled to the bus terminal, the shunt control unit and the control unit, and is used to monitor the power supply device according to the data transmitted by the bus terminal.

According to the power supply device described in a preferred embodiment of the present invention, the feedback control circuit includes a voltage divider and an amplifier. The voltage divider is coupled to the output end, and is used for dividing the output voltage to generate a corresponding sensing voltage. The negative terminal of the amplifier is coupled to the voltage divider to receive the sensing voltage, the positive terminal is coupled to the shunt control unit to receive the reference signal, and the output terminal is coupled to the control unit to output the feedback signal.

According to the power supply device described in a preferred embodiment of the present invention, the above-mentioned shunt control unit includes a pull-up voltage unit, a pull-up resistor, a current generation unit, an input unit, an output unit, and an adjustment unit. The pull-up voltage unit generates a pull-up voltage according to the reference voltage. The pull-up resistor is coupled between the pull-up voltage unit and the bus terminal. The current generating unit generates a corresponding first current signal and a second current signal according to the current sensing signal. The input unit is coupled to the bus end and is used for generating a third current signal according to the boosted voltage and the bus signal. The output unit is coupled to the bus terminal for generating a bus signal according to the second current signal and the boosted voltage. The adjusting unit is coupled to the input unit and the current generating unit for generating and adjusting the reference signal according to the reference voltage, the third current signal and the first current signal.

The invention proposes a power supply device with shunt control. The power supply device includes an input terminal, an output terminal, a bus terminal, a power circuit, a feedback control circuit, a control unit and a shunt control unit. The bus end is coupled to the bus to provide a bus communication interface and a split control interface. The power circuit receives the input voltage of the input terminal and supplies output voltage and output current to the output terminal. The feedback control circuit is coupled to the output end and used for generating a feedback signal according to the output of the power supply device. The control unit is coupled to the power circuit and the feedback control circuit, and controls the power circuit according to the feedback signal. The shunt control unit is coupled to the power circuit, the bus terminal and the feedback control circuit, and is used to output a bus signal at the bus terminal according to the output current of the power supply device, and output according to the reference voltage, the bus signal and the output current of the power supply device Reference signal to adjust the feedback signal.

Because the present invention adopts the parallel structure of multiple power supply devices, the existing bus communication interface of each power supply device is used as the shunt control interface to share the total output current of each power supply device, so each power supply device can reduce its own output current, thereby reducing its operating temperature. At the same time, because each power supply device can automatically detect its own output state at any time, and output the bus signal through the bus terminal according to its output state, each power supply device can automatically adjust its power supply according to the bus signal at its bus terminal. output current to achieve the purpose of automatic shunting.

In order to make the above and other objects, features and advantages of the present invention more comprehensible, preferred embodiments will be described in detail below together with the accompanying drawings.

Description of drawings

FIG. 1 is a block diagram illustrating a conventional power supply.

FIG. 2 is a block diagram illustrating that various devices are connected to each other through a serial bus in a conventional computer architecture.

Figure 3 shows the waveform timing diagram of the bus in Figure 2.

FIG. 4 illustrates a preferred embodiment of a power supply with shunt function according to the present invention.

FIG. 5 illustrates a preferred embodiment of a distribution control unit according to the present invention.

FIG. 6 illustrates a preferred embodiment of a current generating unit according to the present invention.

FIG. 7 illustrates a preferred embodiment of the input unit according to the present invention.

FIG. 8 illustrates a preferred embodiment of the level detection unit in the input unit according to the present invention.

FIG. 9 illustrates a preferred embodiment of an adjustment unit according to the present invention.

Fig. 10 illustrates a preferred embodiment of an output unit according to the present invention.

FIG. 11 illustrates a preferred embodiment of parallel connection of multiple power supplies to share output current according to the present invention.

10: Power circuit 20: Control unit

30: Error amplifier 40: Bus communication circuit

50: Shunt control unit 52: Buffer

53: Transistor 55: Operational amplifier

100: Current generating unit 150: Input unit

155: offset voltage 160: buffer amplifier

161: Current source 200: Adjustment unit

207: Unity gain buffer 250: Output unit

257: Unity gain amplifier CLK: Clock terminal of the bus

DATA: Data terminal of the bus D _I : Input data

D ₀ : output data FB: feedback signal

I ₁ : first current signal I ₂ : second current signal

I _M : Internal current of the current generating unit I _O : Output current

I _X : The third current signal R ₁ : Pull-up resistor

R ₂ : Input resistance R ₃ : Adjustment resistance

R ₄ : Output resistance R _A , R _B : Resistance

V _B : Bus signal V _SP : Bias signal

V _DH , V _DL : logic level _VI : current sensing signal

V _IN : input voltage V _M : pull-up voltage

V _O : Output voltage V _REF : Reference signal

V _R1 : Reference voltage Z _O : Output impedance

Detailed ways

To facilitate the description of the spirit of the present invention, a common computer architecture will be used as an example below to illustrate how to realize the shunt function of parallel power supply devices (such as power supplies) without changing the original circuit architecture. In the following embodiments, the existing serial bus interface (serial bus interface) in the computer system will be used as the control interface of the shunt, without additional interface or pins. Those skilled in the art can also use a parallel bus interface (parallel bus interface) as the control interface for shunting according to the spirit of the present invention.

Please refer to FIG. 4 , which illustrates a preferred embodiment of a power supply with shunt function according to the present invention. The power supply includes an input terminal having an input voltage V _IN , an output terminal having an output voltage V _O , and a bus terminal coupled to a bus of an external personal computer or a central processing unit. The bus terminal includes a data terminal DATA and a clock terminal CLK for providing a bus communication interface and a distribution control interface. The power circuit 10 receives an input voltage V _IN at an input terminal, and supplies an output voltage V _O and an output current I _O to the output terminal. In this embodiment, the power circuit 10 further generates a corresponding current sensing signal V _I according to the output current I _O.

The feedback control circuit includes an amplifier (such as an error amplifier) 30 and a voltage divider. The voltage divider is composed of resistors _RA and _RB connected in series, and is coupled to the output terminal for dividing the output voltage V _O to generate a corresponding sensing voltage. The amplifier 30 generates the feedback signal FB according to the sense voltage (provided by the voltage divider) received by its negative terminal and the reference signal V _REF (provided by the shunt control unit 50 ) received by its positive terminal. The control unit 20 is coupled to the amplifier 30 and the power circuit 10 for controlling the power circuit 10 according to the feedback signal FB, so as to stabilize and adjust the output of the power supply. The reference signal V _REF is generated based on a reference voltage V _R1 .

The shunt control unit 50 is coupled to the bus terminal (herein, for example, coupled to the data terminal DATA of the bus terminal) and the feedback control circuit, and is used for controlling the output current I _O of the output terminal (herein, for example, based on the current sensing signal V _I ) and the feedback control circuit. The reference voltage V _R1 generates and outputs a bus signal to the data terminal DATA. The shunt control unit 50 further generates and outputs a reference signal V _REF according to the reference voltage V _R1 , the bus signal of the data terminal DATA and the current sensing signal V _I , so as to adjust the feedback signal FB. Therefore, the split control unit 50 can adjust the output of the power supply via the feedback control circuit and the power circuit 10 .

The bus communication circuit 40 is used for supervising and/or controlling the power supply. Through the communication of the bus interface, the bus communication circuit 40 manages the input and output data. In this embodiment, the bus communication circuit 40 is further connected to the control unit 20 so as to acquire and control the data (such as voltage, current and operating temperature, etc.) of the power supply. When an external personal computer or central processing unit transmits data to the power supply via the data terminal DATA of the bus, the shunt control unit 50 transmits the input data _D1 of the data terminal DATA to the bus communication circuit 40, so the bus communication circuit 40 is The input data D _I can be captured in accordance with the timing of the clock terminal CLK of the bus. When the power supply intends to transmit data to an external personal computer or central processing unit via the data terminal DATA of the bus, the bus communication circuit 40 transmits the output data D _O to the shunt control unit in accordance with the timing of the clock terminal CLK of the bus 50.

Please refer to FIG. 5 , which illustrates a preferred embodiment of the diversion control unit 50 according to the present invention. The shunt control unit 50 includes a pull-up voltage unit, a pull-up resistor R ₁ , a current generating unit 100 , an input unit 150 , an output unit 250 and an adjustment unit 200 . The pull-up voltage unit generates a pull-up voltage V _M according to the reference voltage V _R1 , and includes an operational amplifier 55 , resistors 56 and 57 . The reference voltage V _R1 is connected to the positive terminal of the operational amplifier 55 , so the output terminal of the operational amplifier 55 generates a corresponding pull-up voltage V _M . The pull-up resistor _R1 is coupled between the pull-up voltage unit and the bus terminal (for example, the data terminal DATA here) for providing a high-impedance pull-up voltage to the bus terminal. The current generating unit 100 generates a first current signal I ₁ and a second current signal I ₂ according to the current sensing signal V _I . The input unit 150 is coupled to the bus terminal for generating a third current signal I _X according to the bus signal V _B and the pull-up voltage V _M . The output unit 250 is coupled to the bus terminal for generating the bus signal V _B according to the second current signal I ₂ and the pull-up voltage V _M and outputting it to the bus terminal. The adjusting unit 200 is coupled to the input unit 150 and the current generating unit 100 for generating and adjusting the reference signal V _REF according to the reference voltage V _R1 , the third current signal I _X and the first current signal I ₁ . When an external personal computer or central processing unit transmits data to the power supply via the data terminal DATA of the bus, the distribution control unit 50 outputs the input data D _I of the data terminal DATA to the bus communication circuit 40 via the buffer 52 . When the power supply intends to transmit data to an external personal computer or central processing unit via the data terminal DATA of the bus, the bus communication circuit 40 transmits the output data D _O to the transistor 53 in accordance with the timing of the clock terminal CLK of the bus. gate. Since the potential of the data terminal DATA has been set to a high level by the pull-up resistor _R1 (representing a logic 0 here), when the output data D _O to be output is a logic 1, only the transistor 53 needs to be turned on. The potential of the data terminal DATA is set to a low level (representing a logic 1 here).

Please refer to FIG. 6 , which illustrates a preferred embodiment of the current generating unit 100 according to the present invention. As shown in FIG. 6 , the first current signal I ₁ and the second current signal I ₂ are generated by mirroring the current I _M formed by the transistors 103 , 104 and 105 . The current I _M is generated through the operational amplifier 101 , the transistor 102 and the resistor 106 according to the current sensing signal V _I . Therefore, the first current signal I ₁ and the second current signal I ₂ correspond to the current sensing signal V _I and the output current I _O .

Please refer to FIG. 7 , which illustrates a preferred embodiment of the input unit 150 according to the present invention. As shown in FIG. 7 , the input unit 150 includes an input resistor R ₂ , a level detection unit 170 and a buffer amplifier 160 . The level detection unit 170 is coupled to the bus terminal (for example, the data terminal DATA here) for detecting the bus signal V _B of the bus terminal. The buffer amplifier 160 has a first output terminal O/P and a second output terminal, and a positive terminal of the buffer amplifier 160 has an offset voltage (offset voltage) 155 . Its positive terminal is coupled to the level detection unit 170 for receiving its bias signal V _SP . The negative terminal of the buffer amplifier 160 is coupled to its first output terminal O/P, and the first output terminal O/P is further coupled to the pull-up voltage V _M through the input resistor R ₂ . The second output terminal of the buffer amplifier 160 generates a third current signal I _X according to the pull-up voltage V _M , the bias signal V _SP , the offset voltage 155 and the input resistor R ₂ .

Current source 161 and transistors 162 , 163 , 164 , 165 form a differential input stage of buffer amplifier 160 . The transistor 167 is connected between the transistor 165 and the first output terminal O/P of the buffer amplifier 160 . The transistors 168 and 169 form a current mirror, wherein the transistor 168 is connected to the transistor 167 for receiving the current from the first output terminal O/P of the buffer amplifier 160 . The transistor 169 outputs the third current signal I _X , so the third current signal I _X is proportional to the current of the first output terminal O/P of the buffer amplifier 160 . The third current signal I _X can be expressed as Equation (1).

$I_x={\mathrm{<figure-callout\; id="1"\; label="K"\; filenames="C20051005693800161.png,C20051005693800171.png"\; state="\{\{state\}\}">K</figure-callout>}}_1\&times;\frac{V_m-(V_{\mathrm{SP}}+V_{\mathrm{offset}})}{R_2}$ Equation (1)

Wherein, k ₁ is the current mirror ratio of the transistors 168 and 169 , and V _offset is the voltage value of the offset voltage 155 .

Please refer to FIG. 8 , which illustrates a preferred embodiment of the level detection unit 170 in the input unit 150 according to the present invention. As shown in FIG. 8 , the level detection unit 170 includes a multiple sampling unit and a buffer-high amplifier. The multiple sampling unit samples the bus signal V _B at the bus terminal (here, for example, the data terminal DATA) and generates a plurality of sampling signals. The sampling high buffer amplifier is coupled to the multi-sampling unit, and the bias signal V _SP is determined according to the higher voltage among the sampling signals. The multiple sampling unit includes switches 301 and 302 controlled by sampling pulse signals _φ1 and _φ2 . The sampled signals sampled by the switches 301 and 302 are respectively stored in the capacitors 305 and 306 .

The sampling pulse signal generator alternately generates the first sampling pulse signal φ ₁ and the second sampling pulse signal φ ₂ . The sampling pulse signal generator includes a flip-flop 331 , AND gates 332 and 333 . The pulse signal φ is connected to the input of the flip-flop 331 and the inputs of the AND gates 332, 333, and is generated periodically. The output of flip-flop 331 is connected to AND gates 332 , 333 . The AND gates 332 and 333 respectively output the first sampling pulse signal φ ₁ and the second sampling pulse signal φ ₂ . The positive terminal of the comparator 321 is connected to the bus terminal, the negative terminal is provided by the threshold voltage V _TH , the output terminal generates a stop signal, and is coupled to the input terminals of the AND gates 332 , 333 via the debounce unit 330 . The debounce unit 330 is used to filter noise. When the signal at the bus terminal is lower than the threshold voltage V _TH , the stop signal disables the first sampling pulse signal φ ₁ and the second sampling pulse signal φ ₂ .

The high buffer amplifier includes amplifiers 310 and 312 . The positive terminals of amplifiers 310 and 312 are connected to capacitors 305 and 306, respectively. The output of the amplifier 310 is coupled to the output terminal of the high buffer amplifier via a diode 315 . The output of amplifier 312 is also coupled to the output of the high buffer amplifier via diode 316 . The negative terminals of the amplifiers 310 and 312 are respectively coupled to the output terminals of the high buffer amplifiers. The output terminal of the high buffer amplifier has a current source 319 coupled to the ground terminal for terminating the output bias signal V _SP . Therefore, according to the detected sampling signal, the output terminal of the high buffer amplifier is taken to output the bias signal V _SP .

Please refer to FIG. 9 , which illustrates a preferred embodiment of the adjustment unit 200 according to the present invention. As shown in FIG. 9 , the adjustment unit 200 includes an adjustment current mirror composed of transistors 201 and 202 , an adjustment resistor R ₃ and a unity gain buffer 207 . The first current signal I ₁ and the third current signal I _X are connected to the transistor 201 . The transistor 202 outputs an adjusted current signal according to the first current signal _I1 and the third current signal _Iλ . The adjustment resistor R ₃ is connected to the transistor 202 for receiving the adjustment current signal and generating the reference signal V _REF . The input terminal of the unity gain buffer 207 receives the reference voltage V _R1 , and its output terminal is coupled to the adjustment resistor R ₃ . The reference signal V _REF can be expressed as equation (2).

V _REF ＝V _R1 +[k ₂ ×(l _X -l ₁ )]×R ₃ Equation (2)

Where k ₂ is the current mirror ratio of transistors 201 and 202 .

Please refer to FIG. 10 , which illustrates a preferred embodiment of the output unit 250 according to the present invention. As shown in FIG. 10 , the output unit 250 includes an output resistor R ₄ , a unity gain amplifier 257 and an output current mirror composed of transistors 251 and 252 . The unity gain amplifier 257 has an output type of open collector (or open drain), and its output terminal is connected to the bus terminal (here, for example, the data terminal DATA) for generating the bus signal V _B . The bus signal V _B determines the voltage level of the high logic signal at the bus terminal. The negative terminal of the unity gain amplifier 257 is connected to its output terminal, and its positive terminal is coupled to the pull-up voltage V _M through the output resistor R ₄ . The transistor 252 is coupled to the positive terminal of the unity gain amplifier 257 . The transistor 251 receives the second current signal I ₂ . A voltage drop is generated across the output resistor _R4 according to the second current signal _I2 . Therefore, the bus signal V _B is generated according to the second current signal I ₂ , the output resistor R ₄ and the pull-up voltage V _M . The bus signal V _B can be expressed as equation (3).

V _B ＝V _M -k ₃ ×I ₂ ×R ₄ Equation (3)

Wherein, k ₃ is the current mirror ratio of transistors 251 and 252 .

Referring to equation (3), we can find that the bus signal V _B is modulated according to the output current I _O of the power supply. Because the output terminal of the unit gain amplifier 257 is an open collector (or open drain) type, the unit gain amplifier 257 can only pull down the bus signal V _B , so the bus terminal can be disconnected. In the case of no load, the maximum voltage of the bus signal V _B is regulated by the pull-up voltage V _M .

Please refer to FIG. 11 , which illustrates a preferred embodiment of parallel connection of power supplies 350 , 360 and 370 to share the output current according to the present invention. As shown in FIG. 11 , the bus signal V _B of each power supply is coupled through the bus terminal. Each power supply has an output voltage V _O1 ˜V _On , an output current I _O1 ˜I _On , and an output impedance R _O1 ˜R _On . The power supply with the largest output current arbitrates the bus signal V _B . The power supply that arbitrates the bus signal V _B is defined as the main power supply, and the other power supplies are the auxiliary supplies, and the auxiliary supplies will track the bus signal V _B to share the output current. The third current signal I _X of the auxiliary supplier is generated according to equation (1). The offset voltage V _offset determines the initial threshold. When the voltage drop of the bus signal V _B is greater than the offset voltage V _offset , the auxiliary supplier will start to generate the third current signal I _X and share the output current with the main supplier. A lower bus signal V _B will generate a higher third current signal I _X . Finally, the auxiliary supply will share the output current by increasing its output voltage. The output voltage V _O (such as V _O1 , V _{O2 .} . . V _OB ) is determined by the reference signal V _REF .

$V_o=\frac{R_A+R_B}{R_B}\&times;V_{\mathrm{REF}}$ Equation (4)

Wherein, _RA and _RB are the resistance values of the resistors _RA and _RB in FIG. 4 , respectively.

Equation (2) shows that the reference signal V _REF is adjusted by the third current signal I _X and the first current signal I ₁ , wherein the first current signal I ₁ represents the output current I _O of the power supply. When the third current signal I _X is higher than the first current signal I ₁ , the reference signal V _REF increases. An increase in the reference signal V _REF will result in an increase in the output current I _O. Finally, after increasing its output current I _O , the increase of the reference signal V _REF will be converged. An increase in the output current of the auxiliary supply will reduce the output current of the main supply through the bus terminals communicating the bus signal V _B . Therefore, the purpose of apportioning the output current is achieved. The total output current I _O is shared by all power supplies, which can be expressed as follows.

$I_0=\frac{V_o}{Z_o}=I_{01}+I_{02}+...+I_{0\mathrm{no}}=\frac{V_{o1}-V_{\mathrm{<figure-callout\; id="1"\; label="o\; R\; o"\; filenames="C20051005693800161.png,C20051005693800171.png"\; state="\{\{state\}\}">o</figure-callout>}}}{R_o}+\frac{V_{o1}-V_o}{R_{o2}}+...\frac{V_{\mathrm{On}}-V_o}{R_{\mathrm{On}}}$ Equation (5)

where Z _O represents the total output load.

Although the present invention has been disclosed above with preferred embodiments, it is not intended to limit the present invention. Anyone skilled in the art can make some changes and modifications without departing from the spirit and scope of the present invention. Therefore, this The scope of protection of the invention shall be defined by the scope of the appended patent application.

Claims (15)

1. power supply device with flow-dividing control is characterized in that it comprises:

One input;

One output;

One bus end is coupled to a bus, in order to bus communication interface and flow-dividing control interface to be provided;

One power circuit receives the input voltage of this input, outputs current to this output in order to supply an output voltage and, and wherein this power circuit produces a current sensing signal according to this output current;

One feedback control circuit is coupled to this output, in order to according to the output of this power supply device and a reference signal and produce a feedback signal;

One control unit is coupled to this power circuit and this feedback control circuit, controls this power circuit according to this feedback signal, in order to the stable output of adjusting this power supply device;

One flow-dividing control unit, be coupled to this power circuit, this bus end and this feedback control circuit, in order to according to this current sensing signal and a reference voltage and export a bus signals, and export this reference signal according to this reference voltage, this bus signals and this current sensing signal, to adjust this feedback signal; And

One bus communication circuit is coupled to this bus end, this flow-dividing control unit and this control unit, according to data that this bus end transmitted in order to monitor this power supply device;

Wherein, above-mentioned flow-dividing control unit comprises:

One draws high voltage cell, draws high voltage in order to produce one according to this reference voltage;

One draws high resistance, is coupled to this and draws high between voltage cell and this bus end;

One current generating unit is in order to produce corresponding one first current signal and one second current signal according to this current sensing signal;

One input unit is coupled to this bus end, produces one the 3rd current signal in order to draw high voltage and this bus signals according to this;

One output unit is coupled to this bus end, produces this bus signals in order to draw high voltage according to this second current signal and this; And

One adjustment unit is coupled to this input unit and this current generating unit, in order to produce and to adjust this reference signal according to this reference voltage, the 3rd current signal and this first current signal.

2. power supply device according to claim 1 is characterized in that wherein said feedback control circuit comprises:

One voltage divider is coupled to this output, in order to this output voltage carried out dividing potential drop and to produce a corresponding sensing voltage according to this; And

One amplifier, its negative terminal are coupled to this voltage divider to receive this sensing voltage, and its anode is coupled to this flow-dividing control unit to receive this reference signal, and its output is coupled to this control unit in order to export this feedback signal.

3. power supply device according to claim 1 is characterized in that wherein said input unit comprises:

One input resistance, its first end connects this and draws high voltage cell;

Surely the position detecting unit is coupled to this bus end, detects this bus signals of this bus end, in order to export a bias voltage signal; And

One buffer amplifier, its anode has an offset voltage, and be coupled to this standard position detecting unit to receive this bias voltage signal, the negative terminal of this buffer amplifier is coupled to second end of its first output and this input resistance, and second output of this buffer amplifier draws high voltage, this bias voltage signal, this offset voltage and this input resistance according to this and produces the 3rd current signal.

4. power supply device according to claim 3 is characterized in that wherein said accurate position detecting unit comprises:

One multiple sampling unit in order to the high levle of this bus signals of this bus end of taking a sample, and produces a plurality of sampled signals; And

One gets high buffer amplifier, is coupled to this multiple sampling unit, in order to voltage soprano in the above-mentioned sampled signal of foundation, and determines this bias voltage signal.

5. power supply device according to claim 1 is characterized in that wherein said output unit comprises:

One output resistance, its first end is connected to this and draws high voltage cell;

One unity gain amplifier, its anode is coupled to second end of this output resistance, its output connects the negative terminal of this bus end and this unity gain amplifier, and in order to produce this bus signals, wherein the output of this unity gain amplifier is the opener electrode or opens the kenel of drain electrode; And

One current mirror output is coupled to the anode of this unity gain amplifier, in order to produce pressure drop according to this second current signal on this output resistance;

Wherein this bus signals be according to this output resistance, this draws high voltage and this second current signal produces.

6. power supply device according to claim 1 is characterized in that wherein said adjustment unit comprises:

One adjusts current mirror, adjusts current signal in order to produce one according to the 3rd current signal and this first current signal;

One adjusts resistance, and its first end is coupled to this adjustment current mirror, receives this adjustment current signal, in order to produce this reference signal; And

One unity gain buffer, its input receives this reference voltage, and its output is coupled to second end of this adjustment resistance.

7. power supply device according to claim 1 is characterized in that wherein said bus is a serial bus.

8. power supply device according to claim 1 is characterized in that it is a power supply unit.

9. power supply device with flow-dividing control is characterized in that it comprises:

One input;

One output;

One bus end is coupled to a bus, in order to bus communication interface and flow-dividing control interface to be provided;

One power circuit receives the input voltage of this input, outputs current to this output in order to supply an output voltage and;

One feedback control circuit is coupled to this output, in order to produce a feedback signal according to the output of this power supply device;

One control unit is coupled to this power circuit and this feedback control circuit, controls this power circuit according to this feedback signal; And

One flow-dividing control unit, be coupled to this power circuit, this bus end and this feedback control circuit, in order to export a bus signals of this bus end according to this output current of this power supply device, and export a reference signal according to this output current of a reference voltage, this bus signals and this power supply device, to adjust this feedback signal, this flow-dividing control unit comprises:

One draws high voltage cell, draws high voltage in order to produce one according to this reference voltage;

One draws high resistance, is coupled to this and draws high between voltage cell and this bus end;

One input unit is coupled to this bus end, produces one the 3rd current signal in order to draw high voltage and this bus signals according to this;

One output unit is coupled to this bus end, produces this bus signals in order to draw high voltage according to this output current of this power supply device and this; And

One adjustment unit is coupled to this input unit, produces and adjust this reference signal in order to this output current according to this reference voltage, the 3rd current signal and this power supply device.

10. power supply device according to claim 9 is characterized in that wherein said feedback control circuit comprises:

One voltage divider is coupled to this output, in order to this output voltage carried out dividing potential drop and to produce a corresponding sensing voltage according to this; And

One amplifier, its negative terminal are coupled to this voltage divider to receive this sensing voltage, and its anode is coupled to this flow-dividing control unit to receive this reference signal, and its output is coupled to this control unit in order to export this feedback signal.

11. power supply device according to claim 9 is characterized in that wherein said input unit comprises:

One input resistance, its first end connects this and draws high voltage cell;

Surely the position detecting unit is coupled to this bus end, detects this bus signals of this bus end, in order to export a bias voltage signal; And

One buffer amplifier, its anode has an offset voltage, and be coupled to this standard position detecting unit to receive this bias voltage signal, the negative terminal of this buffer amplifier is coupled to second end of its first output and this input resistance, and second output of this buffer amplifier draws high voltage, this bias voltage signal, this offset voltage and this input resistance according to this and produces the 3rd current signal.

12. power supply device according to claim 11 is characterized in that wherein said accurate position detecting unit comprises:

One multiple sampling unit in order to the high levle of this bus signals of this bus end of taking a sample, and produces a plurality of sampled signals; And

One gets high buffer amplifier, is coupled to this multiple sampling unit, in order to voltage soprano in the above-mentioned sampled signal of foundation, and determines this bias voltage signal.

13. power supply device according to claim 9 is characterized in that wherein said output unit comprises:

One output resistance, its first end is connected to this and draws high voltage cell;

One unity gain amplifier, its anode is coupled to second end of this output resistance, its output connects the negative terminal of this bus end and this unity gain amplifier, and in order to produce this bus signals, wherein the output of this unity gain amplifier is the opener electrode or opens the kenel of drain electrode; And

One current mirror output is coupled to the anode of this unity gain amplifier, produces pressure drop in order to this output current according to this power supply device on this output resistance;

Wherein this bus signals is to produce according to this output resistance, this this output current that draws high voltage and this power supply device.

14. power supply device according to claim 9 is characterized in that wherein said adjustment unit comprises:

One adjusts current mirror, produces one in order to this output current according to the 3rd current signal and this power supply device and adjusts current signal;

One adjusts resistance, and its first end is coupled to this adjustment current mirror, receives this adjustment current signal, in order to produce this reference signal; And

One unity gain buffer, its input receives this reference voltage, and its output is coupled to second end of this adjustment resistance.

15. power supply device according to claim 9 is characterized in that it is a power supply unit.

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