CN100394380C - 包括对准或者广播指令的多媒体协处理器控制机制 - Google Patents
包括对准或者广播指令的多媒体协处理器控制机制 Download PDFInfo
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- CN100394380C CN100394380C CNB038239930A CN03823993A CN100394380C CN 100394380 C CN100394380 C CN 100394380C CN B038239930 A CNB038239930 A CN B038239930A CN 03823993 A CN03823993 A CN 03823993A CN 100394380 C CN100394380 C CN 100394380C
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Abstract
Description
Claims (24)
Applications Claiming Priority (3)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
US10/215,756 US6986023B2 (en) | 2002-08-09 | 2002-08-09 | Conditional execution of coprocessor instruction based on main processor arithmetic flags |
US10/215,756 | 2002-08-09 | ||
US10/263,246 | 2002-10-02 |
Publications (2)
Publication Number | Publication Date |
---|---|
CN1688966A CN1688966A (zh) | 2005-10-26 |
CN100394380C true CN100394380C (zh) | 2008-06-11 |
Family
ID=31494935
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
CNB038239930A Expired - Lifetime CN100394380C (zh) | 2002-08-09 | 2003-08-06 | 包括对准或者广播指令的多媒体协处理器控制机制 |
Country Status (3)
Country | Link |
---|---|
US (6) | US6986023B2 (zh) |
JP (3) | JP5586128B2 (zh) |
CN (1) | CN100394380C (zh) |
Families Citing this family (110)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US6986023B2 (en) * | 2002-08-09 | 2006-01-10 | Intel Corporation | Conditional execution of coprocessor instruction based on main processor arithmetic flags |
US7392368B2 (en) * | 2002-08-09 | 2008-06-24 | Marvell International Ltd. | Cross multiply and add instruction and multiply and subtract instruction SIMD execution on real and imaginary components of a plurality of complex data elements |
US7254698B2 (en) | 2003-05-12 | 2007-08-07 | International Business Machines Corporation | Multifunction hexadecimal instructions |
US7139900B2 (en) * | 2003-06-23 | 2006-11-21 | Intel Corporation | Data packet arithmetic logic devices and methods |
US7610466B2 (en) * | 2003-09-05 | 2009-10-27 | Freescale Semiconductor, Inc. | Data processing system using independent memory and register operand size specifiers and method thereof |
US7275148B2 (en) * | 2003-09-08 | 2007-09-25 | Freescale Semiconductor, Inc. | Data processing system using multiple addressing modes for SIMD operations and method thereof |
US7315932B2 (en) | 2003-09-08 | 2008-01-01 | Moyer William C | Data processing system having instruction specifiers for SIMD register operands and method thereof |
GB2411975B (en) * | 2003-12-09 | 2006-10-04 | Advanced Risc Mach Ltd | Data processing apparatus and method for performing arithmetic operations in SIMD data processing |
US8082419B2 (en) | 2004-03-30 | 2011-12-20 | Intel Corporation | Residual addition for video software techniques |
US7353244B2 (en) * | 2004-04-16 | 2008-04-01 | Marvell International Ltd. | Dual-multiply-accumulator operation optimized for even and odd multisample calculations |
US7395410B2 (en) * | 2004-07-06 | 2008-07-01 | Matsushita Electric Industrial Co., Ltd. | Processor system with an improved instruction decode control unit that controls data transfer between processor and coprocessor |
US9557994B2 (en) | 2004-07-13 | 2017-01-31 | Arm Limited | Data processing apparatus and method for performing N-way interleaving and de-interleaving operations where N is an odd plural number |
US7586904B2 (en) * | 2004-07-15 | 2009-09-08 | Broadcom Corp. | Method and system for a gigabit Ethernet IP telephone chip with no DSP core, which uses a RISC core with instruction extensions to support voice processing |
US7447725B2 (en) * | 2004-11-05 | 2008-11-04 | International Business Machines Corporation | Apparatus for controlling rounding modes in single instruction multiple data (SIMD) floating-point units |
US7219213B2 (en) * | 2004-12-17 | 2007-05-15 | Intel Corporation | Flag bits evaluation for multiple vector SIMD channels execution |
US7836284B2 (en) * | 2005-06-09 | 2010-11-16 | Qualcomm Incorporated | Microprocessor with automatic selection of processing parallelism mode based on width data of instructions |
US7694114B2 (en) | 2005-06-09 | 2010-04-06 | Qualcomm Incorporated | Software selectable adjustment of SIMD parallelism |
US7603575B2 (en) * | 2005-06-30 | 2009-10-13 | Woodbridge Nancy G | Frequency-dependent voltage control in digital logic |
US20070038984A1 (en) * | 2005-08-12 | 2007-02-15 | Gschwind Michael K | Methods for generating code for an architecture encoding an extended register specification |
US7421566B2 (en) * | 2005-08-12 | 2008-09-02 | International Business Machines Corporation | Implementing instruction set architectures with non-contiguous register file specifiers |
US7516299B2 (en) * | 2005-08-29 | 2009-04-07 | International Business Machines Corporation | Splat copying GPR data to vector register elements by executing lvsr or lvsl and vector subtract instructions |
DE102005052061A1 (de) * | 2005-11-01 | 2007-05-16 | Carl Zeiss Imaging Solutions G | Verfahren und Vorrichtung zur Bildverarbeitung |
US7555514B2 (en) * | 2006-02-13 | 2009-06-30 | Atmel Corportation | Packed add-subtract operation in a microprocessor |
US20070300042A1 (en) * | 2006-06-27 | 2007-12-27 | Moyer William C | Method and apparatus for interfacing a processor and coprocessor |
US7805590B2 (en) * | 2006-06-27 | 2010-09-28 | Freescale Semiconductor, Inc. | Coprocessor receiving target address to process a function and to send data transfer instructions to main processor for execution to preserve cache coherence |
US7925862B2 (en) * | 2006-06-27 | 2011-04-12 | Freescale Semiconductor, Inc. | Coprocessor forwarding load and store instructions with displacement to main processor for cache coherent execution when program counter value falls within predetermined ranges |
US9069547B2 (en) | 2006-09-22 | 2015-06-30 | Intel Corporation | Instruction and logic for processing text strings |
US7865698B1 (en) * | 2008-03-27 | 2011-01-04 | Xilinix, Inc. | Decode mode for an auxiliary processor unit controller in which an opcode is partially masked such that a configuration register defines a plurality of user defined instructions |
US8755515B1 (en) | 2008-09-29 | 2014-06-17 | Wai Wu | Parallel signal processing system and method |
US8918623B2 (en) | 2009-08-04 | 2014-12-23 | International Business Machines Corporation | Implementing instruction set architectures with non-contiguous register file specifiers |
US8904115B2 (en) * | 2010-09-28 | 2014-12-02 | Texas Instruments Incorporated | Cache with multiple access pipelines |
US8959501B2 (en) | 2010-12-14 | 2015-02-17 | Microsoft Corporation | Type and length abstraction for data types |
DE112011104770B4 (de) * | 2011-01-25 | 2022-08-25 | Nxp Canada Inc. | Apparat und Verfahren zum gemeinsamen Vektoreinheit Benutzen |
CN106406817B (zh) * | 2011-04-01 | 2019-06-14 | 英特尔公司 | 向量友好指令格式及其执行 |
US20130042091A1 (en) * | 2011-08-12 | 2013-02-14 | Qualcomm Incorporated | BIT Splitting Instruction |
US10318291B2 (en) | 2011-11-30 | 2019-06-11 | Intel Corporation | Providing vector horizontal compare functionality within a vector register |
WO2013081588A1 (en) * | 2011-11-30 | 2013-06-06 | Intel Corporation | Instruction and logic to provide vector horizontal compare functionality |
US9792117B2 (en) * | 2011-12-08 | 2017-10-17 | Oracle International Corporation | Loading values from a value vector into subregisters of a single instruction multiple data register |
US10534606B2 (en) | 2011-12-08 | 2020-01-14 | Oracle International Corporation | Run-length encoding decompression |
US9697174B2 (en) | 2011-12-08 | 2017-07-04 | Oracle International Corporation | Efficient hardware instructions for processing bit vectors for single instruction multiple data processors |
CN104011670B (zh) | 2011-12-22 | 2016-12-28 | 英特尔公司 | 用于基于向量写掩码的内容而在通用寄存器中存储两个标量常数之一的指令 |
WO2013095575A1 (en) * | 2011-12-22 | 2013-06-27 | Intel Corporation | Broadcast operation on mask register |
CN110471699B (zh) | 2011-12-23 | 2023-07-28 | 英特尔公司 | 用于指令处理的处理器核、方法和系统 |
CN104011659B (zh) | 2011-12-23 | 2017-06-06 | 英特尔公司 | 用于确定值是否在范围内的指令的装置和方法 |
WO2013100783A1 (en) * | 2011-12-29 | 2013-07-04 | Intel Corporation | Method and system for control signalling in a data path module |
US9864602B2 (en) | 2011-12-30 | 2018-01-09 | Intel Corporation | Packed rotate processors, methods, systems, and instructions |
US9632781B2 (en) * | 2013-02-26 | 2017-04-25 | Qualcomm Incorporated | Vector register addressing and functions based on a scalar register data value |
US9990202B2 (en) | 2013-06-28 | 2018-06-05 | Intel Corporation | Packed data element predication processors, methods, systems, and instructions |
US9323524B2 (en) * | 2013-09-16 | 2016-04-26 | Oracle International Corporation | Shift instruction with per-element shift counts and full-width sources |
US9430390B2 (en) | 2013-09-21 | 2016-08-30 | Oracle International Corporation | Core in-memory space and object management architecture in a traditional RDBMS supporting DW and OLTP applications |
US10331583B2 (en) | 2013-09-26 | 2019-06-25 | Intel Corporation | Executing distributed memory operations using processing elements connected by distributed channels |
CN104298639B (zh) * | 2014-09-23 | 2017-03-15 | 天津国芯科技有限公司 | 主处理器与若干协处理器的嵌入式连接方法及连接接口 |
US20160179530A1 (en) * | 2014-12-23 | 2016-06-23 | Elmoustapha Ould-Ahmed-Vall | Instruction and logic to perform a vector saturated doubleword/quadword add |
US9854261B2 (en) | 2015-01-06 | 2017-12-26 | Microsoft Technology Licensing, Llc. | Detecting markers in an encoded video signal |
WO2016187232A1 (en) | 2015-05-21 | 2016-11-24 | Goldman, Sachs & Co. | General-purpose parallel computing architecture |
US10210134B2 (en) * | 2015-05-21 | 2019-02-19 | Goldman Sachs & Co. LLC | General-purpose parallel computing architecture |
US10025823B2 (en) | 2015-05-29 | 2018-07-17 | Oracle International Corporation | Techniques for evaluating query predicates during in-memory table scans |
US20160378480A1 (en) * | 2015-06-27 | 2016-12-29 | Pavel G. Matveyev | Systems, Methods, and Apparatuses for Improving Performance of Status Dependent Computations |
CN105426161B (zh) * | 2015-11-12 | 2017-11-07 | 天津大学 | 一种power指令集向量协处理器的译码电路 |
US10061714B2 (en) | 2016-03-18 | 2018-08-28 | Oracle International Corporation | Tuple encoding aware direct memory access engine for scratchpad enabled multicore processors |
US10061832B2 (en) | 2016-11-28 | 2018-08-28 | Oracle International Corporation | Database tuple-encoding-aware data partitioning in a direct memory access engine |
US10055358B2 (en) | 2016-03-18 | 2018-08-21 | Oracle International Corporation | Run length encoding aware direct memory access filtering engine for scratchpad enabled multicore processors |
US10402425B2 (en) | 2016-03-18 | 2019-09-03 | Oracle International Corporation | Tuple encoding aware direct memory access engine for scratchpad enabled multi-core processors |
US10599488B2 (en) | 2016-06-29 | 2020-03-24 | Oracle International Corporation | Multi-purpose events for notification and sequence control in multi-core processor systems |
US10380058B2 (en) | 2016-09-06 | 2019-08-13 | Oracle International Corporation | Processor core to coprocessor interface with FIFO semantics |
US10402168B2 (en) | 2016-10-01 | 2019-09-03 | Intel Corporation | Low energy consumption mantissa multiplication for floating point multiply-add operations |
US10783102B2 (en) | 2016-10-11 | 2020-09-22 | Oracle International Corporation | Dynamically configurable high performance database-aware hash engine |
US10459859B2 (en) | 2016-11-28 | 2019-10-29 | Oracle International Corporation | Multicast copy ring for database direct memory access filtering engine |
US10176114B2 (en) | 2016-11-28 | 2019-01-08 | Oracle International Corporation | Row identification number generation in database direct memory access engine |
US10725947B2 (en) | 2016-11-29 | 2020-07-28 | Oracle International Corporation | Bit vector gather row count calculation and handling in direct memory access engine |
US10474375B2 (en) | 2016-12-30 | 2019-11-12 | Intel Corporation | Runtime address disambiguation in acceleration hardware |
US10416999B2 (en) | 2016-12-30 | 2019-09-17 | Intel Corporation | Processors, methods, and systems with a configurable spatial accelerator |
US10572376B2 (en) | 2016-12-30 | 2020-02-25 | Intel Corporation | Memory ordering in acceleration hardware |
US10558575B2 (en) | 2016-12-30 | 2020-02-11 | Intel Corporation | Processors, methods, and systems with a configurable spatial accelerator |
US20200073635A1 (en) * | 2017-06-29 | 2020-03-05 | Intel Corporation | Systems, apparatuses, and methods for vector-packed fractional multiplication of signed words with rounding, saturation, and high-result selection |
US11334319B2 (en) | 2017-06-30 | 2022-05-17 | Intel Corporation | Apparatus and method for multiplication and accumulation of complex values |
US11294679B2 (en) * | 2017-06-30 | 2022-04-05 | Intel Corporation | Apparatus and method for multiplication and accumulation of complex values |
US10515049B1 (en) | 2017-07-01 | 2019-12-24 | Intel Corporation | Memory circuits and methods for distributed memory hazard detection and error recovery |
US10469397B2 (en) | 2017-07-01 | 2019-11-05 | Intel Corporation | Processors and methods with configurable network-based dataflow operator circuits |
US10515046B2 (en) | 2017-07-01 | 2019-12-24 | Intel Corporation | Processors, methods, and systems with a configurable spatial accelerator |
US10387319B2 (en) | 2017-07-01 | 2019-08-20 | Intel Corporation | Processors, methods, and systems for a configurable spatial accelerator with memory system performance, power reduction, and atomics support features |
US10445234B2 (en) | 2017-07-01 | 2019-10-15 | Intel Corporation | Processors, methods, and systems for a configurable spatial accelerator with transactional and replay features |
US10445451B2 (en) | 2017-07-01 | 2019-10-15 | Intel Corporation | Processors, methods, and systems for a configurable spatial accelerator with performance, correctness, and power reduction features |
US10467183B2 (en) | 2017-07-01 | 2019-11-05 | Intel Corporation | Processors and methods for pipelined runtime services in a spatial array |
US10496574B2 (en) | 2017-09-28 | 2019-12-03 | Intel Corporation | Processors, methods, and systems for a memory fence in a configurable spatial accelerator |
US11086816B2 (en) | 2017-09-28 | 2021-08-10 | Intel Corporation | Processors, methods, and systems for debugging a configurable spatial accelerator |
US10380063B2 (en) | 2017-09-30 | 2019-08-13 | Intel Corporation | Processors, methods, and systems with a configurable spatial accelerator having a sequencer dataflow operator |
US10445098B2 (en) | 2017-09-30 | 2019-10-15 | Intel Corporation | Processors and methods for privileged configuration in a spatial array |
US10445250B2 (en) | 2017-12-30 | 2019-10-15 | Intel Corporation | Apparatus, methods, and systems with a configurable spatial accelerator |
US10565134B2 (en) | 2017-12-30 | 2020-02-18 | Intel Corporation | Apparatus, methods, and systems for multicast in a configurable spatial accelerator |
US10417175B2 (en) | 2017-12-30 | 2019-09-17 | Intel Corporation | Apparatus, methods, and systems for memory consistency in a configurable spatial accelerator |
US10528346B2 (en) | 2018-03-29 | 2020-01-07 | Intel Corporation | Instructions for fused multiply-add operations with variable precision input operands |
US11307873B2 (en) | 2018-04-03 | 2022-04-19 | Intel Corporation | Apparatus, methods, and systems for unstructured data flow in a configurable spatial accelerator with predicate propagation and merging |
US10564980B2 (en) | 2018-04-03 | 2020-02-18 | Intel Corporation | Apparatus, methods, and systems for conditional queues in a configurable spatial accelerator |
US10853073B2 (en) | 2018-06-30 | 2020-12-01 | Intel Corporation | Apparatuses, methods, and systems for conditional operations in a configurable spatial accelerator |
US10891240B2 (en) | 2018-06-30 | 2021-01-12 | Intel Corporation | Apparatus, methods, and systems for low latency communication in a configurable spatial accelerator |
US10459866B1 (en) | 2018-06-30 | 2019-10-29 | Intel Corporation | Apparatuses, methods, and systems for integrated control and data processing in a configurable spatial accelerator |
US11200186B2 (en) | 2018-06-30 | 2021-12-14 | Intel Corporation | Apparatuses, methods, and systems for operations in a configurable spatial accelerator |
US10678724B1 (en) | 2018-12-29 | 2020-06-09 | Intel Corporation | Apparatuses, methods, and systems for in-network storage in a configurable spatial accelerator |
US10965536B2 (en) | 2019-03-30 | 2021-03-30 | Intel Corporation | Methods and apparatus to insert buffers in a dataflow graph |
US10915471B2 (en) | 2019-03-30 | 2021-02-09 | Intel Corporation | Apparatuses, methods, and systems for memory interface circuit allocation in a configurable spatial accelerator |
US11029927B2 (en) | 2019-03-30 | 2021-06-08 | Intel Corporation | Methods and apparatus to detect and annotate backedges in a dataflow graph |
US10817291B2 (en) | 2019-03-30 | 2020-10-27 | Intel Corporation | Apparatuses, methods, and systems for swizzle operations in a configurable spatial accelerator |
US11037050B2 (en) | 2019-06-29 | 2021-06-15 | Intel Corporation | Apparatuses, methods, and systems for memory interface circuit arbitration in a configurable spatial accelerator |
US11029958B1 (en) * | 2019-12-28 | 2021-06-08 | Intel Corporation | Apparatuses, methods, and systems for configurable operand size operations in an operation configurable spatial accelerator |
US11907713B2 (en) | 2019-12-28 | 2024-02-20 | Intel Corporation | Apparatuses, methods, and systems for fused operations using sign modification in a processing element of a configurable spatial accelerator |
US11868777B2 (en) * | 2020-12-16 | 2024-01-09 | Advanced Micro Devices, Inc. | Processor-guided execution of offloaded instructions using fixed function operations |
US11625249B2 (en) | 2020-12-29 | 2023-04-11 | Advanced Micro Devices, Inc. | Preserving memory ordering between offloaded instructions and non-offloaded instructions |
US11921634B2 (en) | 2021-12-28 | 2024-03-05 | Advanced Micro Devices, Inc. | Leveraging processing-in-memory (PIM) resources to expedite non-PIM instructions executed on a host |
US12050531B2 (en) * | 2022-09-26 | 2024-07-30 | Advanced Micro Devices, Inc. | Data compression and decompression for processing in memory |
Citations (3)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US4750110A (en) * | 1983-04-18 | 1988-06-07 | Motorola, Inc. | Method and apparatus for executing an instruction contingent upon a condition present in another data processor |
US6298438B1 (en) * | 1996-12-02 | 2001-10-02 | Advanced Micro Devices, Inc. | System and method for conditional moving an operand from a source register to destination register |
US6332186B1 (en) * | 1998-05-27 | 2001-12-18 | Arm Limited | Vector register addressing |
Family Cites Families (67)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JPS57185540A (en) * | 1981-05-11 | 1982-11-15 | Hitachi Ltd | Data processor |
JPH0766349B2 (ja) * | 1985-04-30 | 1995-07-19 | 富士通株式会社 | シフタ回路 |
US4873630A (en) * | 1985-07-31 | 1989-10-10 | Unisys Corporation | Scientific processor to support a host processor referencing common memory |
JPS62214464A (ja) * | 1986-03-17 | 1987-09-21 | Hitachi Ltd | データ処理システム |
US5073864A (en) * | 1987-02-10 | 1991-12-17 | Davin Computer Corporation | Parallel string processor and method for a minicomputer |
JPS63261449A (ja) * | 1987-04-20 | 1988-10-28 | Hitachi Ltd | デ−タ処理装置 |
MY104191A (en) * | 1988-09-06 | 1994-02-28 | Mitsubishi Gas Chemical Co | Process for producing multilayer printed wiring board |
US5420989A (en) * | 1991-06-12 | 1995-05-30 | Cyrix Corporation | Coprocessor interface supporting I/O or memory mapped communications |
JP3043861B2 (ja) * | 1991-09-30 | 2000-05-22 | 株式会社東芝 | データ処理装置 |
US5420809A (en) * | 1993-11-30 | 1995-05-30 | Texas Instruments Incorporated | Method of operating a data processing apparatus to compute correlation |
US5734874A (en) * | 1994-04-29 | 1998-03-31 | Sun Microsystems, Inc. | Central processing unit with integrated graphics functions |
ZA9510127B (en) * | 1994-12-01 | 1996-06-06 | Intel Corp | Novel processor having shift operations |
WO1996017291A1 (en) * | 1994-12-02 | 1996-06-06 | Intel Corporation | Microprocessor with packing operation of composite operands |
GB9509989D0 (en) * | 1995-05-17 | 1995-07-12 | Sgs Thomson Microelectronics | Manipulation of data |
US5815715A (en) * | 1995-06-05 | 1998-09-29 | Motorola, Inc. | Method for designing a product having hardware and software components and product therefor |
US5696985A (en) * | 1995-06-07 | 1997-12-09 | International Business Machines Corporation | Video processor |
CN103455304B (zh) * | 1995-08-31 | 2016-04-27 | 英特尔公司 | 用于处理指令集的处理器 |
US6385634B1 (en) * | 1995-08-31 | 2002-05-07 | Intel Corporation | Method for performing multiply-add operations on packed data |
US5721892A (en) * | 1995-08-31 | 1998-02-24 | Intel Corporation | Method and apparatus for performing multiply-subtract operations on packed data |
US5936872A (en) * | 1995-09-05 | 1999-08-10 | Intel Corporation | Method and apparatus for storing complex numbers to allow for efficient complex multiplication operations and performing such complex multiplication operations |
JPH0997178A (ja) * | 1995-09-29 | 1997-04-08 | Matsushita Electric Ind Co Ltd | 飽和演算処理装置および方法 |
JP3701401B2 (ja) * | 1996-08-12 | 2005-09-28 | 株式会社ルネサステクノロジ | 飽和演算命令を有するマイクロプロセッサ |
US5838984A (en) * | 1996-08-19 | 1998-11-17 | Samsung Electronics Co., Ltd. | Single-instruction-multiple-data processing using multiple banks of vector registers |
US5805875A (en) * | 1996-09-13 | 1998-09-08 | International Computer Science Institute | Vector processing system with multi-operation, run-time configurable pipelines |
US5893066A (en) * | 1996-10-15 | 1999-04-06 | Samsung Electronics Co. Ltd. | Fast requantization apparatus and method for MPEG audio decoding |
US6016395A (en) * | 1996-10-18 | 2000-01-18 | Samsung Electronics Co., Ltd. | Programming a vector processor and parallel programming of an asymmetric dual multiprocessor comprised of a vector processor and a risc processor |
US6006315A (en) * | 1996-10-18 | 1999-12-21 | Samsung Electronics Co., Ltd. | Computer methods for writing a scalar value to a vector |
US5930519A (en) * | 1997-04-30 | 1999-07-27 | Hewlett Packard Company | Distributed branch logic system and method for a geometry accelerator |
JP3781519B2 (ja) * | 1997-08-20 | 2006-05-31 | 富士通株式会社 | プロセッサの命令制御機構 |
US5923893A (en) * | 1997-09-05 | 1999-07-13 | Motorola, Inc. | Method and apparatus for interfacing a processor to a coprocessor |
US5933650A (en) * | 1997-10-09 | 1999-08-03 | Mips Technologies, Inc. | Alignment and ordering of vector elements for single instruction multiple data processing |
US8489860B1 (en) * | 1997-12-22 | 2013-07-16 | Texas Instruments Incorporated | Mobile electronic device having a host processor system capable of dynamically canging tasks performed by a coprocessor in the device |
US5996057A (en) * | 1998-04-17 | 1999-11-30 | Apple | Data processing system and method of permutation with replication within a vector register file |
US6247113B1 (en) * | 1998-05-27 | 2001-06-12 | Arm Limited | Coprocessor opcode division by data type |
GB2338094B (en) * | 1998-05-27 | 2003-05-28 | Advanced Risc Mach Ltd | Vector register addressing |
US6178500B1 (en) * | 1998-06-25 | 2001-01-23 | International Business Machines Corporation | Vector packing and saturation detection in the vector permute unit |
US6272512B1 (en) * | 1998-10-12 | 2001-08-07 | Intel Corporation | Data manipulation instruction for enhancing value and efficiency of complex arithmetic |
US6282633B1 (en) * | 1998-11-13 | 2001-08-28 | Tensilica, Inc. | High data density RISC processor |
US6529930B1 (en) * | 1998-11-16 | 2003-03-04 | Hitachi America, Ltd. | Methods and apparatus for performing a signed saturation operation |
WO2000043868A1 (en) | 1999-01-20 | 2000-07-27 | Hitachi, Ltd. | Data processor and device for arithmetic operation |
JP2000222208A (ja) * | 1999-01-29 | 2000-08-11 | Mitsubishi Electric Corp | 情報処理装置、命令割当て制御方法、命令割当て制御装置および命令割当て制御プログラムを記録したコンピュータで読取り可能な記録媒体 |
GB2355084B (en) * | 1999-07-21 | 2004-04-28 | Element 14 Ltd | Setting condition values in a computer |
US6546480B1 (en) * | 1999-10-01 | 2003-04-08 | Hitachi, Ltd. | Instructions for arithmetic operations on vectored data |
US6526430B1 (en) * | 1999-10-04 | 2003-02-25 | Texas Instruments Incorporated | Reconfigurable SIMD coprocessor architecture for sum of absolute differences and symmetric filtering (scalable MAC engine for image processing) |
US6430684B1 (en) * | 1999-10-29 | 2002-08-06 | Texas Instruments Incorporated | Processor circuits, systems, and methods with efficient granularity shift and/or merge instruction(s) |
AU1780301A (en) * | 1999-11-18 | 2001-05-30 | Sun Microsystems, Inc. | Decompression bit processing with a general purpose alignment tool |
JP2001229138A (ja) * | 2000-02-15 | 2001-08-24 | Sony Corp | 画像処理装置および画像処理方法 |
US6671797B1 (en) * | 2000-02-18 | 2003-12-30 | Texas Instruments Incorporated | Microprocessor with expand instruction for forming a mask from one bit |
US6748521B1 (en) * | 2000-02-18 | 2004-06-08 | Texas Instruments Incorporated | Microprocessor with instruction for saturating and packing data |
WO2001063434A1 (en) * | 2000-02-24 | 2001-08-30 | Bops, Incorporated | Methods and apparatus for dual-use coprocessing/debug interface |
US6829697B1 (en) * | 2000-09-06 | 2004-12-07 | International Business Machines Corporation | Multiple logical interfaces to a shared coprocessor resource |
US20020065860A1 (en) * | 2000-10-04 | 2002-05-30 | Grisenthwaite Richard Roy | Data processing apparatus and method for saturating data values |
US20020083311A1 (en) * | 2000-12-27 | 2002-06-27 | Paver Nigel C. | Method and computer program for single instruction multiple data management |
US6754804B1 (en) * | 2000-12-29 | 2004-06-22 | Mips Technologies, Inc. | Coprocessor interface transferring multiple instructions simultaneously along with issue path designation and/or issue order designation for the instructions |
JP3776732B2 (ja) * | 2001-02-02 | 2006-05-17 | 株式会社東芝 | プロセッサ装置 |
US6889242B1 (en) * | 2001-06-29 | 2005-05-03 | Koninklijke Philips Electronics N.V. | Rounding operations in computer processor |
US7228401B2 (en) * | 2001-11-13 | 2007-06-05 | Freescale Semiconductor, Inc. | Interfacing a processor to a coprocessor in which the processor selectively broadcasts to or selectively alters an execution mode of the coprocessor |
US7853778B2 (en) * | 2001-12-20 | 2010-12-14 | Intel Corporation | Load/move and duplicate instructions for a processor |
US20040073773A1 (en) * | 2002-02-06 | 2004-04-15 | Victor Demjanenko | Vector processor architecture and methods performed therein |
US20030167460A1 (en) * | 2002-02-26 | 2003-09-04 | Desai Vipul Anil | Processor instruction set simulation power estimation method |
US7065546B2 (en) * | 2002-04-09 | 2006-06-20 | Sony Electronics Inc. | Method of performing quantization within a multimedia bitstream utilizing division-free instructions |
JP4202673B2 (ja) * | 2002-04-26 | 2008-12-24 | 株式会社東芝 | システムlsi開発環境生成方法及びそのプログラム |
US20030221089A1 (en) * | 2002-05-23 | 2003-11-27 | Sun Microsystems, Inc. | Microprocessor data manipulation matrix module |
US7020873B2 (en) * | 2002-06-21 | 2006-03-28 | Intel Corporation | Apparatus and method for vectorization of detected saturation and clipping operations in serial code loops of a source program |
US6986023B2 (en) * | 2002-08-09 | 2006-01-10 | Intel Corporation | Conditional execution of coprocessor instruction based on main processor arithmetic flags |
AU2003256870A1 (en) | 2002-08-09 | 2004-02-25 | Intel Corporation | Multimedia coprocessor control mechanism including alignment or broadcast instructions |
US7689641B2 (en) * | 2003-06-30 | 2010-03-30 | Intel Corporation | SIMD integer multiply high with round and shift |
-
2002
- 2002-08-09 US US10/215,756 patent/US6986023B2/en not_active Expired - Lifetime
- 2002-09-30 US US10/262,195 patent/US7213128B2/en not_active Expired - Lifetime
- 2002-10-02 US US10/263,246 patent/US7047393B2/en not_active Expired - Lifetime
-
2003
- 2003-08-06 CN CNB038239930A patent/CN100394380C/zh not_active Expired - Lifetime
-
2007
- 2007-04-30 US US11/797,067 patent/US7373488B2/en not_active Expired - Lifetime
-
2008
- 2008-05-01 US US12/149,429 patent/US20080209187A1/en not_active Abandoned
- 2008-06-20 JP JP2008161911A patent/JP5586128B2/ja not_active Expired - Fee Related
-
2009
- 2009-08-12 US US12/539,944 patent/US8131981B2/en not_active Expired - Lifetime
-
2011
- 2011-01-28 JP JP2011016901A patent/JP5634898B2/ja not_active Expired - Lifetime
-
2014
- 2014-07-31 JP JP2014156777A patent/JP2014225287A/ja active Pending
Patent Citations (3)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US4750110A (en) * | 1983-04-18 | 1988-06-07 | Motorola, Inc. | Method and apparatus for executing an instruction contingent upon a condition present in another data processor |
US6298438B1 (en) * | 1996-12-02 | 2001-10-02 | Advanced Micro Devices, Inc. | System and method for conditional moving an operand from a source register to destination register |
US6332186B1 (en) * | 1998-05-27 | 2001-12-18 | Arm Limited | Vector register addressing |
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US20080209187A1 (en) | 2008-08-28 |
JP5586128B2 (ja) | 2014-09-10 |
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JP2009037599A (ja) | 2009-02-19 |
JP5634898B2 (ja) | 2014-12-03 |
CN1688966A (zh) | 2005-10-26 |
JP2011108265A (ja) | 2011-06-02 |
US7213128B2 (en) | 2007-05-01 |
US7047393B2 (en) | 2006-05-16 |
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