CN100390936C - 形成微电子电路元件的方法 - Google Patents
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Abstract
描述一种形成微电子电路元件的方法。在支撑层的上表面形成牺牲层。所述牺牲层极薄且均匀。然后在所述牺牲层上形成定高层，此后蚀刻掉所述牺牲层，使得在所述支撑层的上表面和所述定高层的下表面之间留下明确界定的间隙。然后，通过所述间隙从成核硅位置选择性地生长单晶半导体材料。所述单晶半导体材料形成具有厚度与所述原始牺牲层的厚度一致的单晶层。
Description
发明背景
1)技术领域
本发明涉及形成微电子电路元件(element of a microelectronic circuit)的方法以及包括所述元件的器件。
2)背景技术
纳米技术涉及在多个方向上形成具有纳米数量级尺寸的极小结构。
某些器件，例如绝缘硅(SOI)器件，要求在绝缘电介质层上形成单晶硅或其他单晶半导体材料。存在多种能被用来在绝缘层上产生单晶半导体层的技术。这样的技术通常涉及对单晶半导体材料进行特定深度的离子注入，将另一个晶片的电介质层附着到所述半导体材料，随后在离子注入到的深度对所述半导体材料进行剪切(shearing)，此后在所述电介质层上遗留下一层薄薄的半导体材料。这样，能够在电介质层上形成非常薄且均匀的半导体层。
但是，半导体制造环境很少为晶片的彼此附着以及随后的晶片从彼此剪切做好准备，因此所述环境对于SOI器件的加工而言是装备不良的。
附图说明
参照附图，以实施例的方式来描述本发明，其中：
图1图示出自晶片的部分的透视图，所述部分包括单晶衬底、电介质层、以及薄且均匀的牺牲层；
图2是在蚀刻掉牺牲层的左部分以后，与图1相似的视图；
图3是在形成定高(height-defining)层以后，与图2相似的视图；
图4是在定高层和电介质层的左前部分被蚀刻掉以留下暴露在单晶衬底上的成核位置以后，与图3相似的视图；
图5是在蚀刻牺牲层以在电介质层和定高层的右部分之间留下间隙以后，与图4相似的视图；
图6是在单晶半导体材料的最初部分在成核位置上生长以后，与图5相似的视图；
图7是已生长单晶半导体材料使得在间隙中形成单晶层以后，与图6相似的视图；
图8是在定高层的右部分上形成掩模块以后，与图7相似的视图；
图9是在蚀刻定高层以后，与图8相似的视图，其中以掩模块定义定高层的间隔块(spacerblock)的尺寸，所述间隔块保留在单晶层上；
图10是邻近间隔块的相对侧形成间隔侧墙以后，与图9相似的视图；
图11是在间隔块被蚀刻掉以后，与图10相似的视图；
图12是在蚀刻单晶层以后，与图11相似的视图，其中以间隔侧墙用来作为掩模，使得单晶层的单晶线元件保留在电介质层上；
图13是间隔侧墙被蚀刻掉以后，与图12相似的视图；以及
图14是与图13相似的视图，图示了包括线元件的三-栅(tri-gate)晶体管器件的加工。
具体实施方式
在以下的描述中，使用诸如水平的、垂直的、宽度、长度、高度和厚度的术语。这些术语被使用来描述和定义结构和表面彼此相关的方位，并且不应被解释为绝对参照系所固有的。
附图中的图1图示出自已经部分加工的晶片的部分20，其具有宽度22和长度24。部分20包括常规的硅单晶衬底26，形成在单晶衬底26上的支撑二氧化硅(SiO2)电介质层28，以及形成在电介质层28上的氮化硅(Si2NO3)牺牲层30。衬底可以例如是硅(Si)、锗(Ge)、硅锗(SixGey)、砷化镓(GaAs)、InSb、GaP、GaSb或碳。牺牲层30具有厚度34A，所述厚度极薄，典型为几个纳米的数量级。例如，一种形成15nm薄且均匀的氮化硅层的工艺为等离子体增强化学气相沉积(CVD)，其具有1KW的功率，13.5MHz的高频，或者在2和3托(Torr)之间的CVD条件下约10KHz的低频，具有350-450℃的温度，具有75-150sccm的硅烷流速，10-15slm的N2O的流速，以及20slm的N2流速。
如图2所示，随后除去牺牲层30的部分。牺牲层30的保留部分现在具有宽度35，并且电介质层的部分36被暴露。部分36具有宽度38，并且沿长度24延伸。牺牲层30的侧表面42被暴露。
如图3所示，定高层44随后形成。定高层44典型地由与电介质层28相同的材料制成。定高层44具有在电介质层28上并且在结构上与其连接的左部分46，还具有右部分48，其具有在牺牲层30的上表面上的下表面。电介质层28的水平上表面与右部分48的水平下表面之间的距离由牺牲层30的厚度34A定义。
图4图示了图3在左部分46的前部被除去以后的结构。掩模(masking)图3的整个结构，而在左部分46的前部上方留下开口，然后暴露左部分46的前部给蚀刻剂，所述蚀刻剂选择性地除去在单晶衬底26材料上的电介质层28、牺牲层30以及定高层44的材料。定高层44通过左部分46的后部分50仍然在结构上与电介质层28和单晶衬底26连接。牺牲层30的侧表面42暴露在已被蚀刻出来的部分内。成核位置52暴露在单晶衬底26上。
如图5所示，牺牲层30随后被蚀刻掉。使用蚀刻剂选择性地除去图4所示的其他组成部分(component)的材料上的牺牲层30的一些材料。后部分50将右部分48悬挂在电介质层28上方。间隙34B被定义在电介质层28的上表面和右部分48的下表面之间。间隙54具有与牺牲层30的最初厚度34A相等的垂直高度34B。
在氢烘烤(hydrogen bake)步骤中，以20托20slm的H2流速，在200℃下清洁成核位置52三分钟。
然后，如图6所示，在成核位置52上开始单晶半导体材料60的生长。用于硅的外延生长的常规工艺可以用来选择性地生长单晶半导体材料60，例如，一种CVD工艺是在20托的压力，240sccm的SiH2CL2，140sccm的HCl和20slm的氢的情况下，在温度为825℃的ASM E3000外延反应器中进行的。单晶半导体材料60从成核位置52生长，垂直向上经过电介质层28的左侧表面。成核位置52的预清洁与所述工艺条件一起确保材料60是单晶的，并且无缺陷。应该注意的是，间隙54在单晶半导体材料60的一侧上是开放的。作为替换，可以使用SiXGeY或者另一种材料来代替硅。
如图7所示，单晶半导体材料60随后从左向右水平生长通过间隙54。这样，薄单晶层62形成在间隙54中。单晶层62具有与间隙54的高度34B以及牺牲层30的最初厚度34A相等的厚度34C。由于牺牲层30极薄并且具有非常均匀的厚度，单晶层62也极薄并且具有极其均匀的厚度。
参照图8和图9，随后掩模块64(图8)在右部分48上形成图形。然后使用掩模块64来图形化出自定高层44的间隔块66，此后掩模块64被除去(图9)。间隔块66具有与掩模块64相同的宽度和长度。
如图10所示，随后在间隔块66的相对侧上以及单晶层62的上表面上形成氮化硅间隔侧墙68。通过在单晶层62上以及间隔块66的相对侧表面和上表面上保形地(conformally)沉积氮化硅层来形成间隔侧墙68，此后将所述氮化硅层回蚀(etch back)以留下间隔侧墙68。使用蚀刻剂选择性地除去在纯单晶硅和二氧化硅上的氮化硅。这样的工艺的优点在于间隔侧墙68能够被制成厚度极薄且均匀。因此，在所给出的实施方案中，定高层44用作双重目的，即定义间隙54的垂直高度34B，为了定义间隔侧墙68的位置而形成的间隔块66也出自定高层44。
如图11所示，间隔块66随后被除去。于是，除了正好在间隔侧墙68下面以外，单晶层62的整个上表面都被暴露。使用蚀刻剂并且选择性地除去在氮化硅和纯单晶硅上的二氧化硅。
参照图12，以间隔侧墙68作为掩模，通过各向异性地蚀刻单晶层62来除去单晶层62的暴露部分。单晶层62所遗留的是正好在间隔侧墙68下面的单晶线元件(wire element)72。
参照图13，随后用蚀刻剂除去间隔侧墙，所述蚀刻剂选择性地除去在纯单晶硅和二氧化硅上的氮化硅。于是，线元件72的上表面被暴露。线元件72的高度与最初的牺牲层的厚度相等；线元件72的宽度由间隔侧墙68的宽度定义。
如图14所示，线元件72可以成为三-栅晶体管器件74的部分。首先以P-或者N-掺杂物注入每个半导体线元件72，使其成为可导电的。然后，在每个线元件72的相对侧以及上表面上形成栅电介质层76。然后，在两个栅电介质层76的上表面和侧表面上构造导电的栅电极78。然后，将线元件72退火以活化所述掺杂物。可以在线元件72上施加电压。当栅电极78接通电压时，电流流过线元件72。
尽管已经描述并且在附图中示出了某些示例性的实施方案，但应该可以理解，这样的实施方案仅仅是例证性的并且对本发明不是限制性的，并且本发明不应被限制于这些所示出和描述的具体构造和布局，因为本领域普通技术人员可以进行修改。
Claims (10)
1.一种形成微电子电路元件的方法，包括：
形成牺牲层，所述牺牲层具有在支撑层的上表面上的下表面，其中所述支撑层形成在半导体单晶衬底的部分上，所述半导体单晶衬底的未被所述支撑层覆盖的开放部分具有成核位置，并且所述牺牲层与所述半导体单晶衬底不连接；
形成定高层，所述定高层具有在所述牺牲层的上表面上的下表面；
除去牺牲层，从而在所述支撑层的所述上表面和所述定高层的所述下表面之间定义间隙；
至少部分地通过所述间隙从所述成核位置生长单晶半导体材料，所述单晶半导体材料的高度由所述间隙的高度定义；
图案化所述定高层以在所述单晶半导体材料上形成间隔块；
通过在所述单晶半导体材料和所述间隔块的表面上沉积保形层并且回蚀所述保形层，在所述间隔块的侧面形成间隔侧墙；
除去所述间隔块；以及
利用所述间隔侧墙作为掩模蚀刻所述单晶半导体材料，以从所述单晶半导体材料形成线元件。
2.如权利要求1的方法，其中所述支撑层是绝缘体。
3.如权利要求2的方法，还包括：
掺杂所述线元件；以及
在所述线元件的相对侧上并且沿所述线元件的相对侧形成导电栅。
4.如权利要求1的方法，其中所述单晶半导体材料是硅(Si)、锗(Ge)、硅锗(SixGey)、砷化镓(GaAs)、InSb、GaP、GaSb和碳中的至少一种。
5.一种形成微电子电路元件的方法，包括：
在半导体单晶衬底的部分上形成电介质层，所述半导体单晶衬底的未被所述电介质层覆盖的开放部分作为成核位置；
在所述半导体单晶衬底上形成结构，所述结构具有定高层、被定义在所述电介质层的上表面和所述定高层的下表面之间的间隙，所述间隙与所述半导体单晶衬底不连接；
从在半导体单晶衬底上的所述成核位置生长单晶半导体材料，所述单晶半导体材料至少部分地通过所述间隙生长，所述单晶半导体材料的高度由所述间隙的高度定义；
图案化所述定高层以在所述单晶半导体材料上形成间隔块；
通过在所述单晶半导体材料和所述间隔块的表面上沉积保形层并且回蚀所述保形层，在所述间隔块的侧面形成间隔侧墙；
除去所述间隔块；以及
利用所述间隔侧墙作为掩模蚀刻所述单晶半导体材料，以从所述单晶半导体材料形成线元件。
6.如权利要求5的方法，其中所述电介质层是绝缘体。
7.如权利要求6的方法，还包括：
掺杂所述线元件；以及
在所述线元件的相对侧上并且沿所述线元件的相对侧形成导电栅。
8.一种形成微电子电路元件的方法，包括：
在水平半导体单晶衬底的部分上水平地形成电介质层，所述半导体单晶衬底的未被所述电介质层覆盖的开放部分作为成核位置；
形成牺牲层，所述牺牲层具有在所述电介质层的水平上表面上的水平下表面，所述牺牲层的材料不同于所述电介质层，并且所述牺牲层与所述半导体单晶衬底不连接；
形成定高层，所述定高层具有在所述牺牲层的水平上表面上的下表面，所述定高层的材料不同于所述牺牲层；
用蚀刻剂除去所述牺牲层，所述蚀刻剂选择性地除去在所述电介质层和所述定高层材料上的所述牺牲层材料，从而在所述电介质层的所述上表面和所述定高层的所述下表面之间留下间隙，所述定高层通过在所述半导体单晶衬底上的支撑段被保持在相对于所述电介质层的垂直位置；
从所述半导体单晶衬底上的所述成核位置生长单晶半导体材料，所述单晶半导体材料通过至少部分所述间隙水平地生长以形成半导体层，所述半导体层的垂直高度受所述间隙的垂直高度限制；
图案化所述定高层以在所述单晶半导体材料上形成间隔块；
通过在所述单晶半导体材料和所述间隔块的表面上沉积保形层并且回蚀所述保形层，在所述间隔块的侧面形成间隔侧墙；
除去所述间隔块；以及
利用所述间隔侧墙作为掩模蚀刻所述单晶半导体材料，以从所述单晶半导体材料形成线元件。
9.如权利要求8的方法，还包括：
掺杂所述线元件；以及
在所述线元件的相对侧上并且沿所述线元件的相对侧形成导电栅。
10.如权利要求8的方法，其中，在水平地生长进所述间隙以前，所述单晶半导体材料垂直地生长超过所述电介质层。
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|---|---|---|---|
| US10/387,623 | 2003-03-12 | ||
| US10/387,623 US6972228B2 (en) | 2003-03-12 | 2003-03-12 | Method of forming an element of a microelectronic circuit |
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| Publication Number | Publication Date |
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| CN1748289A CN1748289A (zh) | 2006-03-15 |
| CN100390936C true CN100390936C (zh) | 2008-05-28 |
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| EP (1) | EP1602126A1 (zh) |
| CN (1) | CN100390936C (zh) |
| AU (1) | AU2003297950A1 (zh) |
| TW (1) | TWI230418B (zh) |
| WO (1) | WO2004082002A1 (zh) |
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| Publication number | Priority date | Publication date | Assignee | Title |
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| US8994104B2 (en) | 1999-09-28 | 2015-03-31 | Intel Corporation | Contact resistance reduction employing germanium overlayer pre-contact metalization |
| KR100594295B1 (ko) * | 2004-09-24 | 2006-06-30 | 삼성전자주식회사 | 층 성장을 이용한 게이트 형성 방법 및 이에 따른 게이트구조 |
| US7709391B2 (en) * | 2006-01-20 | 2010-05-04 | Applied Materials, Inc. | Methods for in-situ generation of reactive etch and growth specie in film formation processes |
| US7976634B2 (en) | 2006-11-21 | 2011-07-12 | Applied Materials, Inc. | Independent radiant gas preheating for precursor disassociation control and gas reaction kinetics in low temperature CVD systems |
| US8278687B2 (en) * | 2008-03-28 | 2012-10-02 | Intel Corporation | Semiconductor heterostructures to reduce short channel effects |
| US8129749B2 (en) * | 2008-03-28 | 2012-03-06 | Intel Corporation | Double quantum well structures for transistors |
| US8440998B2 (en) * | 2009-12-21 | 2013-05-14 | Intel Corporation | Increasing carrier injection velocity for integrated circuit devices |
| US8633470B2 (en) * | 2009-12-23 | 2014-01-21 | Intel Corporation | Techniques and configurations to impart strain to integrated circuit devices |
| US8227304B2 (en) | 2010-02-23 | 2012-07-24 | International Business Machines Corporation | Semiconductor-on-insulator (SOI) structure and method of forming the SOI structure using a bulk semiconductor starting wafer |
| US9484432B2 (en) | 2010-12-21 | 2016-11-01 | Intel Corporation | Contact resistance reduction employing germanium overlayer pre-contact metalization |
| US8901537B2 (en) | 2010-12-21 | 2014-12-02 | Intel Corporation | Transistors with high concentration of boron doped germanium |
| CN111986989B (zh) * | 2019-05-23 | 2023-05-26 | 中芯国际集成电路制造(上海)有限公司 | 半导体结构及其形成方法 |
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| US4838991A (en) * | 1987-10-30 | 1989-06-13 | International Business Machines Corporation | Process for defining organic sidewall structures |
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- 2003-03-12 US US10/387,623 patent/US6972228B2/en not_active Expired - Fee Related
- 2003-12-15 EP EP03797023A patent/EP1602126A1/en not_active Withdrawn
- 2003-12-15 CN CNB2003801096425A patent/CN100390936C/zh not_active Expired - Fee Related
- 2003-12-15 WO PCT/US2003/039944 patent/WO2004082002A1/en not_active Application Discontinuation
- 2003-12-15 AU AU2003297950A patent/AU2003297950A1/en not_active Abandoned
- 2003-12-18 TW TW092136016A patent/TWI230418B/zh not_active IP Right Cessation
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| US4999314A (en) * | 1988-04-05 | 1991-03-12 | Thomson-Csf | Method for making an alternation of layers of monocrystalline semiconducting material and layers of insulating material |
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Also Published As
| Publication number | Publication date |
|---|---|
| WO2004082002A1 (en) | 2004-09-23 |
| US6972228B2 (en) | 2005-12-06 |
| CN1748289A (zh) | 2006-03-15 |
| TW200425335A (en) | 2004-11-16 |
| US20040180499A1 (en) | 2004-09-16 |
| AU2003297950A1 (en) | 2004-09-30 |
| TWI230418B (en) | 2005-04-01 |
| EP1602126A1 (en) | 2005-12-07 |
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