CN100390782C - Real-time fast Fourier transform circuit - Google Patents

Abstract

The present invention relates to a fast Fourier transform processor, which discloses a real-time fast Fourier transform circuit and is used for calculating N points of discrete Fourier transform. The present invention comprises a plurality of base 2<4> papilionaceous cells connected by a complex number multiplier; the complex number output by the last level of the base 2<4> papilionaceous cell multiplies the twiddle factor provided by a control cell to obtain a multiplication of complex numbers through the complex number multiplier. Each base 2<4> papilionaceous cell comprises a papilionaceous cell BF1, a papilionaceous cell BF2, a papilionaceous cell BF3 and a papilionaceous cell BF4 which are in serial connection, wherein the input of the papilionaceous cell BF1 is the whole input of the base 2<4> papilionaceous cell and the output of the papilionaceous cell BF4 is the whole output of the base 2<4> papilionaceous cell. The number of the complex number multiplier in the real-time fast Fourier transform circuit is cut down to log 16n-1 and the structure of each papilionaceous cell is simple; controlled by a counter, the present invention has the advantages of small circuit area and little power consumption; the papilionaceous cells BF1, BF2, BF3 and BF4 can be easily realized.

Description

A kind of real-time fast Fourier transform circuit

Technical field

The present invention relates to a kind of FFT (fast fourier transform) processor, have base 2 based on VLSI (large scale integrated circuit) ⁴The fft circuit structure is specifically related to a kind of basic 2 ⁴Real-time fast Fourier transform circuit.

Background technology

FFT is the effective ways that calculate DFT (Discrete Fourier Transform, discrete Fourier transform (DFT)), time-domain signal can be changed into frequency-region signal.Inverse Fourier transform carries out opposite conversion.

To N point sequence x (n), its DFT transfer pair is defined as:

$X\left(k\right)=\underset{n=0}{\overset{N-1}{\mathrm{\&Sigma;}}}x\left(n\right)W_N^{\mathrm{nk}}k=\mathrm{0,1},...,N-1,W_N=e^{-\mathrm{<figure-callout\; id="2"\; label="j"\; filenames="C20051003592500131.png,C20051003592500151.png"\; state="\{\{state\}\}">j</figure-callout>}\frac{2\mathrm{\&pi;}}{N}}---\left(1\right)$

$x\left(n\right)=\frac{1}{N}\underset{k=0}{\overset{N-1}{\mathrm{\&Sigma;}}}X\left(k\right)W_N^{-\mathrm{nk}}n=\mathrm{0,1},...,N-1---\left(2\right)$

Obviously, obtain N point X (k) and need N ²The inferior complex addition of inferior complex multiplication and N (N-1), and realize that Complex multiplication needs twice real add of four real multiplies, realizing once that plural number adds then needs real add twice.When N was very big, its calculated amount was appreciable.

In fact, in the DFT computing, include a large amount of repetitive operations.W _NThe value of the factor has following characteristics:

W ⁰＝1，W ^N/2＝-1，W _N ^N+r＝W _N ^r，W ^N/2+r＝-W ^r。

The key of problem is how to utilize the periodicity and the symmetry of the W factor dexterously, derives a fast algorithm efficiently.This algorithm is proposed in nineteen sixty-five by J.W.Cooley and J.W.Tukey the earliest.(fast Fourier transform FFT) makes the multiplication computation amount of N point DFT by N to the fast fourier transform algorithm that Cooley and Tukey propose ²Inferior reducing to

Log ₂N time.After the algorithm of Cooley-Tukey proposes, new algorithm continues to bring out, generally speaking, the developing direction of Fast Fourier Transform (FFT) has two, one is the algorithm that equals 2 integral number power at N, as 2-base algorithm, basic 4 algorithms, real factor algorithm and SPLIT RADIX ALGORITHM FOR etc., another is the algorithm that N is not equal to 2 integral number power.

Along with the develop rapidly of VLSI (very large scale integrated circuit) (VLSI), how to finish the emphasis that the FFT computing is the signal Processing field always with hardware.Comprise a large amount of complex multiplications and additive operation in the middle of the FFT, and circuit area that multiplier takies and power consumption are very big, how to reduce multiplier, reduce power consumption, raising speed is the Several Key Problems of fft processor design.Based on the repeatability of algorithm and the consideration of resource multiplex, people have proposed the basic calculating unit of a kind of butterfly processing unit as the FFT computing, and this element are used repeatedly finally finish whole FFT computings.

Raising speed, reduce power consumption and reduce Method for Area have a variety ofly, it is pipeline organization that a kind of reasonable method is arranged.The processor of pipeline system is distributed to calculated amount on the continuous butterfly processing unit, so that carry out parallel processing.In essence, stream line operation can make the local result that obtains from the previous stage of processor not having being used to next processing level under the situation about postponing immediately.The processing speed of real-time pipeline processor must be complementary with the acquisition speed that input data rate promptly is used for continued operation.This just means that the pipeline system fft processor must calculate the DFT of N length in N clock period.

E.H.Worl and A.M. are at their article " Pipeline and Parallel-pipeline FFT Processors for VLSIImplementation " (IEEE Trans.Compu., C33 (5): 414-426,1984) described a kind of basic 2 streamline unipaths time-delay feedback (R2SDF) FFT in, this FFT can provide at a high speed and real-time signal Processing.But this design needs log ₂N-1 complex multiplier finished the FFT that a N is ordered, and this means to implement more complicated.

Shousheng He and Mats Torkelsso have announced a kind of basic 2 in their U.S.Patent.No.6098088 ²The pipeline system FFT structure of DIT (decimation in time algorithm).The multiplier that this pipeline organization will be calculated N point FFT to be needed is reduced to log ₄N-1.In addition, Shousheng He and Torkelson M. they article " A new approach topipeline FFT processor " (Parallel Processing Symposim, 1996, Proceedings of IPPS ' 96, The 10 ^ThLnternational, 1996) mention in and use base 2 ³DIF (decimation in frequency) fft algorithm only needs log ₈N-1 complex multiplier.But the structure about this algorithm do not mentioned in this piece article.

R.B. the patent No. of announcing in China in April 4 calendar year 2001 in the shellfish of Hull is that 98813921.9 patent is improved the patent of Shousheng He, has proposed improving one's methods of base 8 and basic 16 algorithms, has reduced the use of multiplier, has reduced power consumption.But because radix is high more, control complicatedly more, this patent does not propose how to reduce the complexity of control and realization.

The patent 20040059766 that Yeh Yeou-Min announced in the U.S. on March 25th, 2004 has been announced a kind of pipeline FFT/IFFT processor of low complex degree.This structure is that the unipath postpones feedback-type base 2 ³FFT, this algorithm is the base 2 and the algorithm of basic 8 combinations, has kept the advantage of basic 8 frameworks, has reduced the use of multiplier, has also kept simple controllers as the base 2, the complexity that has reduced control and realized.But the reduction of this complexity relatively is applicable to the FFT that N is less, the FFT base 2 very big for N ³Algorithm still is not enough.

Illustrated in the United States Patent (USP) 20040059766 how Yeou-Min reduces realization base 2 ³The FFT complexity.On structure, Figure 1A has described the described similar real-time pipeline system FFT with Yeou-Min, and it is used for 64 FFT is N=64.Specifically, the feedback register 1 of input data sequence being passed to 7,32 word lengths of first butterfly unit links up output and the input of butterfly 7.The second butterfly unit 8 and the 3rd dish unit 9 have the feedback register 2 of one 16 word lengths and the feedback register 3 of 8 word lengths respectively.Multiplier 14 will comprise that the first order of butterfly unit 7,8,9 links up with comprising the second level of butterfly unit 10,11,12, and take advantage of data stream with twiddle factor Wi.Butterfly unit 7 and 10,8 and 11,9 is distinguished identical with 12 structure.Butterfly unit 10,11,12 is equipped with feedback register 4,5,6, and they have the capacity of 4,2 and 1 word lengths respectively.Output sequence X (K) comes from the second level output of processor.Be used as isochronous controller and address counter with clock signal 15 synchronous binary counters 13, the address that can be used for twiddle factor produces.

BFI type butterfly shown in Figure 1B comprises two totalizers 16, two subtracters 17 and four MUX 18, and the operation of described MUX is controlled by control signal 19.BFII type butterfly shown in Fig. 1 C is structurally similar with BFI type butterfly, but comprise 2-2 converter 20 and the contrary input of band with door 21.Control signal 22 acts on the contrary input with door 21, and the control signal 19 that acts on MUX 18 also acts on the non-contrary input with door 21, drives converter 20 with the output of door 21.BFIII type butterfly shown in Fig. 1 D structurally with the structural similarity of BFII, but comprise a W8 multiplication unit 22, two contrary inputs of band with door 23 and 24, one or 25.Control signal 22 acts on the contrary input with door 23, control signal 19 and 26 actings in conjunction in the non-contrary input of door 23.Control signal 26 also acts on the contrary input with door 24, and control signal 19 also acts on the non-contrary input with door 24.With the input acting in conjunction of door 23 and 24 in or door 25, or the output 27 control transformation devices 20 of door 25.

Base 2 among Figure 1A ³Single operation that postpones feedback FFT as follows.In cycle, 2 select 1 MUX 18 to be converted to a reset in the first butterfly unit at first N/2, and butterfly is idle.Input data from the left side are reached feedback shift register, are filled until them.In cycle, MUX 18 goes to a set at next N/2, and the butterfly unit is with the data of importing and be stored in 2 DFT of data computation in the shift register.

The output X (n) of butterfly is transferred into the input of next butterfly, and X (n+N/2) is transmitted back to will be at next N/2 shift register of selecting of multichannel in addition in the cycle.

Except the interval of butterfly list entries just realizing that for N/4 and by exchanging the simple rotation factor multiplication, the operation of the operation of second butterfly and first butterfly is similar by converter 20 and controlled reality-void that adds reducing.This just need be from two control signals 19 and 22 of synchronous counter 13.Except the interval of butterfly list entries just is N/8 and by the W8 multiplication unit, the operation of the operation of the 3rd butterfly and second butterfly is similar.These need be from three control signals 19,22 and 26 of synchronous counter 13.Then, data are through a full complex multiplier 14, word for word to form base 2 ³The first order result of FFT.Next step processing procedure repeats this mode at interval by handling a grade input that reduces by half each continuous butterfly.After N-1 clock period, the anti-order of step-by-step is exported whole DFT transformation results X (K).

The WO97/19412 application form of He is thought, base 2 ²It is best that SDF FFT Processing Structure is calculated pipeline system FFT.R.B. 98813921.9 application forms in the shellfish of Hull improve this structure, can only use more a spot of fixed coefficient multiplier to radix greater than 4 FFT.20040059766 application forms of Yeh Yeou-Min have proposed further improvement, allow basic 2 ³Structure becomes and simplifies most.But, all do not have proposition how to reduce the complexity of basic 16 algorithm controls.

Summary of the invention

The present invention proposes a kind of with base 2 ⁴Algorithm is realized the structure of N point FFT/IFFT, and this structure only needs log ₁₆N-1 complex multiplier.

A kind of real-time fast Fourier transform circuit disclosed by the invention is used to calculate N point discrete Fourier conversion DFT, comprises a plurality of bases 2 that connect with complex multiplier ⁴Butterfly unit, described complex multiplier is with described basic 2 of previous stage ⁴The twiddle factor that the plural number of butterfly unit output and control module provide multiplies each other and obtains a multiplication of complex numbers; It is characterized in that described each base 2 ⁴Butterfly unit includes butterfly unit BF1 connected in series, butterfly unit BF2, butterfly unit BF3 and butterfly unit BF4, and described butterfly unit BF1 is input as whole basic 2 ⁴The input of butterfly unit, described butterfly unit BF4 is output as whole basic 2 ⁴The output of butterfly unit.

This real-time fast Fourier transform circuit disclosed by the invention when described N equals at 256, comprises two described basic 2 that connect with a described complex multiplier ⁴The butterfly processing unit, described counter is controlled described real-time fast Fourier transform circuit by clock signal; First are described basic 2 years old ⁴Butterfly unit comprises that described butterfly unit BF1 and feedback connect its output and be connected its output is connected its output and 32 word lengths importing with the register of 64 word lengths of input, described butterfly unit BF3 and feedback register with the register of 128 word lengths of input, described butterfly unit BF2 and feedback with described butterfly unit BF4 and feed back the register that is connected its 16 word lengths exporting and import, second described basic 2 ⁴The unit comprises that described butterfly unit BF1 and feedback connect its output and be connected its output is connected its output and 2 word lengths importing with the register of 4 word lengths of input, described butterfly unit BF3 and feedback register with the register of 8 word lengths of input, described butterfly unit BF2 and feedback with described butterfly unit BF4 and feed back the register that is connected its 1 word length exporting and import.

FFT structure of the present invention is made up of butterfly unit 1, butterfly unit 2, butterfly unit 3 and butterfly unit 4 these four butterfly circuits.The structure of each butterfly unit is all fairly simple, controls the work of entire circuit by a counter, so simple in structure, circuit area is less, power consumption is also less.

Advantage of the present invention is to form base 2 ⁴Butterfly unit BF1, BF2, BF3 and the BF4 of butterfly unit is easy to realize.The second, the present invention drops to log with the number of complex multiplier ₁₆N-1.

Description of drawings

Figure 1A is 64 bases 2 ³The unipath postpones feedback (SDF) pipeline FFT processor structure;

Figure 1B is the base 2 shown in Figure 1A ³The circuit diagram of the BFI that uses in the SDF pipeline FFT processor;

Fig. 1 C is the base 2 shown in Figure 1A ³The circuit diagram of the BFII that uses in the SDF pipeline FFT processor;

Fig. 1 D is the base 2 shown in Figure 1A ³The circuit diagram of the BFII that uses in the SDF pipeline FFT processor;

Fig. 2 is a base 2 ⁴The signal flow graph of butterfly unit;

Fig. 3 A is according to 256 bases 2 of the invention process ⁴The structural drawing of SDF pipeline FFT processor;

Fig. 3 B is 256 bases 2 shown in Fig. 3 A ⁴The circuit diagram of the BF1 that uses in the SDF pipeline FFT processor;

Fig. 3 C is 256 bases 2 shown in Fig. 3 A ⁴The circuit diagram of the BF2 that uses in the SDF pipeline FFT processor;

Fig. 3 D is 256 bases 2 shown in Fig. 3 A ⁴The circuit diagram of the BF3 that uses in the SDF pipeline FFT processor;

Fig. 3 E is 256 bases 2 shown in Fig. 3 A ⁴The circuit diagram of the BF4 that uses in the SDF pipeline FFT processor;

Fig. 4 A is-circuit diagram of j multiplier;

Fig. 4 B is

The circuit diagram of multiplier;

Fig. 4 C is The circuit diagram of multiplier;

Fig. 4 D is The circuit diagram of multiplier;

Fig. 5 is according to 4096 bases 2 of the invention process ⁴The structural drawing of SDF pipeline FFT processor;

Embodiment

In the following description, comprised the ins and outs that some are specific, such as certain embodiments, technology, hardware circuit, device etc., this be for clearer, all sidedly the present invention is described, rather than limit range of application of the present invention.For example, the present invention uses and 4096 FFT as embodiment at 256.But these embodiment and structure only are exemplary, the expert of present technique as can be seen, other embodiment that does not break away from these specific detail can realize the present invention equally.In other cases, omitted detailed description, hindered explanation of the present invention to avoid too much details to known DFT/FFT method, device and technology.

Fig. 2 is a base 2 ⁴The signal flow graph of processing unit, the twiddle factor that need use has W ₁₆ ¹, W ₁₆ ², W ₁₆ ³, W ₁₆ ⁴, W ₁₆ ⁵, W ₁₆ ⁶And W ₁₆ ⁷

Wherein ${\mathrm{<figure-callout\; id="16"\; label="W"\; filenames="C20051003592500131.png,C20051003592500132.png"\; state="\{\{state\}\}">W</figure-callout>}}_{16}^1=\cos \left(\frac{\mathrm{\&pi;}}{8}\right)-j\sin \left(\frac{\mathrm{\&pi;}}{8}\right),$ ${\mathrm{<figure-callout\; id="16"\; label="W"\; filenames="C20051003592500131.png,C20051003592500132.png"\; state="\{\{state\}\}">W</figure-callout>}}_{16}^2=\cos \left(\frac{\mathrm{\&pi;}}{4}\right)-j\sin \left(\frac{\mathrm{\&pi;}}{4}\right),$

${\mathrm{<figure-callout\; id="16"\; label="W"\; filenames="C20051003592500131.png,C20051003592500132.png"\; state="\{\{state\}\}">W</figure-callout>}}_{16}^3=\cos \left(\frac{3\mathrm{\&pi;}}{8}\right)-j\sin \left(\frac{3\mathrm{\&pi;}}{8}\right),$ ${\mathrm{<figure-callout\; id="16"\; label="W"\; filenames="C20051003592500131.png,C20051003592500132.png"\; state="\{\{state\}\}">W</figure-callout>}}_{16}^4=\cos \left(\frac{\mathrm{\&pi;}}{2}\right)-j\sin \left(\frac{\mathrm{\&pi;}}{2}\right),$

${\mathrm{<figure-callout\; id="16"\; label="W"\; filenames="C20051003592500131.png,C20051003592500132.png"\; state="\{\{state\}\}">W</figure-callout>}}_{16}^5=\cos \left(\frac{5\mathrm{\&pi;}}{8}\right)-j\sin \left(\frac{5\mathrm{\&pi;}}{8}\right),$ ${\mathrm{<figure-callout\; id="16"\; label="W"\; filenames="C20051003592500131.png,C20051003592500132.png"\; state="\{\{state\}\}">W</figure-callout>}}_{16}^6=\cos \left(\frac{3\mathrm{\&pi;}}{4}\right)-j\sin \left(\frac{3\mathrm{\&pi;}}{4}\right),$

${\mathrm{<figure-callout\; id="16"\; label="W"\; filenames="C20051003592500131.png,C20051003592500132.png"\; state="\{\{state\}\}">W</figure-callout>}}_{16}^7=\cos \left(\frac{7\mathrm{\&pi;}}{8}\right)-j\sin \left(\frac{7\mathrm{\&pi;}}{8}\right).$

In order to reduce the use of complex multiplier, must find out rule from top twiddle factor, making it can abbreviation be that common logical operation just can be finished complex multiplication operation.Wherein, the easiest abbreviation be ${\mathrm{<figure-callout\; id="16"\; label="W"\; filenames="C20051003592500131.png,C20051003592500132.png"\; state="\{\{state\}\}">W</figure-callout>}}_{16}^4=-j.$

$(X+\mathrm{jY})*{\mathrm{<figure-callout\; id="16"\; label="W"\; filenames="C20051003592500131.png,C20051003592500132.png"\; state="\{\{state\}\}">W</figure-callout>}}_{16}^4=-j(X+\mathrm{jY})=Y-\mathrm{jX},$ Can finish this complex multiplication operation with the circuit shown in Fig. 4 A.

Secondly easily that abbreviation is W ₁₆ ²And W ₁₆ ⁶, ${\mathrm{<figure-callout\; id="16"\; label="W"\; filenames="C20051003592500131.png,C20051003592500132.png"\; state="\{\{state\}\}">W</figure-callout>}}_{16}^2=\cos \left(\frac{\mathrm{\&pi;}}{4}\right)-j\sin \left(\frac{\mathrm{\&pi;}}{4}\right)=\frac{\sqrt{2}}{2}-\frac{\sqrt{2}}{2}j$

${\mathrm{<figure-callout\; id="16"\; label="W"\; filenames="C20051003592500131.png,C20051003592500132.png"\; state="\{\{state\}\}">W</figure-callout>}}_{16}^6=\cos \left(\frac{3\mathrm{\&pi;}}{4}\right)-j\sin \left(\frac{3\mathrm{\&pi;}}{4}\right)=-\frac{\sqrt{2}}{2}+\frac{\sqrt{2}}{2}j=-\mathrm{<figure-callout\; id="16"\; label="j\; W"\; filenames="C20051003592500131.png,C20051003592500132.png"\; state="\{\{state\}\}">j</figure-callout>}{W}_{}^{}{}_{16}^2,$ So as long as with W ₁₆ ²Abbreviation, W ₁₆ ⁶Also along with can abbreviation.

$\frac{\sqrt{2}}{2}=0.7071068=2^{-1}+2^{-3}+2^{-4}+2^{-6}+2^{-8}+2^{-9}$

$(X+\mathrm{jY})*W_{16}^2=(X+\mathrm{jY})*(\frac{\sqrt{2}}{2}-\frac{\sqrt{2}}{2}j)=\frac{\sqrt{2}}{2}[(X+Y)+j(Y-X)]$

$=(2^{-1}+2^{-3}+2^{-4}+{2^{-6}+2}^{-8}+2^{-9})(X+Y)+j(2^{-1}+2^{-3}+2^{-4}+2^{-6}+2^{-8}+2^{-9})(Y+X)$

Can realize with the circuit shown in Fig. 4 B.

${\mathrm{<figure-callout\; id="16"\; label="W"\; filenames="C20051003592500131.png,C20051003592500132.png"\; state="\{\{state\}\}">W</figure-callout>}}_{16}^5=\cos \left(\frac{5\mathrm{\&pi;}}{8}\right)-j\sin \left(\frac{5\mathrm{\&pi;}}{8}\right)=\sin (\frac{\mathrm{\&pi;}}{2}-\frac{5\mathrm{\&pi;}}{8})-j\cos (\frac{\mathrm{\&pi;}}{2}-\frac{5\mathrm{\&pi;}}{8})$

$=-\sin \left(\frac{\mathrm{\&pi;}}{8}\right)-j\cos \left(\frac{\mathrm{\&pi;}}{8}\right)=-\mathrm{<figure-callout\; id="16"\; label="j\; W"\; filenames="C20051003592500131.png,C20051003592500132.png"\; state="\{\{state\}\}">j</figure-callout>}{W}_{}^{}{}_{16}^1$

${\mathrm{<figure-callout\; id="16"\; label="W"\; filenames="C20051003592500131.png,C20051003592500132.png"\; state="\{\{state\}\}">W</figure-callout>}}_{16}^7=\cos \left(\frac{7\mathrm{\&pi;}}{8}\right)-j\sin \left(\frac{7\mathrm{\&pi;}}{8}\right)=\sin (\frac{\mathrm{\&pi;}}{2}-\frac{7\mathrm{\&pi;}}{8})-j\cos (\frac{\mathrm{\&pi;}}{2}-\left(\frac{7\mathrm{\&pi;}}{8}\right))$

$=-\sin \left(\frac{3\mathrm{\&pi;}}{8}\right)-\cos \left(\frac{3\mathrm{\&pi;}}{8}\right)=-\mathrm{<figure-callout\; id="16"\; label="j\; W"\; filenames="C20051003592500131.png,C20051003592500132.png"\; state="\{\{state\}\}">j</figure-callout>}{W}_{}^{}{}_{16}^3$

W like this ₁₆ ⁵And W ₁₆ ⁷Just can use W ₁₆ ¹And W ₁₆ ³Represent, though W ₁₆ ¹And W ₁₆ ³Between do not have direct multiple relation, but they all and

With

Relation is arranged.

$\sin \left(\frac{\mathrm{\&pi;}}{8}\right)=0.382683432=2^{-2}+2^{-3}+2^{-8}+2^{-9}+2^{-10}+2^{-11}$

$\cos \left(\frac{\mathrm{\&pi;}}{8}\right)=0.923879533=2^{-1}+2^{-2}+2^{-3}+2^{-5}+2^{-6}+2^{-9}$

So this multiplication can be realized with the circuit shown in Fig. 4 C and Fig. 4 D.

Fig. 3 A is for using the example of 256 fft processors of the present invention.Specifically, this practical circuit is by two bases 2 ⁴Butterfly unit is formed, and the centre couples together them with a complex multiplier.Each base 2 ⁴The unit all is made up of four registers group and four base 2 butterfly units, wherein first base 2 ⁴Four registers group 100,101,102 and 103 capacity are respectively 128,64,32 and 16 word lengths in the unit, and four base 2 butterfly units 108,109,110 and 111 are respectively BF1-1, BF2-1, BF3-1 and BF4-1.Second base 2 ⁴Four registers group 104,105,106 and 107 capacity are respectively 8,4,2 and 1 word lengths in the unit, and four base 2 butterfly units 112,113,114 and 115 are respectively BF1-2, BF2-2, BF3-2 and BF4-2.

Specifically, the feedback register 100 of at first input data sequence x (n) being passed to 108,128 word lengths of first butterfly unit links up output and the input of butterfly 108.Equally, the input and output of the second butterfly unit 109, the 3rd dish unit 110 and the 4th butterfly unit 111 are fed register 101,102 and 103 respectively and link up.Multiplier 117 will comprise that the first order of butterfly unit 108,109,110 and 111 links up with comprising the second level of butterfly unit 112,113,114 and 115, and take advantage of data stream with twiddle factor Wi.Butterfly unit 108 and 112,109 and 113,110 and 114,111 is distinguished identical with 115 structure.Butterfly unit 112,113,114 and 115 is equipped with feedback register 104,105,106 and 107, and the contact relation between them is identical with the first order.Output sequence X (K) comes from the second level output of processor.Be used as isochronous controller and address counter with clock signal 118 synchronous binary counters 116, the address that can be used for twiddle factor produces.

BF1 type butterfly shown in Fig. 3 B comprises two totalizers 120, two subtracters 121 and four MUX 122, and the operation of described MUX is controlled by control signal 123.To the BF1-1 of the first order, the 7th of control signal 123 sum counters 116 links to each other, and to partial BF1-2, the 3rd of control signal 123 sum counters 116 links to each other.

BF2 type butterfly shown in Fig. 3 C is structurally similar with BF1 type butterfly, comprises two totalizers 124, two subtracters 125, subtracter 130, four MUX 127, two MUX 131, not gate 129 and one and door 128.Control signal 132 acts on the input of not gate 129, and control signal 127 acts on and door 128 input, the output action of not gate 129 in the input of door 128, with the output action of door 128 in MUX 131.One end of subtracter 130 fixedly is connected on the level "0".To the BF2-1 of the first order, control signal 127, control signal 132 link to each other with the 6th, the 7th of counter 116 respectively, and to partial BF2-2, control signal 127, control signal 132 link to each other with the 2nd, the 3rd of counter 116 respectively.

BF3 type butterfly shown in Fig. 3 D is similar with BF2 structurally, comprise two totalizers 140, two subtracters 141, four MUX 142, MUX 144,145, two MUX of subtracter 146, two

Multiplication unit 147, totalizer 148, subtracter 149, three not gates, one or, two input and door and two three inputs and door.Control signal 143 acts on MUX 142, with the output action of door 153 in MUX 144, or the output action of door 152 is in MUX 146.To first order BF3-1, control signal 151,150 links to each other with the 5th with the 7th, the 6th of counter 116 respectively with 143.To second level BF3-2, control signal 151,150 links to each other with the 1st with the 3rd, the 2nd of counter 116 respectively with 143.Shown in Fig. 4 B be

The physical circuit of multiplication unit 147.

BF4 type butterfly shown in Fig. 3 E is similar with BF3 structurally, but comprise a totalizer 174, subtracter 175, two MUX 173, select 2 selector switchs 176, two for two 2

Multiplier 178, two

Multiplier 177, XOR gate, two four inputs and door, three input and door, not gate and two or.Or door 179 output action is in MUX 173, selects 2 selector switchs 176 with the output action of door 180 in 2.2 select the working mechanism of 2 selector switchs 176 to be: when the control signal when 176 was 1, an end of totalizer 174 connected 178, and the other end connects 177, and an end of subtracter 175 connects 188, one ends and connects 187; When 176 control signals were 0, an end of totalizer 174 connected 187, and the other end connects 188, and an end of subtracter 175 connects 177, one ends and connects 178.To first order BF4, control signal 163,164,165 links to each other with the 7th respectively at the 4th, the 5th, the 6th of counter 116 with 166, to second level BF4, control signal 163,164,165 links to each other with the 3rd respectively at the 0th, the 1st, the 2nd of counter 116 with 166.

Multiplier and

The circuit of multiplier is shown in Fig. 4 C.

Base 2 among Fig. 3 A ⁴Single operation that postpones feedback FFT as follows.In cycle, 2 select 1 MUX 122 to be converted to a reset among the BF1 at first N/2, are reached feedback shift register 100 from the input data on the left side, are filled until them.In cycle, MUX 122 goes to a set at next N/2, and BF1 is with the data of importing and be stored in 2 DFT of data computation in the shift register.

X(n)＝x(n)+x(n+N/2) 0≤n＜N/2

X(n+N/2)＝x(n)-x(n+N/2)

The output X (n) of butterfly is transferred into the input of next butterfly, and X (n+N/2) is transmitted back to will be at next N/2 shift register of selecting of multichannel in addition in the cycle.

To 3N/4 between the cycle, MUX 126 is converted to a reset among the BF2 at first N/2, is reached feedback shift register 101 from the input data of BF1, is filled until them.In cycle, MUX goes to a set at next N/4, and BF2 is with the data of importing and be stored in 2 DFT of data computation in the shift register.In cycle, MUX 131 goes to a reset at this N/4, and in the ensuing N/4 cycle, MUX 131 goes to a set, will import data and multiply by-j, then with 2 DFT of data computation that are stored in the shift register.The output X (n) of butterfly is transferred into the input of next butterfly, and X (n+N/4) is transmitted back to will be at next N/4 shift register of selecting of multichannel in addition in the cycle.

To 7N/8 between the cycle, MUX 142 is converted to a reset among the BF3 at first 3N/4, is reached feedback shift register 102 from the input data of BF2, is filled until them.In cycle, MUX 142 goes to a set at next N/8, and BF2 is with the data of importing and be stored in 2 DFT of data computation in the shift register.In cycle, MUX 144 goes to a reset at this N/8, and in an ensuing N/4 cycle, back N/8 cycle MUX 144 goes to a set, will import data and multiply by-j, then with 2 DFT of data computation that are stored in the shift register.During 11N/8 arrived 12N/8 week, MUX 144 went to a reset, and MUX 146 goes to a set, will import data and multiply by W ₁₆ ², then with 2 DFT of data computation that are stored in the shift register.

First 7N/8 to 15N/16 between the cycle among the BF4 MUX 162 go to a reset, reached feedback shift register 103 from the input data of BF3, be filled until them.In the 17N/16 cycle, MUX 167 goes to a set, and data be multiply by W ₁₆ ⁴In the 19N/16 cycle, MUX 169 goes to a set, and data be multiply by W ₁₆ ²In the 21N/16 cycle, MUX 173 goes to a set, and 2 select 2 selector switchs to go to a reset, and data be multiply by W ₁₆ ⁶, then with 2 DFT of data computation that are stored in the shift register.

The first order described above need be controlled fairly simple from circuit from four control signals of synchronous counter 116 as can be seen.Then, data are through a full complex multiplier 117, word for word to form base 2 ⁴The first order result of FFT.Next step processing procedure repeats this mode at interval by handling a grade input that reduces by half each continuous butterfly.After N-1 clock period, the anti-order of step-by-step is exported whole DFT transformation results X (K).Then, the next frame to conversion under situation about not suspending is handled, because the processing of pipeline system is all arranged at the places at different levels of processor.

Fig. 5 is for using the example of 4096 fft processors of the present invention.Specifically, this practical circuit is by three bases 2 ⁴The butterfly processing unit is formed, and the centre couples together them with two complex multipliers.Each base 2 ⁴The unit all is made up of four registers group and four base 2 butterfly units, wherein first base 2 ⁴Four registers group 200,201,202 and 203 capacity are respectively 2048,1024,512 and 256 word lengths in the unit, and four base 2 butterfly units 212,213,214 and 215 are respectively BF1-1, BF2-1, BF3-1 and BF4-1.Second base 2 ⁴Four registers group 204,205,206 and 207 capacity are respectively 128,64,32 and 16 word lengths in the unit, and four base 2 butterfly units 216,217,218 and 219 are respectively BF1-2, BF2-2, BF3-2 and BF4-2.The 3rd base 2 ⁴Four registers group 208,209,210 and 211 capacity are respectively 8,4,2 and 1 word lengths in the unit, and four base 2 butterfly units 220,221,222 and 223 are respectively BF1-3, BF2-3, BF3-3 and BF4-3.

Compared with former method, the invention provides a kind of base of forming by BF1, BF2, BF3 and BF4 unit 2 ⁴Butterfly Processing Structure, its output comprise a BF1 unit at least, with a complex multiplier each grade connection are got up.BF2 comprises one

Multiple twiddle factor, BF3 comprises one simultaneously

With

Multiple twiddle factor, BF4 comprises one simultaneously

With

Multiple twiddle factor.All BF1, BF2, BF3 and BF4 unit are all controlled by a flowing water counter, and the flowing water counter is also controlled the generation of twiddle factor in the complex multiplier.

The method that the present invention introduced can realize easily, and can revise to satisfy the count demand of FFT of difference, is not limited in the object lesson in the above-mentioned explanation.

Claims (9)

1. a real-time fast Fourier transform circuit is used to calculate N point discrete Fourier conversion DFT, comprises a plurality of bases 2 that connect with complex multiplier ⁴Butterfly unit, described complex multiplier is with described basic 2 of previous stage ⁴The twiddle factor that the plural number of butterfly unit output and control module provide multiplies each other and obtains a multiplication of complex numbers; It is characterized in that described each base 2 ⁴Butterfly unit includes butterfly unit BF1 connected in series, butterfly unit BF2, butterfly unit BF3 and butterfly unit BF4, and described butterfly unit BF1 is input as whole basic 2 ⁴The input of butterfly unit, described butterfly unit BF4 is output as whole basic 2 ⁴The output of butterfly unit.

2. a kind of real-time fast Fourier transform circuit according to claim 1 is characterized in that, described butterfly unit BF1, BF2, BF3 and BF4 are by a counter controls.

3. a kind of real-time fast Fourier transform circuit according to claim 2 is characterized in that described counter is also controlled the generation of twiddle factor in the described complex multiplier.

4. a kind of real-time fast Fourier transform circuit according to claim 1 is characterized in that, described butterfly unit BF2 comprises one

Multiple twiddle factor; Described butterfly unit BF3 comprises one simultaneously

Multiple twiddle factor and one

Multiple twiddle factor; Described butterfly unit BF4 comprises one simultaneously

Multiple twiddle factor, one

Multiple twiddle factor and one

Multiple twiddle factor.

5. a kind of real-time fast Fourier transform circuit according to claim 1 is characterized in that, described N equals 256 points, and described real-time fast Fourier transform circuit comprises two described basic 2 that connect with a described complex multiplier (117) ⁴Butterfly unit, counter (116) is controlled described real-time fast Fourier transform circuit by clock signal (118); First are described basic 2 years old ⁴Butterfly unit comprises that described butterfly unit BF1 (108) and feedback connect its output and be connected its output is connected its output and 32 word lengths importing with register (101), described butterfly unit BF3 (110) and the feedback of 64 word lengths of input register (102) with register (100), described butterfly unit BF2 (109) and the feedback of 128 word lengths of input with described butterfly unit BF4 (111) and feed back the register (103) that is connected its 16 word lengths exporting and import, second described basic 2 ⁴The unit comprises that described butterfly unit BF1 (112) and feedback connect its output and be connected its output is connected its output and 2 word lengths importing with register (105), described butterfly unit BF3 (114) and the feedback of 4 word lengths of input register (106) with register (104), described butterfly unit BF2 (113) and the feedback of 8 word lengths of input with described butterfly unit BF4 (115) and feed back the register (107) that is connected its 1 word length exporting and import.

6. a kind of real-time fast Fourier transform circuit according to claim 5, it is characterized in that, described butterfly unit BF1 is with the data of input and be stored in 2 DFT of data computation in the shift register, comprise two totalizers (120), two subtracters (121) and four MUX (122), the operation of described MUX is controlled by the 7th or the 3rd control signal s from described counter (116).

7. a kind of real-time fast Fourier transform circuit according to claim 6, it is characterized in that, described butterfly unit BF2 is structurally similar with described butterfly unit BF1, comprises also that at the circuit structure front end identical with described butterfly unit BF1 one one end fixedly is connected on subtracter (130), two MUX (131), a not gate (129) and and the door (128) on the level "0"; Control signal m from the 6th of described counter (116) or the 2nd imports and door (128) with described control signal s jointly by described not gate (129), with the output action of door (128) in MUX (131).

8. a kind of real-time fast Fourier transform circuit according to claim 7, it is characterized in that, described butterfly unit BF3 is structurally similar with described butterfly unit BF2, comprises also that at the circuit structure front end identical with described butterfly unit BF2 output is respectively through two

A totalizer (148) of multiplication unit (147) and a subtracter (149), and corresponding two MUX (146) that connect, two not gates, one or and two three inputs and door; Jointly import first described three inputs and door by first described not gate with described control signal s, described control signal m from the 5th of described counter (116) or the 1st control signal h, described control signal m imports second described three input and door by second described not gate jointly with described control signal h, described control signal s, the output of two described three inputs and door by described or (152) act on MUX (146).

9. a kind of real-time fast Fourier transform circuit according to claim 8 is characterized in that, described butterfly unit BF4 is structurally similar with described butterfly unit BF3, also comprises two at the circuit structure front end identical with described butterfly unit BF3 Multiplier (178) and (188), two

Multiplier (177) and (187), select 2 selector switchs (176), a totalizer (174), a subtracter (175), two MUX (173) for two 2, and XOR gate, two four inputs and door, three input and door (180), not gate and two or; And:

Jointly import first described four inputs and door by first described not gate with described control signal s, described control signal m and described control signal h from the 4th of described counter (116) or the 0th control signal d, described control signal m and described control signal h import second described four input and door with described control signal s and described control signal d behind the door jointly by non-;

Described control signal m and described control signal h by described XOR gate after with described control signal s, control signal d import jointly described three the input with the door (180); The output action of described three inputs and door (180) selects 2 selector switchs (176) in 2;

Two described four inputs with the output of door by described first or behind the door, import described jointly or (179) with described three inputs with the output of door (180), the described or output action of (179) is in MUX (173).

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