CN100389490C - Flattening method of flas storage device - Google Patents
Flattening method of flas storage device Download PDFInfo
- Publication number
- CN100389490C CN100389490C CNB021422613A CN02142261A CN100389490C CN 100389490 C CN100389490 C CN 100389490C CN B021422613 A CNB021422613 A CN B021422613A CN 02142261 A CN02142261 A CN 02142261A CN 100389490 C CN100389490 C CN 100389490C
- Authority
- CN
- China
- Prior art keywords
- layer
- memory device
- oxide layer
- flush memory
- flattening method
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Expired - Fee Related
Links
Images
Abstract
The present invention relates to a flattening method of a flash storage device. A tunnel penetrating oxidization layer is firstly formed on a substrate, and then, the tunnel penetrating oxidization layer forms a floating grid electrode; a top cover layer is formed on the floating grid electrode, wherein the tunnel penetrating oxidization layer, the floating grid electrode and the top cover layer form a stack structure. Then, if the top cover layer is a nitride layer, the stack structure needs to be firstly deposited with an oxidization layer, and the high-density plasma phosphorosilicate glass is formed on the substrate. If the top cover layer is an oxidization layer, a high-density plasma nitride layer is directly formed on the substrate to cover the stack structure. Subsequently, a part of high-density plasma layer is removed to be exposed out of the top edge of the top cover layer; finally, the top cover layer is removed, and a part of deposition layer on the top cover layer can be simultaneously removed.
Description
Technical field
The present invention is the manufacture craft of relevant a kind of flush memory device (FLASH memory device), and particularly relevant for a kind of flattening method of flush memory device.
Background technology
It is to exempt from cmp (chemical mechanical polishing that the present smooth flattening method of flush memory device has a kind of, abbreviation CMP) flattening method of manufacture craft, its manufacture craft is to form one deck tunnel oxide (tunneling oxidelayer) in substrate earlier mostly, on tunnel oxide, form a floating boom utmost point (floating gate) again, and extremely go up formation one deck nitration case (nitride layer) in floating boom.Then, in substrate, form one deck high-density plasma (high density plasma is called for short HDP) oxide layer (oxide layer) and remove to cover above-mentioned device.Then, remove part high-density plasma oxide layer, with the top margin (top edge) that exposes nitration case.Subsequently, remove nitration case, and remove the part high-density plasma oxide layer that is positioned on the nitration case simultaneously.
Yet, known technology is when forming the high-density plasma oxide layer, because adopt the high-density plasma manufacture craft of anisotropic deposition manufacture craft (anisotropic deposition), therefore can cause the defective shown in Figure 1A to take place, can cause the problem of flush memory device generating device fault shown in Figure 1B what is more.
Figure 1A to Figure 1B is the manufacturing process profile of known a kind of flush memory device.
Please refer to Figure 1A and Figure 1B, formed the structure that comprises the tunnel oxide 102 and the floating boom utmost point 104 in substrate 100.And in substrate 100, form one deck high-density plasma oxide layer 106 according to above-mentioned known technology.Yet, because adopt anisotropic deposition manufacture craft to form this floor height density plasma oxide layer 106, so can produce breach (breach) 120 near the peripheral flush memory device of wafer (wafer), in follow-up manufacture craft flow process, pass through behind the Wet-type etching even can form and run through the opening 130 of putting in order floor height density plasma oxide layer 106.Thereby cause shown in Figure 1B, after forming gate dielectric layer 108 and larger area control grid (control gate) 110 successively, because of wherein control grid 110 contacts with substrate 100, and the problem of be short-circuited (short).In addition, known employing high-density plasma oxide layer 1 06 is as dielectric layer usefulness, thus there are moving iron (mobile ion) or impurity (impurity) to exist easily, and then reduce the reliability (reliability) of device.
In addition, above-mentioned known technology also has other shortcoming, such as flush memory device tends to because adopt high-density plasma oxide layer 106 as dielectric layer usefulness, and has fast the problem of erase (fast-erase) to take place when operating at the initial stage of carrying out.At present for solving the above-mentioned shortcoming of erasing fast, normally in the operation of shipment (delivery) preceding advanced line number secondary programization/erase (program/erase), yet this causes shortcoming consuming time again.
Summary of the invention
Therefore, purpose of the present invention is providing a kind of flattening method of flush memory device, produces breach to avoid flush memory device, or even forms the opening that runs through whole floor height density plasma oxide layer.
A further object of the present invention is in that a kind of flattening method of flush memory device is provided, with the problem of avoiding being short-circuited.
Another object of the present invention is providing a kind of flattening method of flush memory device, to prevent existing of moving iron or impurity.
Another purpose of the present invention is providing a kind of flattening method of flush memory device, promotes the reliability of device.
Another purpose of the present invention is providing a kind of flattening method of flush memory device, takes place with the problem of avoiding erasing fast.
Another purpose of the present invention is providing a kind of flattening method of flush memory device, to save the operating time of shipment forward stroke prefaceization/erase.
According to above-mentioned and other purpose, the present invention proposes a kind of flattening method of flush memory device, be included in and form one deck tunnel oxide in the substrate earlier, on tunnel oxide, form a floating boom utmost point again, and in the extremely last one deck cap layer (capping layer) that forms of floating boom, wherein tunnel oxide, the floating boom utmost point and cap layer are formed a stack architecture (stacked structure).Then, deposition one oxide layer on stack architecture forms one deck high intensity plasma glass (HDP phosphosilicate glass is called for short HDP PSG), again to cover stack architecture in substrate.Then, remove (dip) part high intensity plasma glass and oxide layer, to expose the top margin of cap layer.Subsequently, remove cap layer, the part high intensity plasma glass and the partial oxidation layer that wherein are positioned on the cap layer also will be removed simultaneously.
The present invention proposes a kind of flattening method of flush memory device in addition, be included in and form one deck tunnel oxide in the substrate, form a floating boom utmost point again on tunnel oxide, and extremely go up formation one oxide layer in floating boom, wherein tunnel oxide, the floating boom utmost point and oxide layer are formed a stack architecture.Then, in substrate, form a high-density plasma nitration case, to cover stack architecture.Then, remove part high-density plasma nitration case, to expose the top margin of oxide layer.At last, remove oxide layer, and the part high-density plasma nitration case that is positioned on the oxide layer can be removed simultaneously also.
The present invention avoids flush memory device to produce breach by being formed at the layer of oxide layer that covers stack architecture in the substrate, or even forms the opening that runs through whole floor height density plasma oxide layer.And the protection of the oxide layer by this floor height density also can be avoided substrate because of coming out, and form the problem that is short-circuited behind the control grid.Simultaneously, because the present invention adopts high intensity plasma glass as dielectric layer usefulness, thus can prevent the existence of moving iron or impurity, and then promote the reliability of device.
In addition, the present invention comprises that also to adopt the high-density plasma nitration case to replace known with the usefulness of oxide layer as dielectric layer, so can prevent the problem generation of erasing fast, also just can save the operating time of shipment forward stroke prefaceization/erase.
For above and other objects of the present invention, feature and advantage can be become apparent, a preferred embodiment cited below particularly, and cooperate appended graphicly, elaborate.
Description of drawings
Figure 1A to Figure 1B is the manufacturing process profile of known a kind of flush memory device;
Fig. 2 A to Fig. 2 E is the planarization manufacturing flow chart according to the flush memory device of one first embodiment of the present invention;
Fig. 3 A to Fig. 3 D is the planarization manufacturing flow chart according to the flush memory device of one second embodiment of the present invention.
Label declaration:
100,200,300: substrate
102,202,302: tunnel oxide
104,204,304: the floating boom utmost point
106: the high-density plasma oxide layer
108: gate dielectric layer 110: the control grid
120: breach 130: opening
206: cap layer 208,308: stack architecture
210,210a, 210b, 306: oxide layer
212,21 2a, 212b: high intensity plasma glass
312,3 12a, 312b: high-density plasma nitration case
Embodiment
First embodiment
Fig. 2 A to Fig. 2 E is the planarization manufacturing flow chart of the flush memory device (FLASHmemory device) according to one first embodiment of the present invention.
Please refer to Fig. 2 A, in substrate 200, form one deck tunnel oxide 202 earlier, forming one deck material again on tunnel oxide 202 is the floating boom utmost point 204 of polysilicon, and formation one deck is the cap layer (capping layer) 206 of nitration case for example on the floating boom utmost point 204, and wherein tunnel oxide 202, the floating boom utmost point 204 and cap layer 206 are formed stack architectures (stackedstructure) 208.
Then, please refer to Fig. 2 B, deposition layer of oxide layer 210 in substrate 200, and cover above-mentioned stack architecture 208, come out after the subsequent etch manufacture craft to avoid substrate 200, wherein about 200 dusts of the thickness of oxide layer 210.Afterwards, can also implement a temper (annealing treatment), with densification oxide layer 210, whereby to promote the anti-etching ability (etch-resistant capability) of oxide layer 210.
Then, please refer to Fig. 2 C, in substrate 200, form one deck high-density plasma (highdensity plasma, be called for short HDP) phosphorosilicate glass (phosphosilicate glass, be called for short PSG) 212, to cover stack architecture 208, wherein the thickness of high intensity plasma glass 212 is thick and thin than stack architecture 208 than the floating boom utmost point 204, and its thickness is between 1500 dust to 3000 dusts.Owing to adopt high intensity plasma glass 212 as dielectric layer usefulness,, and then promote reliability (reliability) so the present invention can avoid moving iron (mobile ion) or impurity (impurity).
Then, please refer to Fig. 2 D, remove (dip) part high intensity plasma glass 212 and oxide layer 210, up to the top margin that exposes cap layer 206 (top edge), so that high intensity plasma glass 212 and oxide layer 210 are divided into high intensity plasma glass 212a and the oxide layer 210a of position above cap layer 206, and the position is in two parts of the high intensity plasma glass 212b and the oxide layer 210b of 204 of the floating boom utmost points, wherein the method for Qu Chuing for example is with hydrofluoric acid (HF) solution or buffer silicon oxide etching (bufferedoxide etch is called for short BOE) solution removal.
Afterwards, please refer to Fig. 2 E, remove cap layer 206, the high intensity plasma glass 212a and the oxide layer 210a that are positioned at cap layer 206 tops simultaneously also will be removed, and stay high intensity plasma glass 212b and the oxide layer 210b of position 204 of the floating boom utmost points, wherein the method for Qu Chuing is with hot phosphoric acid (hot H for example
3PO
4) solution removal.
Second embodiment
Fig. 3 A to Fig. 3 D is the planarization manufacturing flow chart according to the flush memory device of one second embodiment of the present invention.
Please refer to Fig. 3 A, form one deck tunnel oxide 302 in substrate 300, its thickness is between 70 dust to 100 dusts.Forming a material again on tunnel oxide 302 is the floating boom utmost point 304 of polysilicon, about 1000 dusts of its thickness.Then, on the floating boom utmost point 304, form an oxide layer 306, about 2000 dusts of its thickness.Wherein tunnel oxide 302, the floating boom utmost point 304 and oxide layer 306 are formed a stack architecture 308.
Then, please refer to Fig. 3 B, in substrate 300, form a high-density plasma nitration case (HDP nitride layer) 312, to cover stack architecture 308, wherein the thickness of high-density plasma nitration case 312 is thick and thin than stack architecture 308 than the floating boom utmost point 304, and its thickness is between 1500 dust to 3000 dusts.Because it is known with the usefulness of oxide layer as dielectric layer that the present invention adopts high-density plasma nitration case 312 to replace, so the problem generation of can prevent to erase fast (fast-erase).
Then, please refer to Fig. 3 C, remove part high-density plasma nitration case 312, up to the top margin that exposes cap layer 306, so that high-density plasma nitration case 312 is divided into the high-density plasma nitration case 312a of position above cap layer 306 and position in two parts of high-density plasma nitration case 3 12b of 304 of the floating boom utmost points, the method for Qu Chuing such as be to remove wherein with hot phosphoric acid solution.
Then, please refer to Fig. 3 D, remove oxide layer 306, the high-density plasma nitration case 312a that is positioned at oxide layer 306 tops simultaneously also will be removed, and stay the high-density plasma nitration case 312b of position 304 of the floating boom utmost points, wherein the method for Qu Chuing is to remove with hydrofluoric acid solution for example.
In sum, feature of the present invention comprises:
1, the present invention avoids flush memory device to produce breach by being formed at the layer of oxide layer that covers stack architecture in the substrate, or even forms the opening that runs through whole floor height density plasma oxide layer.
2, the present invention is by the protection of highdensity oxide layer, can avoid substrate because of coming out, and form the problem that is short-circuited behind the control grid.
3, the present invention is owing to adopt high intensity plasma glass as dielectric layer usefulness, thus can prevent the existence of moving iron or impurity, and then promote the reliability of device.
4, also can to select to adopt the high-density plasma nitration case to replace known with the usefulness of oxide layer as dielectric layer in the present invention, takes place with the problem that prevents to erase fast, also just can save the operating time of shipment forward stroke prefaceization/erase.
Though the present invention with a preferred embodiment openly as above; right its is not in order to limiting the present invention, anyly is familiar with this operator, without departing from the spirit and scope of the present invention; when can doing a little change and retouching, so protection scope of the present invention is as the criterion when looking claims person of defining.
Claims (9)
1. the flattening method of a flush memory device is characterized in that: comprising:
In a substrate, form a tunnel oxide;
On this tunnel oxide, form a floating boom utmost point;
Extremely go up formation one cap layer in this floating boom, wherein this tunnel oxide, this floating boom utmost point and this cap layer are formed a stack architecture;
Deposition one oxide layer in this substrate;
In this substrate, form a high intensity plasma glass, to cover this stack architecture;
Remove this high intensity plasma glass of part and this oxide layer, to expose the top margin of this cap layer;
Remove this cap layer, this high intensity plasma glass of part that wherein is positioned on this cap layer is removed simultaneously with this oxide layer of part.
2. flush memory device flattening method as claimed in claim 1 is characterized in that: the thickness of this high intensity plasma glass is extremely thick and thin than this stack architecture than this floating boom.
3. the flattening method of flush memory device as claimed in claim 1, it is characterized in that: the thickness of this high intensity plasma glass is between 1500 dust to 3000 dusts.
4. the flattening method of flush memory device as claimed in claim 1, it is characterized in that: this cap layer comprises nitration case.
5. the flattening method of flush memory device as claimed in claim 1, it is characterized in that: this floating boom utmost point comprises polysilicon.
6. the flattening method of flush memory device as claimed in claim 1 is characterized in that: after this oxide layer of deposition, also comprise and implement a temper with this oxide layer of densification, whereby to promote the anti-etching ability of this oxide layer in this substrate.
7. the flattening method of flush memory device as claimed in claim 1 is characterized in that: the method for removing this high intensity plasma glass of part and this oxide layer comprises with hydrofluoric acid solution to be removed.
8. the flattening method of flush memory device as claimed in claim 1 is characterized in that: the method for removing this high intensity plasma glass of part and this oxide layer comprises with the buffer silicon oxide etching solution to be removed.
9. the flattening method of flush memory device as claimed in claim 1, it is characterized in that: the method for removing this cap layer comprises with hot phosphoric acid solution to be removed.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CNB021422613A CN100389490C (en) | 2002-08-28 | 2002-08-28 | Flattening method of flas storage device |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CNB021422613A CN100389490C (en) | 2002-08-28 | 2002-08-28 | Flattening method of flas storage device |
Related Child Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| CNB2006101449371A Division CN100456441C (en) | 2002-08-28 | 2002-08-28 | Flattening method for flash memory device |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| CN1479368A CN1479368A (en) | 2004-03-03 |
| CN100389490C true CN100389490C (en) | 2008-05-21 |
Family
ID=34147990
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| CNB021422613A Expired - Fee Related CN100389490C (en) | 2002-08-28 | 2002-08-28 | Flattening method of flas storage device |
Country Status (1)
| Country | Link |
|---|---|
| CN (1) | CN100389490C (en) |
Families Citing this family (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN100346471C (en) * | 2004-12-16 | 2007-10-31 | 旺宏电子股份有限公司 | Flash memory storing element and method for making same |
| CN101577244B (en) * | 2008-05-05 | 2011-11-30 | 中芯国际集成电路制造(北京)有限公司 | Flattening method of interlayer medium layer and forming method of contact hole |
Citations (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US6391718B1 (en) * | 2001-01-03 | 2002-05-21 | Macronix International Co., Ltd. | Planarization method for flash memory device |
| US6441429B1 (en) * | 1998-04-06 | 2002-08-27 | Taiwan, Semiconductor Manufacturing Company | Split-gate flash memory device having floating gate electrode with sharp peak |
-
2002
- 2002-08-28 CN CNB021422613A patent/CN100389490C/en not_active Expired - Fee Related
Patent Citations (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US6441429B1 (en) * | 1998-04-06 | 2002-08-27 | Taiwan, Semiconductor Manufacturing Company | Split-gate flash memory device having floating gate electrode with sharp peak |
| US6391718B1 (en) * | 2001-01-03 | 2002-05-21 | Macronix International Co., Ltd. | Planarization method for flash memory device |
Also Published As
| Publication number | Publication date |
|---|---|
| CN1479368A (en) | 2004-03-03 |
Similar Documents
| Publication | Publication Date | Title |
|---|---|---|
| US9111871B2 (en) | Semiconductor structure and method for forming the same | |
| JP2001024076A (en) | Flash eeprom cell and manufacture thereof | |
| CN103107138A (en) | Manufacturing method of separated grid type flash memory with peripheral circuit | |
| CN101140877B (en) | Flash memory device | |
| US20050048721A1 (en) | Structure and fabricating method with self-aligned bit line contact to word line in split gate flash | |
| US7122443B2 (en) | Method of fabricating flash memory device | |
| US6468862B1 (en) | High capacitive-coupling ratio of stacked-gate flash memory having high mechanical strength floating gate | |
| CN111415937B (en) | Memory and forming method thereof | |
| CN100389490C (en) | Flattening method of flas storage device | |
| CN109659237B (en) | Forming method of flash memory device | |
| CN100456441C (en) | Flattening method for flash memory device | |
| US7300844B2 (en) | Method of forming gate of flash memory device | |
| CN113745228B (en) | Semiconductor structure and forming method thereof | |
| CN106298676B (en) | Method for manufacturing semiconductor element | |
| CN100468704C (en) | Production method of SONOS flash memory | |
| CN112447742B (en) | Semiconductor structure and forming method thereof | |
| CN100517657C (en) | SONOS Flash memory manufacture method | |
| US7413953B2 (en) | Method of forming floating gate array of flash memory device | |
| US20090065846A1 (en) | Non-volatile memory and manufacturing method thereof | |
| CN103178018A (en) | Method for manufacturing separation gate quick-flashing memory unit | |
| CN111755449B (en) | Semiconductor structure and forming method thereof | |
| CN103943571A (en) | Manufacturing method of nonvolatile memory | |
| US20230062401A1 (en) | Test structure for void and topography monitoring in a flash memory device | |
| KR20100079329A (en) | Method manufactruing of flash memory device | |
| US7488649B2 (en) | Method of manufacturing split gate type non-volatile memory device |
Legal Events
| Date | Code | Title | Description |
|---|---|---|---|
| C06 | Publication | ||
| PB01 | Publication | ||
| C10 | Entry into substantive examination | ||
| SE01 | Entry into force of request for substantive examination | ||
| C14 | Grant of patent or utility model | ||
| GR01 | Patent grant | ||
| CF01 | Termination of patent right due to non-payment of annual fee | ||
| CF01 | Termination of patent right due to non-payment of annual fee |
Granted publication date: 20080521 Termination date: 20190828 |