CN100385625C - Polysiliconized metal grid structure and method for making same - Google Patents

Polysiliconized metal grid structure and method for making same Download PDF

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CN100385625C
CN100385625C CNB2004100399681A CN200410039968A CN100385625C CN 100385625 C CN100385625 C CN 100385625C CN B2004100399681 A CNB2004100399681 A CN B2004100399681A CN 200410039968 A CN200410039968 A CN 200410039968A CN 100385625 C CN100385625 C CN 100385625C
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layer
polysilicon
metal silicide
metal
protective layer
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CN1670921A (en
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刘汉兴
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Winbond Electronics Corp
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Winbond Electronics Corp
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Abstract

The present invention relates to a polycrystal silication metal gate structure and a manufacturing method thereof. The manufacturing method comprises the following steps: (a) a base board is provided; (b) a polysilicon layer r and a silication metal layer are respectively formed above the base board; (c) a part of the silication metal layer is removed to define a silication metal structure; (d) a protective layer is formed on the polysilicon layer and covers the silication metal structure; (e) a horizontal part which the protective layer, the polysiliconlayer and the silication metal structure are contacted is removed to form a protective structure; (f) the polysilicon layer which is not covered by the silication metal structure and the protective structure is removed to define the polysilicon structure; (g) the polysilicon structure is oxidated so that the side surface of the polysilicon structure forms an insulation structure.

Description

Multi-crystal silicification metal gate structure and manufacture method thereof
Technical field
Relevant a kind of semiconductor structure of the present invention and manufacture method thereof refer to that especially it can be applicable to CMOS transistor (CMOS) about a kind of multi-crystal silicification metal gate structure and manufacture method thereof.
Background technology
Because the development of semiconductor element technology in recent years rapidly and then brought up the flourish of computer, communication and network industry, and its progressive motive power, be that metal oxide semiconductor transistor (MOS) size constantly dwindles, because the element that dwindles can improve switch speed and components consume power, the element integrated level of circuit and functional (as data storage, logical operation, signal processing etc.) have also all been strengthened.Since CMOS transistor (CMOS) have high integration and and advantage such as low-energy-consumption, therefore be the most normal semiconductor element that is used and researchs and develops at present.
In the integrated circuit processing technique of deep-submicron, because in live width, contact area and connect under all diminishing situation such as the face degree of depth, in order to improve the craftmanship of element effectively, reduce resistance and reduce resistance capacitance (RC) signal propagation delay that is caused and the dead resistance that reduces element gate, replace previous polysilicon (polysilicon) grid and develop polysilicon metal (Polycide) grid structure.See also Fig. 1, this technology grows one deck tungsten silicide (WSi exactly on polysilicon (polysilicon) 1 X) 2, because of tungsten silicide (WSi X) 2 have the advantage of high-melting-point, stability and low-resistivity, so the application on semiconductor technology is more and more general, particularly be used as the grid conducting layer of metal oxide semiconductor transistor (MOS).
It should be noted that because of polysilicon metal (Polycide) the 1st, by polysilicon (polysilicon) 1 and tungsten silicide (WSi X) 2 two kinds of unlike materials form, and single plasma is to both etching speeds and inconsistent, thus must be divided into two steps, so that carry out etching at single material respectively.Phase I at first is to the tungsten silicide (WSi on the polysilicon metal (Polycide) 3 X) 2 carry out etching, as tungsten silicide (WSi X) after 2 etching ends, enter second stage polysilicon (polysilicon) 1 etching again.Because tungsten silicide (WSi X) 2 produce oxidation when being easy to high temperature (about 400 ℃), and the oxide of tungsten is volatile, can pollute environment.Usually general plasma etching also can be kept the environment that is lower than below 400 ℃, but when carrying out second stage to polysilicon (polysilicon) 1 etching, because of polysilicon (polysilicon) 1 needs higher etch-rate, to guarantee thoroughly to remove the polysilicon metal (Polycide) 3 that is exposed under the plasma, therefore temperature may continue to increase to improve etch-rate, tungsten silicide (WSi like this X) 2 items can Yin Wendu too high and produce oxidation, and then produce volatile contaminant matter, and be covered in tungsten oxide on the silicon layer to have increased the contact range with silicon dioxide layer 4, therefore cause leakage current easily.
Summary of the invention
Purpose of the present invention is for providing a kind of multi-crystal silicification metal gate structure and manufacture method thereof.
The manufacture method of multi-crystal silicification metal gates according to an aspect of the present invention comprises the following steps: that (a) provides a substrate; (b) form a polysilicon layer and a metal silicide layer respectively in this substrate top; (c) remove this metal silicide layer partly, use limiting a metal silicide structure; (d) form a protective layer on this polysilicon layer, and cover this metal silicide structure; (e) remove the level part that this protective layer contacts with this polysilicon layer and this metal silicide structure, to form a protection structure; (f) remove not this polysilicon layer that is covered by this metal silicide structure and this protection structure, use qualification one polysilicon structure; And (g) this polysilicon structure of oxidation, make the side of this polysilicon structure form an insulation system.
According to above-mentioned conception, include an insulating barrier on this substrate and this insulating barrier material is silicon dioxide (SiO 2).
According to above-mentioned conception, this metal silicide layer is to comprise a barrier layer, a tungsten layer and a silicon nitride (SiN in regular turn on this polysilicon layer X) layer, wherein this barrier layer material is titanium nitride (TiN).
According to above-mentioned conception, this metal silicide structure is to utilize an anisotropic dry etch to form.
According to above-mentioned conception, this protective layer is to form by the chemical vapor deposition (CVD) technology, and this protective layer thickness is 50 ~500
Figure C20041003996800052
, this protective layer material can be silicon nitride (SiN again X).
According to above-mentioned conception, this protection structure and this polysilicon structure utilize an anisotropic dry etch to form.
According to above-mentioned conception, be to utilize dry type oxidation process to form this insulation system.
Multi-crystal silicification metal gate structure according to a further aspect of the invention, it comprises:
(a) substrate; (b) polysilicon structure is formed on this substrate, and forms an insulation system in the side of this polysilicon structure; And (c) metal silicide structure, be formed on this polysilicon structure, and form a protection structure in the side of this polysilicon structure.
According to above-mentioned conception, wherein include an insulating barrier on this substrate, and form a polysilicon layer and a metal silicide layer in regular turn, and remove this metal silicide layer partly in this substrate top, use limiting this metal silicide structure.
According to above-mentioned conception, wherein this insulating barrier material is silicon dioxide (SiO 2).
According to above-mentioned conception, wherein this metal silicide layer is to comprise a barrier layer, a tungsten layer and a silicon nitride (SiN in regular turn on this polysilicon layer X) layer, and this barrier layer material is titanium nitride (TiN).
According to above-mentioned conception, wherein this protection structure is that to form a thickness by the chemical vapor deposition (CVD) technology be 50
Figure C20041003996800061
~500
Figure C20041003996800062
Protective layer and covers this metal silicide structure on this polysilicon layer, remove level that this protective layer contacts with this polysilicon layer and this metal silicide structure more partly, to form this protection structure.
According to above-mentioned conception, wherein this protective layer material can be silicon nitride (SiN X).
According to above-mentioned conception, wherein be to utilize dry type oxidation process to form this insulation system.
According to above-mentioned conception, wherein this polysilicon structure, this metal silicide structure and this protection structure are to utilize an anisotropic dry etch to form.
For further specifying above-mentioned purpose of the present invention, design feature and effect, the present invention is described in detail below with reference to accompanying drawing.
Description of drawings
Fig. 1 is existing multi-crystal silicification metal gate structure schematic diagram.
Fig. 2 (a)~(h) is the multi-crystal silicification metal gate structure schematic diagram of preferred embodiment of the present invention.
Embodiment
The invention provides a kind of multi-crystal silicification metal gate structure and manufacture method thereof.Fig. 2 (a)~(h): the multi-crystal silicification metal gate structure schematic diagram of preferred embodiment of the present invention, the step-by-step procedures of this method is as follows:
One base material 21 at first is provided, utilize a shallow trench isolation method (Shallow Trench Isolation, STI) form one first isolation structure 22 and one second isolation structure 23 on this substrate 21 (shown in Fig. 2 (a)) respectively, and (Localized OxidationIsolation is LOCOS) to reach the purpose that forms above-mentioned isolation structure also can to utilize a localized oxidation of silicon isolation method.
Then, with the lip-deep silicon of active region, be oxidized to silicon dioxide (SiO with dry type oxidation process 2) layer 24, this silicon dioxide (SiO 2) layer 24 will be as transistorized gate oxide (Gate Oxide) (shown in Fig. 2 (b)).Then, (thickness is about 500 to form a polysilicon layer 25 in regular turn by the chemical vapor deposition (CVD) technology
Figure C20041003996800071
~1500
Figure C20041003996800072
), (thickness is about 50 on a barrier layer 26
Figure C20041003996800073
~200
Figure C20041003996800074
, its material is titanium nitride (TiN)), (thickness is about 500 to a tungsten layer 27
Figure C20041003996800075
~2000
Figure C20041003996800076
) and one first silicon nitride (SiN X) (thickness is about 500 to layer 28
Figure C20041003996800077
~3000
Figure C20041003996800078
).Next, in this first silicon nitride (SiN X) cover a photoresist 29 (shown in Fig. 2 (c)) on the layer 28, and utilize an anisotropic dry etch, this first silicon nitride (SiN of this photoresist protection will not arranged on the wafer X) layer, this tungsten layer and this barrier layer removed together, and use and limit a metal silicide structure 30 (shown in Fig. 2 (d)).Form one second silicon nitride (SiN by the chemical vapor deposition (CVD) technology again X) layer 31 on this polysilicon layer 25, and cover this metal silicide structure 30 (shown in Fig. 2 (e)), utilize this second silicon nitride of an anisotropic dry etch (SiN again X) layer 31 levels part that contacts with this polysilicon layer and this metal silicide structure, to form a protection structure 32 (shown in Fig. 2 (f)).Then, with this first silicon nitride (SiN X) layer is 28 as a shade; and utilize an anisotropic dry etch; with being arranged on the wafer, do not remove this polysilicon layer of this shade protection; and use qualification one polysilicon structure 33, wherein this metal silicide structure 30 is the multi-crystal silicification metal gates 34 (shown in Fig. 2 (g)) that can be used as metal oxide semiconductor transistor (MOS) with this polysilicon structure 33.Form an insulation system 35 (shown in Fig. 2 (h)) in these polysilicon structure 33 both sides with dry type oxidation process at last, its material is silicon dioxide (SiO 2), can be used to isolate the source/drain electrode of multi-crystal silicification metal gates 33 and transistor metal oxide semiconductor transistor (MOS), in order to carrying out follow-up source/drain electrode heavy doping action.
In sum, the present invention is compared to the manufacture method of prior art, can solve material of tungsten and when high temperature, produce danger with contaminative oxide, to meet the industry environmental protection of being advocated at present, moreover, because of having blocked the oxidation stain deposits yields of tungsten, the oxidize contaminants that more can avoid tungsten is because of having contacted the anxiety of leakage current with silicon layer.Therefore can know that for the foregoing reasons the present invention really can provide preferable in fact benefiting for the development of industry.
Though the present invention describes with reference to current specific embodiment, but those of ordinary skill in the art will be appreciated that, above embodiment is used for illustrating the present invention, under the situation that does not break away from spirit of the present invention, also can make the variation and the modification of various equivalences, therefore, as long as variation, the modification to the foregoing description all will drop in the scope of claims of the present invention in connotation scope of the present invention.

Claims (11)

1. the manufacture method of a multi-crystal silicification metal gates, this manufacture method comprises the following steps:
(a) provide a substrate;
(b) form a polysilicon layer and a metal silicide layer respectively in this substrate top;
(c) remove this metal silicide layer partly, use limiting a metal silicide structure;
(d) form a protective layer on this polysilicon layer, and cover this metal silicide structure;
(e) remove the level part that this protective layer contacts with this polysilicon layer and this metal silicide structure, to form a protection structure;
(f) remove not this polysilicon layer that is covered by this metal silicide structure and this protection structure, use qualification one polysilicon structure; And
(g) this polysilicon structure of oxidation makes the side of this polysilicon structure form an insulation system, and wherein this insulation system is made of different materials with this protection structure.
2. manufacture method as claimed in claim 1 is characterized in that this metal silicide layer is made of tungsten layer, and is to comprise a barrier layer, a tungsten layer and a silicon nitride layer in regular turn on this polysilicon layer.
3. manufacture method as claimed in claim 1 is characterized in that this protective layer thickness is
Figure C2004100399680002C2
4. manufacture method as claimed in claim 1 is characterized in that this protective layer material is a silicon nitride.
5. manufacture method as claimed in claim 1 is characterized in that it being to utilize dry type oxidation process to form this insulation system.
6. multi-crystal silicification metal gate structure, it comprises:
(a) substrate;
(b) polysilicon structure is formed on this substrate, and forms an insulation system in the side of this polysilicon structure; And
(c) a metal silicide structure is formed on this polysilicon structure, and forms a protection structure in the side of this polysilicon structure, and wherein this insulation system is made of different materials with this protection structure.
7. structure as claimed in claim 6 is characterized in that including an insulating barrier on this substrate, and forms a polysilicon layer and a metal silicide layer in regular turn in this substrate top, and removes this metal silicide layer partly, uses limiting this metal silicide structure.
8. structure as claimed in claim 7 is characterized in that this metal silicide layer is to comprise a barrier layer, a tungsten layer and a silicon nitride layer in regular turn on this polysilicon layer.
9. structure as claimed in claim 7; it is characterized in that this protection structure is by forming a protective layer on this polysilicon layer; and cover this metal silicide structure, remove the level part that this protective layer contacts with this polysilicon layer and this metal silicide structure again, to form this protection structure.
10. structure as claimed in claim 9 is characterized in that this protective layer thickness is
Figure C2004100399680003C1
11. structure as claimed in claim 9 is characterized in that this protective layer material is a silicon nitride.
CNB2004100399681A 2004-03-15 2004-03-15 Polysiliconized metal grid structure and method for making same Expired - Lifetime CN100385625C (en)

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CN101866844B (en) * 2010-05-12 2015-04-22 上海华虹宏力半导体制造有限公司 Polysilicon etching method
US8258584B2 (en) * 2010-07-29 2012-09-04 Taiwan Semiconductor Manufacturing, Inc. Offset gate semiconductor device
CN111627992B (en) * 2020-06-05 2023-04-04 福建省晋华集成电路有限公司 Grid structure and manufacturing method thereof

Citations (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN1142684A (en) * 1995-06-30 1997-02-12 现代电子产业株式会社 Method for fabricating metal oxide field effect transistors
US6204173B1 (en) * 1996-06-13 2001-03-20 Micron Technology, Inc. Multiple implantation and grain growth method
US6544874B2 (en) * 2001-08-13 2003-04-08 International Business Machines Corporation Method for forming junction on insulator (JOI) structure

Patent Citations (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN1142684A (en) * 1995-06-30 1997-02-12 现代电子产业株式会社 Method for fabricating metal oxide field effect transistors
US6204173B1 (en) * 1996-06-13 2001-03-20 Micron Technology, Inc. Multiple implantation and grain growth method
US6544874B2 (en) * 2001-08-13 2003-04-08 International Business Machines Corporation Method for forming junction on insulator (JOI) structure

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