CN100380518C - 产生固态存储器的地址配置的方法 - Google Patents

产生固态存储器的地址配置的方法 Download PDF

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Publication number
CN100380518C
CN100380518C CNB021495300A CN02149530A CN100380518C CN 100380518 C CN100380518 C CN 100380518C CN B021495300 A CNB021495300 A CN B021495300A CN 02149530 A CN02149530 A CN 02149530A CN 100380518 C CN100380518 C CN 100380518C
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CN
China
Prior art keywords
address
lines
memory
line
sequence
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Expired - Lifetime
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CNB021495300A
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English (en)
Chinese (zh)
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CN1419240A (zh
Inventor
J·N·霍甘
R·M·罗斯
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Samsung Electronics Co Ltd
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Hewlett Packard Co
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Publication date
Application filed by Hewlett Packard Co filed Critical Hewlett Packard Co
Publication of CN1419240A publication Critical patent/CN1419240A/zh
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Publication of CN100380518C publication Critical patent/CN100380518C/zh
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    • G—PHYSICS
    • G06—COMPUTING OR CALCULATING; COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F12/00—Accessing, addressing or allocating within memory systems or architectures
    • G06F12/02—Addressing or allocation; Relocation
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C8/00—Arrangements for selecting an address in a digital store
    • G11C8/10—Decoders
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C8/00—Arrangements for selecting an address in a digital store
    • G11C8/12—Group selection circuits, e.g. for memory block selection, chip selection, array selection

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  • Engineering & Computer Science (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Theoretical Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • General Engineering & Computer Science (AREA)
  • General Physics & Mathematics (AREA)
  • For Increasing The Reliability Of Semiconductor Memories (AREA)
  • Read Only Memory (AREA)
  • Static Random-Access Memory (AREA)
  • Techniques For Improving Reliability Of Storages (AREA)
CNB021495300A 2001-11-13 2002-11-13 产生固态存储器的地址配置的方法 Expired - Lifetime CN100380518C (zh)

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
US09/990,924 US6466512B1 (en) 2001-11-13 2001-11-13 Method of generating address configurations for solid state memory
US09/990924 2001-11-13

Publications (2)

Publication Number Publication Date
CN1419240A CN1419240A (zh) 2003-05-21
CN100380518C true CN100380518C (zh) 2008-04-09

Family

ID=25536657

Family Applications (1)

Application Number Title Priority Date Filing Date
CNB021495300A Expired - Lifetime CN100380518C (zh) 2001-11-13 2002-11-13 产生固态存储器的地址配置的方法

Country Status (6)

Country Link
US (1) US6466512B1 (https=)
EP (1) EP1310960A3 (https=)
JP (1) JP4081350B2 (https=)
KR (1) KR20030040101A (https=)
CN (1) CN100380518C (https=)
TW (1) TW580711B (https=)

Families Citing this family (13)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US6535455B1 (en) * 2001-10-13 2003-03-18 Hewlett-Packard Company Fault-tolerant neighborhood-disjoint address logic for solid state memory
US7003713B2 (en) * 2002-05-16 2006-02-21 Broadcom Corporation Variable Hamming error correction for a one-time-programmable-ROM
US7350132B2 (en) * 2003-09-10 2008-03-25 Hewlett-Packard Development Company, L.P. Nanoscale interconnection interface
US7191380B2 (en) * 2003-09-10 2007-03-13 Hewlett-Packard Development Company, L.P. Defect-tolerant and fault-tolerant circuit interconnections
US7307345B2 (en) * 2005-11-01 2007-12-11 Hewlett-Packard Development Company, L.P. Crossbar-array designs and wire addressing methods that tolerate misalignment of electrical components at wire overlap points
US7495942B2 (en) * 2004-08-13 2009-02-24 University Of Florida Research Foundation, Inc. Nanoscale content-addressable memory
US7489583B2 (en) * 2005-09-06 2009-02-10 Hewlett-Packard Development Company, L.P. Constant-weight-code-based addressing of nanoscale and mixed microscale/nanoscale arrays
US7319416B2 (en) * 2006-01-30 2008-01-15 Hewlett-Packard Development Company, L.P. Tunneling-resistor-junction-based microscale/nanoscale demultiplexer arrays
US7763978B2 (en) * 2007-03-28 2010-07-27 Hewlett-Packard Development Company, L.P. Three-dimensional crossbar array systems and methods for writing information to and reading information stored in three-dimensional crossbar array junctions
US7630246B2 (en) * 2007-06-18 2009-12-08 Micron Technology, Inc. Programming rate identification and control in a solid state memory
KR100892673B1 (ko) 2007-09-05 2009-04-15 주식회사 하이닉스반도체 어드레스 치환 회로 및 이를 포함하는 반도체 메모리 장치
KR100956946B1 (ko) * 2008-04-16 2010-05-11 매그나칩 반도체 유한회사 비휘발성 메모리 장치의 쓰기방법
KR100971654B1 (ko) * 2008-06-25 2010-07-22 (주)아이엘전자 플럭스 유입 방지 택트 스위치

Citations (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
WO2000017757A2 (en) * 1998-09-04 2000-03-30 Intel Corporation Redundant form address decoder for memory system
CN1254928A (zh) * 1998-10-28 2000-05-31 现代电子产业株式会社 存储器的地址选通信号发生器
US6088287A (en) * 1999-08-23 2000-07-11 Advanced Micro Devices, Inc. Flash memory architecture employing three layer metal interconnect for word line decoding

Family Cites Families (9)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US4064558A (en) * 1976-10-22 1977-12-20 General Electric Company Method and apparatus for randomizing memory site usage
US4092665A (en) * 1976-12-29 1978-05-30 Xerox Corporation Method and means for extracting variable length data from fixed length bytes
US4556960A (en) * 1982-12-13 1985-12-03 Sperry Corporation Address sequencer for overwrite avoidance
US4782340A (en) * 1986-08-22 1988-11-01 Energy Conversion Devices, Inc. Electronic arrays having thin film line drivers
US5550782A (en) * 1991-09-03 1996-08-27 Altera Corporation Programmable logic array integrated circuits
JPH0696598A (ja) * 1992-07-10 1994-04-08 Texas Instr Japan Ltd 半導体メモリ装置及び欠陥メモリセル救済回路
US5721498A (en) * 1995-12-11 1998-02-24 Hewlett Packard Company Block segmentation of configuration lines for fault tolerant programmable logic device
JP2000285694A (ja) * 1999-03-30 2000-10-13 Mitsubishi Electric Corp 半導体記憶装置および半導体記憶装置を搭載する半導体集積回路装置
US6459648B1 (en) * 2001-10-13 2002-10-01 Josh N. Hogan Fault-tolerant address logic for solid state memory

Patent Citations (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
WO2000017757A2 (en) * 1998-09-04 2000-03-30 Intel Corporation Redundant form address decoder for memory system
CN1254928A (zh) * 1998-10-28 2000-05-31 现代电子产业株式会社 存储器的地址选通信号发生器
US6088287A (en) * 1999-08-23 2000-07-11 Advanced Micro Devices, Inc. Flash memory architecture employing three layer metal interconnect for word line decoding

Also Published As

Publication number Publication date
CN1419240A (zh) 2003-05-21
US6466512B1 (en) 2002-10-15
JP2003187589A (ja) 2003-07-04
EP1310960A2 (en) 2003-05-14
EP1310960A3 (en) 2005-01-12
KR20030040101A (ko) 2003-05-22
TW200300261A (en) 2003-05-16
TW580711B (en) 2004-03-21
JP4081350B2 (ja) 2008-04-23

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GR01 Patent grant
ASS Succession or assignment of patent right

Owner name: SAMSUNG ELECTRONICS CO., LTD.

Free format text: FORMER OWNER: HEWLETT-PACKARD CO. (US) P.O. BOX 10301, PALO ALTO CALIFORNIA U.S.A.

Effective date: 20110222

C41 Transfer of patent application or patent right or utility model
COR Change of bibliographic data

Free format text: CORRECT: ADDRESS; FROM: STATE OF CALIFORNIA, THE USA TO: GYEONGGI-DO, SOUTH KOREA

TR01 Transfer of patent right

Effective date of registration: 20110222

Address after: Gyeonggi Do, South Korea

Patentee after: SAMSUNG ELECTRONICS Co.,Ltd.

Address before: California, USA

Patentee before: Hewlett-Packard Co.

CX01 Expiry of patent term
CX01 Expiry of patent term

Granted publication date: 20080409