CN100377336C - Semiconductor device and its producing method - Google Patents
Semiconductor device and its producing method Download PDFInfo
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- CN100377336C CN100377336C CNB2005100530390A CN200510053039A CN100377336C CN 100377336 C CN100377336 C CN 100377336C CN B2005100530390 A CNB2005100530390 A CN B2005100530390A CN 200510053039 A CN200510053039 A CN 200510053039A CN 100377336 C CN100377336 C CN 100377336C
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/44—Structure, shape, material or disposition of the wire connectors prior to the connecting process
- H01L2224/45—Structure, shape, material or disposition of the wire connectors prior to the connecting process of an individual wire connector
- H01L2224/45001—Core members of the connector
- H01L2224/45099—Material
- H01L2224/451—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron (B), silicon (Si), germanium (Ge), arsenic (As), antimony (Sb), tellurium (Te) and polonium (Po), and alloys thereof
- H01L2224/45117—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron (B), silicon (Si), germanium (Ge), arsenic (As), antimony (Sb), tellurium (Te) and polonium (Po), and alloys thereof the principal constituent melting at a temperature of greater than or equal to 400°C and less than 950°C
- H01L2224/45124—Aluminium (Al) as principal constituent
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
- H01L2224/4805—Shape
- H01L2224/4809—Loop shape
- H01L2224/48091—Arched
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/73—Means for bonding being of different types provided for in two or more of groups H01L2224/10, H01L2224/18, H01L2224/26, H01L2224/34, H01L2224/42, H01L2224/50, H01L2224/63, H01L2224/71
- H01L2224/732—Location after the connecting process
- H01L2224/73251—Location after the connecting process on different surfaces
- H01L2224/73265—Layer and wire connectors
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Abstract
To provide a semiconductor device which can secure a durability to thermal cycle equivalent to that when a lead-contained solder is used, can suppress a thermal resistance and secure a heat resistance, and can suppress increase in manufacturing cost, and also a method for manufacturing the semiconductor device. An insulating substrate 2 is joined onto a main surface of a heatsink 1 made of a copper material. A rear-side pattern 5 of the insulating substrate 2 is joined onto a main surface of the heatsink 1 via a solder layer 7 on the rear side of the substrate, whereby the insulating substrate 2 is fixed to the surface of the heatsink 1. Angle grooves 15, inner walls of which are inwardly tilted, are disposed in the outside of four corners of a ceramic base material 3 of the insulating substrate 2 in the main surface of the heatsink 1 outside of end edges of the ceramic base material 3.
Description
Technical field
The present invention relates to semiconductor device and manufacture method thereof, specifically, relate to semiconductor element mounted thereon on insulated substrate, this insulated substrate is connected to semiconductor device and manufacture method thereof on the radiator of resin box bottom surface by welding.
Background technology
Semiconductor element mounted thereon on insulated substrate, by welding this insulated substrate is connected in the semiconductor device on the radiator of resin box bottom surface, when radiator uses copper (Cu) material, add thermal cycle, then can cause in the soldering-tin layer (being called soldering-tin layer under the substrate) that connects radiator and insulated substrate to crack by the differing from of thermal coefficient of expansion between insulated substrate and the Cu.
What become problem here especially is, current, uses from the viewpoint of environmental protection to promote the lead-free Pb-free solder that utilizes.
For example, Sn-Ag-cu system, Sn-Zn system, perhaps, add the Pb-free solder of Bi, Ni, Co, Sb etc. in these, if the deflection of soldering-tin layer under the substrate is identical, then compare with leaded scolding tin, low to the durability performance of thermal cycle, this inventor is clear and definite by test.
Promptly, when crackle takes place in the soldering-tin layer under the substrate that soldering-tin layer and leaded scolding tin constitute under the substrate that Pb-free solder constitutes, when if the deflection of soldering-tin layer is identical, then for the number of occurrence of the thermal cycle relevant with life of product, under the substrate that constitutes by Pb-free solder soldering-tin layer be under the substrate that constitutes by leaded scolding tin soldering-tin layer about 1/5th.
Thereby, when under substrate, using the Pb-free solder of above-mentioned composition in the soldering-tin layer,, keep reliability in order to ensure the durability of thermal cycle equal when using leaded scolding tin, can consider to reduce the deflection of soldering-tin layer.
From above-mentioned result of the test, when having confirmed that under substrate soldering-tin layer uses Pb-free solder, must be reduced to about 45% of deflection when using leaded scolding tin.
In order to reduce the deflection of soldering-tin layer under the substrate, consider to add the thickness of soldering-tin layer under the thick substrate, the thickness of attenuate radiator, the thickness of attenuate insulated substrate etc., when testing respectively, can produce the increase of thermal resistance, the increase of radiator distortion, constitute the new problems such as crackle appearance of the ceramic matrix material of insulated substrate, deflection when as a result, using Pb-free solder can not be reduced to about 45% of deflection when using leaded scolding tin.
In addition, when radiator uses the little material of thermal coefficient of expansion, can reach above-mentioned numerical target, but the cost of this material is higher about 10 times than Cu, what obtain is not the solution of practicality.
Here, in the patent documentation 1,,, disclose and formed the structure that flows into the recess of soldering-tin layer under the substrate around the insulated substrate for preventing to generate crackle under the substrate in the soldering-tin layer though do not mention utilization at Pb-free solder.
[patent documentation 1] spy opens 2002-57280 communique (Figure 11～Figure 13)
Summary of the invention
As described above, when even soldering-tin layer uses Pb-free solder under the substrate, traditional test for the durability of guaranteeing thermal cycle equal when using leaded scolding tin, have and to produce the increase that makes thermal resistance, the increase of the distortion of radiator, constitute in the ceramic matrix material of insulated substrate on new problem such as crackle generation and the manufacturing cost and unpractical problem.
The present invention be directed to the above-mentioned problem points of elimination proposes, purpose provides: the durability that equal thermal cycle is arranged when guaranteeing with the leaded scolding tin of use, realize suppressing thermal resistance and guaranteeing thermal endurance, suppress the semiconductor device and the manufacture method thereof of the rising of manufacturing cost.
Semiconductor device of the present invention possesses:
The rectangular-shaped insulated substrate of semiconductor element mounted thereon;
The radiator that on interarea, is connected with above-mentioned insulated substrate;
With the resin box of above-mentioned radiator as the bottom surface;
Be filled into the hardening resin in the above-mentioned resin box,
The above-mentioned interarea of above-mentioned radiator and being connected of above-mentioned insulated substrate be by
Constitute that the lead-free soldering tin layer that forms between the above-mentioned interarea of the ceramic matrix material of above-mentioned insulated substrate and above-mentioned radiator realizes,
Above-mentioned radiator,
Have and be arranged at least in the above-mentioned interarea corresponding, along the tipper that above-mentioned bight is expanded and its inwall tilts to the inside with the outside, tetragonal bight of above-mentioned ceramic matrix material.
The manufacture method of semiconductor device of the present invention,
Above-mentioned independent inclination groove, by
With respect to the vertical groove of inwall with groove bottom width, groove depth and plan view shape identical with above-mentioned independent inclination groove, with having than wideer width of the groove width of this groove and the diel that has with the protuberance of above-mentioned independent inclination groove same level view shape to come punching press is carried out on the top of above-mentioned groove, make the upper inside wall of above-mentioned groove move and form to the interior Side Volume of above-mentioned groove.
According to semiconductor device of the present invention, owing to have tipper, it is arranged in the interarea of the outside corresponding radiator in the square bight of ceramic matrix material at least, tilt to the inside along bight expansion and inwall, thereby the hardening resin that enters tipper can prevent to split between the edge part of lead-free soldering tin layer and the radiator, thereby, when using Pb-free solder fixed insulation substrate,, can prevent that also lead-free soldering tin layer from cracking and the crackle diffusion even apply thermal cycle.
According to manufacturing method for semiconductor device of the present invention, owing to but punch process forms the independent inclination groove, thereby, if the bight curvature of ceramic matrix material is identical, ceramic matrix material to all size and shape (square and rectangle), but general stamping mould, the expense of inhibition Mold Making just can suppress the increase of the manufacturing cost of semiconductor device integral body.In addition, because stamped area is limited to than in the close limit, stamping pressure only needs less getting final product, and does not need to use large-scale decompressor, can suppress the increase of manufacturing cost.
Description of drawings
Fig. 1 is the formation sectional view of the semiconductor device of the explanation embodiment of the invention.
Fig. 2 is the figure of the situation occurred of soldering-tin layer generation crackle under the explanation substrate.
Fig. 3 is the figure of the situation occurred of the crackle that soldering-tin layer takes place under the explanation substrate.
Fig. 4 is the plane graph of partly leading the formation of stopping device of the explanation embodiment of the invention.
Fig. 5 is the formation sectional view of explanation tipper.
Fig. 6 is the figure of the measured result of expression each factor of formation of determining tipper.
Fig. 7 is the figure of the measured result of expression each factor of formation of determining tipper.
Fig. 8 is the formation plane graph of variation 1 of the semiconductor device of the explanation embodiment of the invention.
Fig. 9 is the formation plane graph of variation 2 of the semiconductor device of the explanation embodiment of the invention.
Figure 10 is the formation plane graph of variation 3 of the semiconductor device of the explanation embodiment of the invention.
Figure 11 is the sectional view of manufacture method of the tipper of explanation punch process.
Figure 12 is the sectional view of manufacture method of the tipper of explanation punch process.
Figure 13 is the sectional view of manufacture method of the tipper of explanation punch process.
Symbol description
1 radiator, 2 insulated substrates, 3 ceramic substrates, 4 circuit patterns, 5 back side patterns, 6 semiconductor elements, soldering-tin layer under 7 substrates, 10 enclosure, 15 tippers, 16 the 1st layers of moulded resin, 17 the 2nd layers of moulded resin 20 resin boxes 30 solder resist
Embodiment
Embodiment
To the embodiment of semiconductor device of the present invention, use Fig. 1～Figure 13 to describe.
＜A-1. device constitutes 〉
＜A-1-1. is whole to be constituted 〉
At first, use Fig. 1 that the formation of the semiconductor device 100 of embodiment is described.
Fig. 1 is that the partial cross section figure of expression semiconductor device 100 has only represented the part relevant with invention.
Among Fig. 1, on the interarea of the radiator 1 that constitutes by copper (Cu) material, be connected with insulated substrate 2.
In addition, the last interarea of ceramic matrix material 3 promptly descends in the interarea of interarea opposition side, is provided with by what Cu or Al constituted thickly to be the circuit pattern 4 of 0.25mm～0.5mm.
In addition, circuit pattern 4 and back side pattern 5 are by the connection of activator metal method or directly connect and be connected with ceramic matrix material 3.
In addition, back side pattern 5 is connected with the interarea of radiator 1 via soldering-tin layer under the substrate 7 (lead-free soldering tin layer), thus insulated substrate 2 is fixed on the radiator 1.
In addition, under the substrate under soldering-tin layer 7 and the semiconductor element soldering-tin layer 8 constitute by Pb-free solder, its composition is, for example, Sn-Ag-Cu system, Sn-Zn system, or add Bi, Ni, Co, Sb etc. in these the insides.
And, in the interarea of the radiator 1 of the edge part outside of the ceramic matrix material 3 that constitutes insulated substrate 2, being provided with tipper 15 (independent inclination groove), it is arranged on the outside, tetragonal bight of ceramic matrix material 3, and inwall tilts to the inside.In addition, will be elaborated below to tipper 15.
Surrounded by the enclosure 10 of resin type around the radiator 1, constituting with radiator 1 is that bottom surface, this bottom surface are that opposition side is the resin box 20 of peristome.In addition, enclosure 10 and resin box 20 are bonding by bonding agent 12.
And, in resin box 20, begin to fill the 1st layer of moulded resin 16 (hardening resin) until the level that covers aluminum steel 9, on the top of the 1st layer of moulded resin 16 from the bottom surface, fill the 2nd layer of moulded resin 17 (hardening resin) until the upper surface of enclosure 10, become 2 layers of resin construction.
The 1st layer of moulded resin 16 owing to also directly contact with the surface of semiconductor element 6, linear expansion coefficient and crooked elastic rate are low, by use impurity few moulded resin, can not lose do one's utmost, element characteristic.
For example, using linear expansion coefficient is 16～22 (ppm/K), and crooked elastic rate is the resin of 7.8～8.8GPa (GigaPascal).In addition, the content of impurity, sodium (Na) ion and halogen (Cl) ion probably are below the 40ppm.
On the other hand, the 2nd layer of moulded resin 17 do not need the physics value of the 1st layer of moulded resin 16 such tight regulation, and for example using linear expansion coefficient is 25～27 (ppm/K), crooked elastic rate is the resin of 11～13Gpa, but also not necessarily will be in this scope.In addition, the not special regulation of the content of impurity.
In addition, use 2 kinds of resins to be in the resin box 20 because the 1st moulded resin 16 price height in addition, are filled the 1st layer of moulded resin until covering aluminum steel 9, if carry out pseudosclerosis, use what kind of resin also can not influence semiconductor element 6 later on.In addition, fill the 2nd layer of moulded resin 17 after, make the 1st layer of moulded resin 16 and 17 sclerosis of the 2nd layer of moulded resin by hardening again.
Certainly, if do not consider cost, be full of by the 1st layer of moulded resin 16 in the resin box 20 and constitute neither.
The formation of＜A-1-2. tipper 〉
Before the explanation of tipper 15, the situation occurred to the crackle of soldering-tin layer generation under the substrate uses Fig. 2 and Fig. 3 to describe.
Fig. 2 is for the partial cross section figure in the formation of preparing with comparison of the present invention that does not have tipper 15, and the formation identical with semiconductor device shown in Figure 1 100 used identical symbol, omits repeat specification.
As shown in Figure 2, insulated substrate 2 reaches interarea at the following interarea of ceramic matrix material 3, has back side pattern 5 and circuit pattern 4 respectively, the edge part generation crackle 18 of soldering-tin layer 7 under the substrate of connection back side pattern 5 and radiator 1.
Here, Fig. 3 represents the plan view of the generation area of crackle.Fig. 3 is, the ideograph of the generation area 180 of the crackle when insulated substrate 2 is seen in the top on radiator 1, carries out ultrasonogram image diagnosis and analysis of sections to the insulated substrate 2 that crackle takes place, and specifies crackle generation area 180.In addition, only represented insulated substrate 2 by the wheel Guo shape of ceramic matrix material 3, circuit pattern 4 omissions such as grade among Fig. 3.
As shown in Figure 3, crackle concentrates on the zone of bottom, tetragonal bight correspondence that plan view is shaped as the ceramic matrix material 3 of rectangle, and in other zones, crackle does not take place basically.
The inventor concentrates the fact of the bottom, tetragonal bight that occurs in ceramic matrix material 3 according to crackle, infers the generation of crackle and the reason of expansion.
That is, be 7～8ppm/K for the thermal coefficient of expansion of insulated substrate 2, the thermal coefficient of expansion of radiator 1 is 16～17ppm/K.Under the state of so differentiated material of thermal coefficient of expansion,, then intensity has been applied pressure than weak part owing to thermal stress if apply thermal cycle repeatedly.This occasion, soldering-tin layer 7 is that intensity is the most weak under the substrate, after being under pressure, this pressure is starting point generation crackle and expansion in the textural bight that concentrates on the bight.
The inventor verified according to a nearly step of this inference, find because the thermal coefficient of expansion of insulated substrate and radiator poor, both connecting portions, be actually the edge part of soldering-tin layer under the substrate, particularly split between the edge part in bight and the radiator, the big deflection of soldering-tin layer generation is the occurrence cause of crackle under substrate.
Obtain following technological thought according to this result, promptly split between edge part by preventing the bight of soldering-tin layer 7 under the substrate and the radiator 1, can prevent the generation of crackle.Then, the concrete formation that realizes this technological thought the best is a tipper 15.
Here, Fig. 4 is that the plane of the semiconductor device shown in Figure 1 100 seen from the top of insulated substrate 2 of expression constitutes.In addition, among Fig. 4 in order to simplify omissions such as semiconductor element 6 on the circuit pattern 4 shown in Figure 1 and enclosure 10.
As shown in Figure 4, in the surface of the radiator 1 of the outside correspondence of tetragonal bight 3c of ceramic matrix material 3, tipper 15 is set independently respectively.To the length that is provided with of tipper 15, an end that makes tipper 15 is to the length of bend during for (being called angular length) L, and when the flat shape of ceramic matrix material 3 was S square for length on one side, length L was set at 1/3rd to 1/6th of length S.By being set to this scope, can reliably suppress the generation of crackle.
In addition, the tetragonal bight 3c of ceramic matrix material 3, formation has curvature respectively, and this bend forms the L word shape that has same curvature with bight 3c, makes each tipper 15 expand along the profile of bight 3c.
Then, the section constitution of representing the Width of tipper 15 with Fig. 5.
Among Fig. 5, tiltangle is represented the angle of inclination to the horizontal plane of groove inwall, and tipper degree of depth h represents the degree of depth of the interarea of radiator 1 to the bottom surface, the width of tipper width 1 expression groove bottom.
In addition, respectively to tiltangle, tipper degree of depth h and tipper 1 have been represented optimum value range among Fig. 5.Specifically, tiltangle is 90 °～110 ° (wishing above 90 °), and tipper degree of depth h is 0.15mm～2.1mm, and tipper width 1 is 1.0mm～3.0mm.
Among Fig. 5, at the position of soldering-tin layer under the substrate 7 and tipper 15 relation expression together, an edge of the groove width direction of the peristome of tipper 15 be arranged to substrate under the position of top basically identical on slope of soldering-tin layer 7.
Promptly, when being connected with the radiator 1 of insulated substrate 2, the scolding tin that dissolves extends, also near the edge part of tipper 15, and the expansion of calculating this scolding tin, setting by determining tipper 15 is so that the edge of tipper 15 in the position that the scolding tin expansion stops, during soldering-tin layer 7, forms formation as shown in Figure 5 under this scolding tin solidify out into substrate.
Adopt such formation, can improve the adhesiveness of the 1st layer of moulded resin 16 and radiator 1, can suppress the scolding tin crackle of the bight generation of insulated substrate 2.
That is, in the resin box 20 in if fill the 1st layer of moulded resin 16, then the inwall of the inclination of the inboard to tipper 15 in and the zone, inclination angle of bottom surface defined also have the 1st layer of moulded resin 16 to enter.
Here, because the thermal stress that thermal cycle causes, the edge part of soldering-tin layer 7 under substrate, during the direction generation deflection of particularly splitting between the edge part in bight and the radiator 1, the last direction of Fig. 5 (relatively with the vertical direction of the interarea of radiator to) and down direction (vertical lower of the interarea of relative and radiator to) though acting on effectively, but it is bonding with the inwall of inboard inclination to tipper 15 in to enter the 1st layer of moulded resin 16 in zone, above-mentioned inclination angle, is not easy to peel off.Here, with substrate under bonding the 1st layer of moulded resin 16 in the slope of soldering-tin layer 7 also identical.
In addition, the 1st layer of bonding moulded resin 16 of inwall that tilts with inboard in tipper 15, the power that acts in the last direction with respect to Fig. 5, stronger adhesiveness is arranged, the 1st layer moulded resin 16 bonding with 7 slopes of soldering-tin layer under the substrate, the power that acts in the following direction with respect to Fig. 5 has stronger adhesiveness, as a result, can prevent to split between the edge part of soldering-tin layer 7 under the substrate and the radiator 1.
In addition, tipper 15 can prevent effectively that also the scolding tin that dissolves from flowing into groove inside.That is, the cross sectional shape at the edge of the groove width direction of the peristome of tipper 15 has the shape of edge shape.Like this, in the rapid changing unit of shape, the surface tension inhibition expansion by scolding tin can prevent that scolding tin from flowing into the inside of tipper 15.In other words, tipper 15 also means the scolding tin and the diffusion that can prevent to flow out cushion.
Determining of the optimum value of each factor of formation of＜A-1-3. tipper 〉
Then, the basis to the optimum value of each factor of formation (tiltangle, tipper degree of depth h and tipper width 1) of tipper 15 describes with Fig. 6 and Fig. 7.
Fig. 6 is expression, change tiltangle (°) time substrate under the occurrence degree results measured figure of crackle in the moulded resin in the progress degree of crackle of soldering-tin layer 7 and bight.
The progress degree of the crackle of soldering-tin layer 7 under the substrate as shown in Figure 6, the big more expression crack progress of numerical value (arbitrary unit) is easier, and the more little expression crack progress of numerical value is difficult more.
Then, as shown in Figure 6, the inclination angle is in 0 °～90 ° scope, and the progress degree of crackle is along with the increase at inclination angle sharply diminishes, and the inclination angle is more than 90 °, and the progress degree of crackle does not change like that, remains minimum basically.
In addition, as shown in Figure 6, the occurrence degree of crackle in the moulded resin in expression bight, the big more crackle of numerical value (arbitrary unit) is easy to generate more, the numerical value crackle life of having difficult labour more more.
Then, as shown in Figure 6, the inclination angle is in 0 °～110 ° scopes, and the crackle occurrence degree is along with the increase at inclination angle slowly increases, if the inclination angle surpasses 110 °, the occurrence degree of crackle sharply increases.From above measured result, the scope of the optimum value of tiltangle is 90 °～110 °.
In addition, characteristic as shown in Figure 6, variation that can't see the length-width ratio (h/l) to tipper has dependence.
Fig. 7 is when changing the length-width ratio (h/l) of the tipper degree of depth h of tipper 15 and tipper width l, the figure of measured result when the progress degree of the crackle of soldering-tin layer 7 is 90 ° at the inclination angle under the substrate and 110 ° the time.
As shown in Figure 7, no matter the length-width ratio of tipper is any inclination angle then if surpass 0.1, and the progress degree change of crackle slows down, and length-width ratio is if surpass 0.5, and then the progress degree of crackle is kept minimum.From this measured result as can be known, the scope of the optimum value of length-width ratio is 0.15～0.7.
＜A-2. effect 〉
As described above, in the semiconductor device 100 of present embodiment, in the interarea of the radiator 1 of the edge part outside of the ceramic matrix material 3 that constitutes insulated substrate 2, basically along the periphery of ceramic matrix material 3, the tipper 15 that inwall tilts to the inside is set, cover wire bond with the lower part by the 1st layer of moulded resin 16, thereby, by entering the 1st layer of moulded resin 16 of tipper, can prevent to split between the edge part of soldering-tin layer 7 under the substrate and the radiator 1, prevent under the substrate that crackle produces and the crackle diffusion in the soldering-tin layer 7.
As a result, be subjected to thermal cycle and soldering-tin layer 7 produces under substrate deflection eases down to the about 40% of deflection when using leaded scolding tin, can guarantee to substrate under soldering-tin layer 7 use the durability of thermal cycle equal when leaded, and keep reliability.
In addition, in the semiconductor device 100 of present embodiment, do not add the thickness of soldering-tin layer 7 under the thick substrate, thickness with attenuate radiator 1, radiator 1 does not use the low material of thermal coefficient of expansion especially yet, thereby can realize suppressing thermal resistance and guaranteeing thermal endurance, and suppresses the rising of manufacturing cost.
In addition, as shown in Figure 4, tipper 15 is independent respectively setting in the surface of the corresponding radiator 1 in the tetragonal bight 3c outside of ceramic matrix material 3, only needs necessary minimal tipper processing to get final product, and can suppress to follow the increase of tipper cost of processing.
＜A-3. variation 1 〉
More than among Shuo Ming the embodiment, tipper 15 independently is provided with formation respectively in the 3c outside, tetragonal bight of ceramic matrix material 3, also can be arranged to the tipper of ring-shaped continuous around ceramic matrix material 3.
Fig. 8 is illustrated in the outside tipper 15A (continuous tilt groove) that is provided with continuously of edge part of ceramic equipment 3.
By tipper 15A is set, around ceramic matrix material 3, soldering-tin layer 7 can prevent to flow out the scolding tin and the diffusion of cushion when dissolving state under the substrate.Each factor of the formation of tipper 15A is except that angular length degree L, and is identical with tipper 15.
＜A-4. variation 2 〉
More than among Shuo Ming the embodiment, the 3c outside, tetragonal bight of ceramic matrix material 3 is provided with one by one respectively and constitutes, and also can be concentric multiple row setting.
Fig. 9 is 3 tipper 15 and 15B that tetragonal bight 3c external concentric shape is provided with that are illustrated in ceramic matrix material 3.
Like this, be provided with, more can improve the adhesiveness of the 1st layer of moulded resin 16 and radiator 1 by concentric shape multiple row.
＜A-5. variation 3 〉
As shown in Figure 4, the 3c outside, tetragonal bight of ceramic matrix material 3, when independently tipper 15 being set respectively, such as previously explained, be provided with the part of tipper 15, when soldering-tin layer under the substrate 7 when dissolving state, can prevent to flow out scolding tin and diffusion, but can not effectively prevent the outflow of 15 scolding tin of tipper above necessary amount.
Thereby, as shown in figure 10, on radiator 1 interarea of 15 correspondences of tipper, cover solder resist 30 and constitute, can effectively prevent the outflow of scolding tin.
Soldering-tin layer 7 is the scolding tin diffusion when dissolving state under the calculating substrate, determines the setting of solder resist 30, makes the edge of solder resist 30 be positioned at scolding tin diffusion stop position.Basically, the edge of the groove width direction of tipper 15 and the edge of solder resist 30 Widths linearly can be set up in parallel.
In addition, as the material of solder resist 30, be exemplified as epoxy resin and epoxy acrylate etc., can select the material of solder resist 30, making the surface of solder resist 30 and the cementability of the 1st layer of moulded resin 16 is good value.
The manufacture method of the tipper of＜A-6. punch process 〉
More than among Shuo Ming the embodiment, tipper uses inclined cutter to carry out cut and forms, and has short feature process time, also can form by punch process.
Below, use Figure 11 and Figure 12, the method that forms tipper by punch process is described.
At first, as shown in figure 11, to have with inclination groove width 1 equal widths and reach the height identical, possess and should form the diel P1 that tipper has the protuberance D1 of same level view shape with tipper degree of depth h, be stamped into the assigned position of the tipper that should form radiator 1, form the vertical groove 151 of inwall.Figure 11 is the state that diel P1 is lifted in expression.
Then, as shown in figure 12, will possess, punching press will be carried out on the top of groove 151 than the only wide α of inclination groove width 1 and high for β, the diel P2 of the protuberance D2 of same level view shape is arranged with the tipper that should form.At this moment, protuberance D2 evenly covers the peristome of groove 151.Figure 12 represents to lift the state of diel P2.
Its result is only carried out volume to the inboard of groove and is moved in the top of the inwall of the groove 151 of the protuberance D2 punching press of wide α than inclination groove width 1, obtains the tipper 15 that inwall tilts to the inside.
In addition, above-mentioned width α is set at 1/3rd length of about inclination groove width, specifically, is set in the scope of 0.4mm～1.0mm.
In addition, height β is set at 1/3rd the length of about tipper degree of depth h, specifically, is set in the scope of 0.05mm～0.7mm.
In addition, each factor of tipper (tiltangle, inclination groove width l, tipper degree of depth h and angular length L) is also identical when cut forms.
Punch process forms tipper, is particularly conducive to the outside, tetragonal bight that tipper independently is arranged on ceramic matrix material respectively.
Promptly, curvature as the bight of ceramic matrix material is identical, then for the ceramic matrix material of all size and shape (square and rectangle), can use above-mentioned diel P1 and P2 jointly, can suppress the Mold Making expense, suppress the increase of the manufacturing cost of semiconductor device integral body.In addition because stamped area is limited in the narrow and small scope, stamping pressure very little just can, do not use large-scale decompressor just can finish, can suppress the increase of manufacturing cost.
For example, expression is an example with 2 kinds of ceramic matrix materials 31 and 32 of the different similar figures of area among Figure 13, can use a mold jointly.
Represent among Figure 13, outside, tetragonal bight at the little ceramic matrix material 31 of area, dispose the state that diel P11, P12, P13 carry out punching press respectively, with in the outside, tetragonal bight of the big ceramic matrix material 32 of area, dispose the state that diel P11, P12, P13 and P14 carry out punching press respectively.
For example, after forming tipper by punch process in the semiconductor device of the ceramic matrix material 31 that usable floor area is little, when carrying out punch process in the semiconductor device of the ceramic matrix material 32 that usable floor area is big, diel P11, P12, P13 and P14 are slided at directions X and Y direction, be set to the outside, tetragonal bight of ceramic matrix material 32, can carry out ceramic matrix material 32 pairing punch process.
In addition, diel P11, P12, P13 and P14, be and the pairing mould of diel P1 shown in Figure 11, Figure 13 represents stamping procedure shown in Figure 11, also identical in the stamping procedure shown in Figure 12, if prepare diel one cover that uses in diel one cover that uses in the stamping procedure shown in Figure 11 and the stamping procedure shown in Figure 12, can be corresponding to the ceramic matrix material of all size and shape (square and rectangle).
Claims (9)
1. semiconductor device possesses:
The rectangular-shaped insulated substrate of semiconductor element mounted thereon;
The radiator that its interarea is connected with above-mentioned insulated substrate;
With the resin box of above-mentioned radiator as the bottom surface;
Be filled into the hardening resin in the above-mentioned resin box,
The above-mentioned interarea of above-mentioned radiator and being connected of above-mentioned insulated substrate be by
Constitute that the lead-free soldering tin layer that forms between the above-mentioned interarea of the ceramic matrix material of above-mentioned insulated substrate and above-mentioned radiator realizes,
Above-mentioned radiator,
Have and be arranged at least in the above-mentioned interarea corresponding, along the tipper that above-mentioned bight is expanded and its inwall tilts to the inside with the outside, tetragonal bight of above-mentioned ceramic matrix material.
2. the described semiconductor device of claim 1 is characterized in that:
Above-mentioned tipper is configured to one of them edge of the groove width direction of its peristome, and is consistent with the apical position on the slope of above-mentioned lead-free soldering tin layer.
3. the described semiconductor device of claim 1 is characterized in that:
In the above-mentioned tipper,
With respect to the angle of inclination of the horizontal plane of above-mentioned inwall be more than 90 ° to 110 ° scope,
Groove depth is 0.15 to 0.7 scope with respect to the length-width ratio of the width of groove bottom.
4. the described semiconductor device of claim 1 is characterized in that:
Above-mentioned tipper is provided with along above-mentioned tetragonal bight respectively, comprises the independent inclination groove that a plurality of flat shapes are the L font.
5. the described semiconductor device of claim 4 is characterized in that also possessing:
The solder resist that is provided with for the above-mentioned interarea that covers the above-mentioned radiator between adjacent above-mentioned independent inclination groove.
6. the described semiconductor device of claim 4 is characterized in that:
The flat shape of above-mentioned independent inclination groove, its bend are the L font with curvature, two groove ends to the length of above-mentioned bend be respectively above-mentioned ceramic matrix material an edge lengths 1/3rd to 1/6th.
7. the described semiconductor device of claim 1 is characterized in that:
Above-mentioned tipper,
Be set to ring-type continuously for surrounding above-mentioned ceramic matrix material.
8. the described semiconductor device of claim 1 is characterized in that,
Above-mentioned hardening resin comprises 2 layers of resin construction: the 1st layer of resin that fill until the height that covers the bonding wire (bonding wire) on the above-mentioned insulated substrate the above-mentioned bottom surface in above-mentioned resin box; The 2nd layer of resin of on above-mentioned the 1st layer of resin, filling,
Above-mentioned the 1st layer of resin compared with above-mentioned the 2nd layer of resin, and linear expansion coefficient and crooked elastic rate are low, and the concentration of sodium ion that contains and halide ion is also low.
9. the manufacture method of the described semiconductor device of claim 4,
Above-mentioned independent inclination groove, by
With respect to the vertical groove of inwall with groove bottom width, groove depth and plan view shape identical with above-mentioned independent inclination groove, with having than wideer width of the groove width of this groove and the diel that has with the protuberance of above-mentioned independent inclination groove same level view shape to come punching press is carried out on the top of above-mentioned groove, make the upper inside wall of above-mentioned groove move and form to the interior Side Volume of above-mentioned groove.
Applications Claiming Priority (2)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP2004175074A JP4722415B2 (en) | 2004-06-14 | 2004-06-14 | Semiconductor device and manufacturing method thereof |
| JP175074/04 | 2004-06-14 |
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| Publication Number | Publication Date |
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| CN1716578A CN1716578A (en) | 2006-01-04 |
| CN100377336C true CN100377336C (en) | 2008-03-26 |
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| CN (1) | CN100377336C (en) |
Families Citing this family (14)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JP4985116B2 (en) * | 2007-03-08 | 2012-07-25 | 富士電機株式会社 | Semiconductor device and manufacturing method thereof |
| JP5252819B2 (en) * | 2007-03-26 | 2013-07-31 | 三菱電機株式会社 | Semiconductor device and manufacturing method thereof |
| JP2009188164A (en) * | 2008-02-06 | 2009-08-20 | Nippon Inter Electronics Corp | Semiconductor device |
| JP2011253950A (en) * | 2010-06-02 | 2011-12-15 | Mitsubishi Electric Corp | Power semiconductor device |
| US9287201B2 (en) * | 2010-12-16 | 2016-03-15 | Mitsubishi Electric Corporation | Semiconductor device |
| JP2014216459A (en) * | 2013-04-25 | 2014-11-17 | 三菱電機株式会社 | Semiconductor device |
| WO2015033515A1 (en) * | 2013-09-04 | 2015-03-12 | 三菱電機株式会社 | Semiconductor module and inverter device |
| DE102014214766A1 (en) * | 2014-07-28 | 2015-06-25 | Siemens Aktiengesellschaft | Method for producing a power module and power module |
| JP6500567B2 (en) * | 2015-04-01 | 2019-04-17 | 富士電機株式会社 | Semiconductor device |
| JP6771412B2 (en) * | 2017-03-16 | 2020-10-21 | 三菱電機株式会社 | Semiconductor device |
| JP6898203B2 (en) * | 2017-10-27 | 2021-07-07 | 株式会社 日立パワーデバイス | Power semiconductor module |
| WO2019176260A1 (en) * | 2018-03-13 | 2019-09-19 | 住友電気工業株式会社 | Semiconductor device |
| US11562977B2 (en) * | 2018-11-20 | 2023-01-24 | Mitsubishi Electric Corporation | Semiconductor device comprising a resin case and a wiring member that is flat in the resin case |
| JP7489181B2 (en) | 2019-11-11 | 2024-05-23 | 株式会社 日立パワーデバイス | Semiconductor Device |
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| JP2000183475A (en) * | 1998-12-21 | 2000-06-30 | Mitsubishi Electric Corp | Metal core substrate |
| CN1396667A (en) * | 2001-07-16 | 2003-02-12 | 诠兴开发科技股份有限公司 | Package of LED |
| US6607942B1 (en) * | 2001-07-26 | 2003-08-19 | Taiwan Semiconductor Manufacturing Company | Method of fabricating as grooved heat spreader for stress reduction in an IC package |
| US6661083B2 (en) * | 2001-02-27 | 2003-12-09 | Chippac, Inc | Plastic semiconductor package |
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- 2004-06-14 JP JP2004175074A patent/JP4722415B2/en not_active Expired - Lifetime
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Patent Citations (5)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JP2000183475A (en) * | 1998-12-21 | 2000-06-30 | Mitsubishi Electric Corp | Metal core substrate |
| US6661083B2 (en) * | 2001-02-27 | 2003-12-09 | Chippac, Inc | Plastic semiconductor package |
| CN1396667A (en) * | 2001-07-16 | 2003-02-12 | 诠兴开发科技股份有限公司 | Package of LED |
| US6607942B1 (en) * | 2001-07-26 | 2003-08-19 | Taiwan Semiconductor Manufacturing Company | Method of fabricating as grooved heat spreader for stress reduction in an IC package |
| US20030176020A1 (en) * | 2001-07-26 | 2003-09-18 | Pei-Haw Tsao | Grooved heat spreader for stress reduction in IC package |
Also Published As
| Publication number | Publication date |
|---|---|
| JP4722415B2 (en) | 2011-07-13 |
| JP2005353945A (en) | 2005-12-22 |
| CN1716578A (en) | 2006-01-04 |
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