CN219457608U - Electronic device - Google Patents

Abstract

The application discloses an electronic device, this electronic device includes: a base layer; a circuit disposed below the base layer and including a dielectric layer and a conductive layer disposed within the dielectric layer; a through hole penetrating through the base layer and connected to the circuit; the reinforcement is arranged in the base layer and beside the through hole, and the reinforcement is used for reducing the stress of the through hole on the dielectric layer. According to the technical scheme, at least the stress of the through hole on the dielectric layer can be reduced, so that the dielectric layer can be prevented from being broken.

Description

Electronic device

Technical Field

The present application relates to the field of semiconductor technology, and more particularly, to an electronic device.

Background

By using the TSV (Through Silicon Via) packaging technology, the data transmission paths among different core chips can be extremely shortened in a single package, and the advantages of improving the signal quality, improving the transmission efficiency, reducing the transmission noise interference problem and the like can be achieved. Meanwhile, because the transmission line between chips is greatly shortened and the transmission is completed in the package, the power consumption consumed by the transmission of the driving signals can be greatly reduced, and the chip transmission method is a chip transmission technical scheme. For example, the vertical electrical signal may be accomplished using TSV technology in 2.5D or 3D stacking technology.

Referring to fig. 1, in the conventional TSV technology, a silicon layer 10 is dry etched to the bottom to form a TSV 12.TSV 12 extends through silicon layer 10 and is connected by oxide layer 20 (e.g., siO ₂ Layer) of exposed wire 22. Also, an insulating layer 14 (e.g., a PI (polyimide) layer) is typically formed at the sidewalls of the TSV 12 for reducing leakage problems between the metal layer 16 of the TSV 12 and the silicon layer 10. However, whether oxide layer 20 is a thin layer (e.g., less than 1 μm thick) or a thick layer (e.g., about 5 μm thick), because of the relatively high CTE (coefficient of thermal expansion ) of insulating layer 14, expansion 50 tends to occur after hardening at high temperature, resulting in outward or inward stresses F1, F2 at the sidewalls of TSV 12 due to thermal expansion and contraction of insulating layer 14. It should be appreciated that since the insulating layer 14 also extends over the upper surface of the silicon layer 10, the stress F1 at the upper surface of the silicon layer 10 is greater than the stress F2 below. The expansion stresses F1, F2 create a moment with the height d (i.e., moment arm) of the sidewall of the TSV 12, which tends to create a large stress at the bottom corner 30 of the TSV 12, so that the structurally fragile oxide layer 20 tends to crack at the bottom corner 30 of the TSV 12.

Disclosure of Invention

In view of the above problems, the present application proposes an electronic device capable of at least suppressing stress caused by thermal expansion and cold contraction of an insulating layer.

The technical scheme of the application is realized as follows:

according to one aspect of the present application, there is provided an electronic device comprising: a base layer; a circuit disposed below the base layer and including a dielectric layer and a conductive layer disposed within the dielectric layer; a through hole penetrating through the base layer and connected to the circuit; the reinforcement is arranged in the base layer and beside the through hole, and the reinforcement is used for reducing the stress of the through hole on the dielectric layer.

In some embodiments, the through-hole includes a conductive element and an insulating layer separating the base layer from the conductive element, wherein the insulating layer connects the dielectric layer.

In some embodiments, the conductive element connects to the conductive layer.

In some embodiments, the stiffener is the same material as the insulating layer.

In some embodiments, the stiffener surrounds the through hole in a top view.

In some embodiments, the stiffener includes multiple portions that are separate from one another.

In some embodiments, the stiffener is connected to the insulating layer and forms an uneven surface with the insulating layer.

In some embodiments, a portion of the stiffener is integrally formed with the insulating layer as a unitary structure.

In some embodiments, a conductive line connecting the through holes is provided between adjacent two portions of the stiffener.

In some embodiments, the stiffener extends downward from the upper surface of the base layer and is spaced apart from the dielectric layer.

According to the technical scheme, the reinforcement piece is arranged beside the through hole, so that the stress of the through hole on the dielectric layer can be reduced, and the dielectric layer can be prevented from being broken.

Drawings

In order to more clearly illustrate the embodiments of the present application or the technical solutions in the prior art, the drawings that are needed in the embodiments will be briefly described below, and it is obvious that the drawings in the following description are only some embodiments of the present application, and that other drawings can be obtained according to these drawings without inventive effort for a person skilled in the art.

Fig. 1 is a schematic cross-sectional view of a prior art electronic device.

Fig. 2A is a schematic cross-sectional view of an electronic device according to an embodiment of the present application.

Fig. 2B is an enlarged partial cross-sectional view of the sidewall of the through hole and the stiffener of the electronic device shown in fig. 2A.

Fig. 3A is a schematic top view of the electronic device shown in fig. 2A at section A1-A1 according to one embodiment of the present application.

Fig. 3B and 3C are schematic top views of the electronic device shown in fig. 2A at section A1-A1, respectively, according to various embodiments of the present application.

Fig. 3D and 3E are top views of the electronic device shown in fig. 2A at section A2-A2 and not separately showing the layers and cover layers of the through via, respectively, according to various embodiments of the present application.

Fig. 4 is a schematic cross-sectional view of an electronic device according to another embodiment of the present application.

Fig. 5 is a schematic cross-sectional view of a through-hole connected to a conductive layer according to another embodiment of the present application.

Fig. 6 is a schematic cross-sectional view of an electronic device according to another embodiment of the present application.

Fig. 7A is a schematic cross-sectional view of an electronic device according to another embodiment of the present application.

Fig. 7B is a schematic top view of the electronic device shown in fig. 7A at section A3-A3 and without the individual layers of the through-holes shown separately.

Fig. 8A-8C are schematic cross-sectional views at various steps of forming an electronic device according to an embodiment of the present application.

Fig. 9 is a graph comparing stresses experienced by dielectric layers at room temperature and high temperature, respectively, for three different comparative electronic devices.

Detailed Description

The following description of the embodiments of the present application will be made clearly and fully with reference to the accompanying drawings, in which it is evident that the embodiments described are only some, but not all, of the embodiments of the present application. All other embodiments obtained by a person of ordinary skill in the art based on the embodiments in the present application are within the scope of the protection of the present application.

The following disclosure provides many different embodiments, or examples, for implementing different features of the provided subject matter. Specific examples of elements and arrangements will be described below to simplify the present disclosure. These are, of course, merely examples and are not intended to limit the utility model. For example, in the following description, forming a first component over or on a second component may include embodiments in which the first component and the second component are in direct contact, and may also include embodiments in which additional components are formed between the first component and the second component such that the first component and the second component may not be in direct contact. Moreover, the present utility model may repeat reference numerals and/or letters in the various examples. This repetition is for the purpose of simplicity and clarity and does not in itself dictate a relationship between the various embodiments and/or configurations discussed.

In addition, embodiments and features of embodiments in this application may be combined with each other without conflict. The technical solutions of the present application will be described in detail below with reference to the accompanying drawings in combination with embodiments.

Embodiments of the present application provide an electronic device. Fig. 2A is a schematic cross-sectional view of an electronic device 100a according to an embodiment of the present application. Referring to fig. 2A, the electronic device 100a includes a base layer 110 and a circuit 120 disposed under the base layer 110. The circuit 120 includes a dielectric layer 121 and a conductive layer 123 within the dielectric layer 121. The electronic device 100a further comprises a through hole 130. The through hole 130 passes through the base layer 110 and connects the conductive layer 123 of the circuit 120. The electronic device 100a further includes a reinforcement member 140 disposed in the base layer 110 and beside the through hole 130, wherein the reinforcement member 140 can be used to reduce the stress of the through hole 130 on the dielectric layer 121.

Fig. 2B is a partially enlarged cross-sectional view of the sidewall of the through hole 130 and the stiffener 140 of the electronic device 100a shown in fig. 2A. Referring to fig. 2B, the expansion stresses F3 and F4 of the reinforcement 140 generate a moment with the height d' of the reinforcement 140, and the moment counteracts the partial moment generated by the stresses F1 and F2 of the through hole 130 and the height d of the through hole 130, so that the partial stress of the through hole 130 can be balanced, the stress at the bottom corner C1 of the through hole 130 is greatly reduced, and the dielectric layer 121 is prevented from being broken.

With continued reference to FIG. 2A, in some embodiments, the material of dielectric layer 121 is an oxide, such as SiO ₂ . The material of the conductive layer 123 may be any suitable conductive material. In some embodiments, the material of the base layer 110 may be Si.In embodiments where the material of the base layer 110 is Si, the through-holes 130 may be referred to as through-silicon vias. In some embodiments, the base layer 110 may be part of a chip. In other embodiments, other materials may be used for the base layer 110 and other structures may be suitable for forming the through-holes 130 therein.

The reinforcement 140 extends from the upper surface 110u of the base layer 110 toward the dielectric layer 121. The bottom surface of the stiffener 140 is spaced apart from the dielectric layer 121. The reinforcement member 140 may be formed by forming a groove in the upper surface 110u of the base layer 110 and then filling the material of the reinforcement member 140 in the groove. In some embodiments, the material of the stiffener 140 may be PI (polyimide). In other embodiments, any other suitable material may be used for reinforcement member 140.

The reinforcement 140 extends to a depth within the base layer 110 less than the depth of the through-hole 130. In some embodiments, the reinforcement member 140 may extend within the base layer 110 to a depth that is 1/2 the depth to which the through-hole 130 extends within the base layer 110. The reinforcement 140 and the through-hole 130 may be spaced apart in the lateral direction by the base layer 110. In some embodiments, the width of the reinforcement 140 in the lateral direction is less than the width of the through-hole 130. The reinforcement member 140 may also have any other suitable dimensional configuration.

Specifically, the through-hole 130 may include a conductive element 132, and an insulating layer 134 separating the base layer 110 from the conductive element 132. The insulating layer 134 may be disposed along sidewalls of the through-hole 130, and the insulating layer 134 exposes the conductive layer 123. In some embodiments, insulating layer 134 may connect conductive layer 123. In some embodiments, insulating layer 134 may be connected to dielectric layer 121.

The electronic device 100a further includes an insulating layer 112, the insulating layer 112 being disposed on the upper surface 110u of the base layer 110. The insulating layer 112 may cover the upper surface 110u. The insulating layer 112 may connect the insulating layer 134 of the through hole 130 and the reinforcement 140. In some embodiments, the insulating layer 112 on the upper surface 110u of the base layer 110, the insulating layer 134 of the through-hole 130, and the reinforcement 140 are integrally formed as a unitary structure (as described below with reference to fig. 8A-8C). In such an embodiment, the insulating layer 112 on the upper surface 110u of the base layer 110, the insulating layer 134 of the through-hole 130, and the stiffener 140 are all the same material, e.g., PI.

Conductive element 132 may be disposed along the top surfaces of insulating layer 134 and conductive layer 123. Conductive element 132 connects to and contacts conductive layer 123. The electronic device 100a further includes a metal layer 114, the metal layer 114 being disposed on the insulating layer 112. The conductive element 132 may be connected to the metal layer 114 over the insulating layer 112, as required for electrical connection.

In addition, the electronic device 100a further includes a cover layer 136, the cover layer 136 being disposed on the conductive element 132 and over the upper surface 110u of the base layer 110. In some embodiments, the material of the cover layer 136 may be the same as the insulating layer 134, e.g., PI is the material of both the cover layer 136 and the insulating layer 134.

Fig. 3A is a schematic top view of the electronic device 100a shown in fig. 2A at section A1-A1 according to one embodiment of the present application. Wherein the respective insulating layers 134 and conductive elements 132 of the through-holes 130 are not separately shown for simplicity. In the top view of fig. 3A, the reinforcement 140 surrounds the through hole 130. In the present embodiment, the reinforcement 140 continuously surrounds the through-hole 130. In a plan view, the through hole 130 may have a circular shape, and the reinforcement 140 has an annular shape.

Fig. 3B and 3C are schematic top views of the electronic device 100a shown in fig. 2A at section A1-A1, respectively, according to various embodiments of the present application. Wherein the respective insulating layers 134 and conductive elements 132 of the through-holes 130 are not separately shown for simplicity. Referring to fig. 3B and 3C, in some embodiments, the reinforcement member 140 may include a plurality of portions 140p that are separated from one another. The plurality of portions 140p are discontinuously arranged around the through hole 130 in a plan view. In some embodiments, portions 140p of reinforcement 140 may have the same shape and size in top view, as shown in fig. 3B. In some embodiments, portions 140p of reinforcement 140 may have different shapes and sizes in a top view, as shown in fig. 3C. In some embodiments, the spacing between each two adjacent portions 140p may be the same or different.

Fig. 3D and 3E are top views of the electronic device 100a shown in fig. 2A at section A2-A2, respectively, according to various embodiments of the present application. Wherein, for simplicity, the respective insulating layers 134 and conductive elements 132 of the through-holes 130 are not shown separately, and the cover layer 136 is not shown. Referring to fig. 3D and 3E, a conductive line 118 connecting the through holes 130 may be provided between adjacent two portions 140p of the reinforcement member 140. In some embodiments, the conductive line 118 may be formed from the metal layer 114 shown in fig. 2A.

Fig. 4 is a schematic cross-sectional view of an electronic device 100b according to another embodiment of the present application. In contrast to the electronic device 100a shown in fig. 2A, in the electronic device 100b, at least one electrode 152 may be provided at the upper surface 110u of the base layer 110. Here, two electrodes 152 are illustrated as example, and the two electrodes 152 are a first electrode 152a and a second electrode 152b, respectively, and the first electrode 152a and the second electrode 152b may be located at both sides of the through hole 130 and the reinforcement 140, respectively. The first electrode 152a and the second electrode 152b are exposed from the upper surface 110u of the base layer 110. The first electrode 152a and the second electrode 152b are provided with the metal layer 114, respectively. The metal layer 114 passes through the insulating layer 112 over the base layer 110 to be connected to the first electrode 152a and the second electrode 152b, respectively. The metal layer 114 on the first electrode 152a may be electrically connected to the conductive element 132 of the through hole 130. The metal layer 114 on the second electrode 152b may not be connected to the conductive element 132 of the through hole 130. UBM (under bump metal) 154 is disposed on the metal layer 114 over the first electrode 152a and the second electrode 152b, respectively. UBM154 is exposed by capping layer 136. The pad 156 is disposed over the UBM 154.

In the embodiment shown in fig. 4, the material of the reinforcement 140 may be the same as the cover layer 136. In this embodiment, the reinforcement 140 and the cover 136 may be an integrally formed unitary structure. Other aspects shown in fig. 4 may be similar to those described with respect to fig. 2A and are not repeated here.

Fig. 5 is a schematic cross-sectional view of a through via 130 connected to a conductive layer 123 according to another embodiment of the present application. As shown with reference to fig. 5, the through-hole 130 and the conductive layer 123 may not be in contact, but connected to the conductive layer 123 through a plurality of connection lines 125 extending vertically on the conductive layer 123. The plurality of connection lines 125 and the conductive layer 123 are buried in the dielectric layer 121, and the plurality of connection lines 125 are exposed by the dielectric layer 121. In the present embodiment, the insulating layer 134 of the through hole 130 is connected to the dielectric layer 121. The connection method between the through hole 130 and the conductive layer 123 shown in fig. 5 can be applied to the electronic device 100a shown in fig. 2A, for example.

Fig. 6 is a schematic cross-sectional view of an electronic device 100c according to another embodiment of the present application. Referring to fig. 6, the reinforcement 140 is connected with the insulating layer 134 of the through-hole 130, and the reinforcement 140 forms an uneven surface with the insulating layer 134. Specifically, the insulating layer 134 of the through-hole 130 and the reinforcement 140 form a stepped uneven surface. Since the reinforcement 140 forms an uneven surface with the insulating layer 134 of the through-hole 130, stress caused by the through-hole 130 can be dispersed.

Specifically, in the present embodiment, the reinforcement member 140 includes a first portion 141 disposed along a sidewall of the reinforcement member 140 away from the through hole 130 and along a bottom surface of the reinforcement member 140, and a second portion 142 disposed in a remaining space of the reinforcement member 140. In some embodiments, the material of the first portion 141 may be the same as the insulating layer 134 of the through-hole 130. The first portion 141 of the reinforcement 140 and the insulating layer 134 may be an integrally formed unitary structure. The sidewall of the second portion 142 may contact the conductive element 132 of the through hole 130. In some embodiments, the material of the second portion 142 may be the same as the material of the cover layer 136. In some embodiments, the reinforcement 140 continuously surrounds the through-hole 130. In other embodiments, the reinforcement 140 may discontinuously surround the through-hole 130.

Fig. 7A is a schematic cross-sectional view of an electronic device 100d according to another embodiment of the present application. Similar to fig. 6, the reinforcement 140 is connected with the insulating layer 134 of the through-hole 130, and the reinforcement 140 forms a stepped uneven surface with the insulating layer 134. Since the reinforcement 140 forms an uneven surface with the insulating layer 134 of the through-hole 130, stress caused by the through-hole 130 can be dispersed.

Further, in the electronic device 100d, the reinforcement member 140 is entirely formed of a uniform material and is connected to the insulating layer 134 of the through-hole 130. In some embodiments, the stiffener 140 may be the same material as the insulating layer 134, e.g., PI. In this embodiment, the reinforcement member 140 and the insulating layer 134 may be integrally formed as a one-piece structure. In addition, the conductive element 132 of the through hole 130 is not in contact with the conductive layer 123, but is connected to the conductive layer 123 through a plurality of connection lines 125 extending vertically on the conductive layer 123. The plurality of connection lines 125 and the conductive layer 123 are buried in the dielectric layer 121, and the plurality of connection lines 125 are exposed by the dielectric layer 121. In the present embodiment, the insulating layer 134 of the through hole 130 is connected to the dielectric layer 121.

Fig. 7B is a schematic top view of the electronic device 100d shown in fig. 7A at section A3-A3.

Wherein the respective insulating layers 134 and conductive elements 132 of the through-holes 130 are not separately shown for simplicity. In the plan view shown in fig. 7B, the reinforcement 140 continuously surrounds the through hole 130. In other embodiments, the reinforcement member 140 may not continuously surround the through-hole 130.

Fig. 8A-8C are schematic cross-sectional views at various steps of forming an electronic device according to an embodiment of the present application. The various steps shown in fig. 8A-8C may be used, for example, to form the electronic device 100a shown in fig. 2A.

Referring to fig. 8A, a circuit 120 and a base layer 110 on the circuit 120 are provided. Wherein the circuit 120 comprises a dielectric layer 121 and a conductive layer 123 located in the dielectric layer 121, and a top surface of the conductive layer 123 is exposed by the dielectric layer 121. A groove 801 exposing the conductive layer 123 is formed in the base layer 110, and a groove 803 is formed beside the groove 801, for example, by performing a dry etching process. The depth of the groove 803 may be smaller than the groove 801. In some embodiments, the depth of groove 803 is 1/2 of the depth of groove 801. In some embodiments, the width of groove 803 may be less than the width of groove 801.

Referring to fig. 8B, an insulating material 812 is formed on the sidewalls of the recess 801, within the recess 801, and over the base layer 110. Wherein the insulating material 812 in the groove 801 forms the insulating layer 134 for the through-hole 130, and the insulating material 812 in the groove 803 forms the stiffener 140. Conductive material is then conformally plated in the recess 801 and over the insulating material 812 over the base layer 110, the plated conductive material forming the conductive elements 132 of the through-holes 130 and the metal layer 114 over the base layer 110. Conductive element 132 is connected to metal layer 114.

Referring to fig. 8C, a cover layer 136 is formed in the remaining space of the groove 801 and over the base layer 110. The material of the cover layer 136 may be the same as or different from the insulating material 812.

Fig. 9 is a graph comparing stresses experienced by dielectric layers at room temperature and high temperature, respectively, for three different comparative electronic devices. Specifically, three comparative examples in fig. 9 include: the existing electronic device 900a of comparative example 1, the electronic device 900b of comparative example 2, and the electronic device 100d shown in fig. 7A as comparative example 3. In the electronic device 900a of comparative example 1 and the electronic device 900b of comparative example 2, the reinforcing member 140 of the present application was not provided. The thickness of the base layer 110 of the electronic device 900b is reduced in the electronic device 900b of comparative example 2 as compared to the electronic device 900a of comparative example 1. The thickness of the base layer 110 in the electronic device 900a of comparative example 1 was 75 μm, and the thickness of the base layer 110 in the electronic device 900b of comparative example 2 was 40 μm. The electronic device 100d of comparative example 3 was provided with the reinforcing member 140, and the thickness of the base layer 110 was 75 μm.

The test result showed that the maximum stress to which the dielectric layer 121 was subjected at room temperature was 103.8MPa and the maximum stress to which the dielectric layer 121 was subjected at high temperature was 213.7MPa for the electronic device 900a of comparative example 1. The test results also show that the maximum stress point is located at the corner of the through hole 130, and the dielectric layer 121 is broken due to the large stress at high temperature. For the electronic device 900b of comparative example 2, the maximum stress to which the dielectric layer 121 was subjected at room temperature was 53.7MPa, and the maximum stress to which the dielectric layer 121 was subjected at high temperature was 138MPa. As can be seen from comparing comparative examples 1 and 2, the stress can be reduced by reducing the thickness of the base layer 110. However, while reducing the thickness of the base layer 110 may reduce stress, reducing the thickness of the base layer 110 may be disadvantageous in many cases.

For the electronic device 100d of comparative example 3, the stiffener 140 of the present application was provided, and the dielectric layer 121 thereof received a maximum stress of 48.6MPa at room temperature and 136.5MPa at high temperature. It can be seen that by providing the reinforcement 140 provided herein, the stress to which the dielectric layer 121 is subjected can be effectively reduced to avoid the dielectric layer 121 from being broken, without reducing the thickness of the base layer 110.

The foregoing description of the preferred embodiments of the present application is not intended to be limiting, but rather is intended to cover any and all modifications, equivalents, alternatives, and improvements within the spirit and principles of the present application.

Claims (10)

1. An electronic device, comprising:

a base layer;

a circuit disposed below the base layer and comprising a dielectric layer and a conductive layer within the dielectric layer;

a through hole penetrating through the base layer and connecting the circuit;

the reinforcement is arranged in the base layer and beside the through hole, and is used for reducing the stress of the through hole on the dielectric layer.

2. The electronic device of claim 1, wherein the electronic device comprises a plurality of electronic components,

the through hole comprises a conductive element and an insulating layer for separating the base layer and the conductive element, wherein the insulating layer is connected with the dielectric layer.

3. The electronic device of claim 2, wherein the electronic device comprises a plurality of electronic components,

the conductive element is connected to the conductive layer.

4. The electronic device of claim 2, wherein the electronic device comprises a plurality of electronic components,

the reinforcement is the same material as the insulating layer.

5. The electronic device of claim 1, wherein the electronic device comprises a plurality of electronic components,

in a plan view, the reinforcement surrounds the through hole.

6. The electronic device of claim 5, wherein the electronic device comprises a plurality of electronic components,

the reinforcement includes a plurality of portions separated from one another.

7. The electronic device of claim 2, wherein the electronic device comprises a plurality of electronic components,

the reinforcement connects the insulating layer and forms an uneven surface with the insulating layer.

8. The electronic device of claim 7, wherein the electronic device comprises a plurality of electronic components,

part of the reinforcement is integrally formed with the insulating layer as a unitary structure.

9. The electronic device of claim 6, wherein the electronic device comprises a plurality of electronic components,

and a conductive circuit connected with the through hole is arranged between two adjacent parts of the reinforcement piece.

10. The electronic device of claim 1, wherein the electronic device comprises a plurality of electronic components,

the stiffener extends downward from the upper surface of the base layer and is spaced apart from the dielectric layer.