CN100373589C - Method for reducing saucerization and etching of conductor structure in chemical mechanical lapping - Google Patents

Method for reducing saucerization and etching of conductor structure in chemical mechanical lapping Download PDF

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Publication number
CN100373589C
CN100373589C CNB2005100262575A CN200510026257A CN100373589C CN 100373589 C CN100373589 C CN 100373589C CN B2005100262575 A CNB2005100262575 A CN B2005100262575A CN 200510026257 A CN200510026257 A CN 200510026257A CN 100373589 C CN100373589 C CN 100373589C
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China
Prior art keywords
copper
contact hole
bias
dielectric layer
chemical mechanical
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Chinese (zh)
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CN1870244A (en
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王欣
白启宏
刘俊良
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Semiconductor Manufacturing International Beijing Corp
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Semiconductor Manufacturing International Shanghai Corp
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Abstract

The present invention relates to a method for reducing the saucerization and the etching of conductor structure in chemical mechanical lapping. Since the lapping velocities of copper in different zones are different, disk sinking and erosion in a copper conductor structure are generated during the later period in the lapping process of cupreous chemical machines. The present invention puts forward a method for reducing the disk sinking and the erosion of conductor structure in the lapping process of chemical machines, and the disk sinking and the erosion of copper are overcome by applying to reversal direct-current bias and balancing the lapping velocities of copper in the different zones.

Description

A kind of conductor structure dish that reduces in cmp falls into and the method that corrodes
Technical field
(Chemical Mechanical Polishing CMP), particularly relates to the chemical mechanical milling tech of the copper that has overcome saucerization to the present invention relates to semi-conductive cmp.
Background technology
Along with greatly with the development of very lagre scale integrated circuit (VLSIC), form and connect the metallic conductor between circuit in conductor and the semiconductor in interelement to have the characteristic of low-resistance value of high signal transmission more and more important; Copper makes it popular because of the low-resistance value that its low-resistivity reaches electric drift (electromigration) and stress hollow (stress voiding) character.
Cmp (CMP) processing procedure is commonly used to planarization copper or removes copper simultaneously and any material around it.The key of cmp processing procedure is the grinding rate of copper and material around.When being ground with a very fast grinding rate of copper conductor than soft-surface, just can cause the depression that occurs dish on the steel structure, promptly dish falls into (dishing) as shown in Figures 1 and 2, in follow-up processing procedure, because variable thickness causes the lead thicknesses difference, cause the resistance instability, influence device performance.Because of dish falls into the unevenness that is caused is to come from the cmp processing procedure for the different grinding rates of different materials and the grinding rate difference of same material zones of different, and this is a kind of challenge for semi-conductor industry.
In present metallochemistry mechanical lapping, comprise chemical action and physical action.In metallochemistry mechanical lapping, chemical action is even more important.By on wafer, adding Dc bias, can quicken or reduce the speed of metallochemistry mechanical lapping, control the processing procedure of metal better.
Summary of the invention
The purpose of this invention is to provide a kind of method that butterfly fell into and corroded (erosion) that in the chemomechanical copper grinding processing procedure, reduces; In the cmp processing procedure, add the chemical grinding speed of direct voltage in the step of removal partially conductive layer with balance zones of different copper.
The present invention reduces by a conductor structure dish and falls into and the method that corrodes in cmp, comprising:
Form first dielectric layer (ILD) on the substrate;
On dielectric layer, form a barrier layer (stop layer)
On the barrier layer, form second dielectric layer (IMD);
Form contact hole and contact hole via plug metal;
Etching forms ground floor (M1) metal wire contact hole;
Form a bronze medal layer, and insert in the contact hole to form conductive structure;
Cmp removes the partially conductive layer with planarization;
Apply reverse Dc bias in the process of lapping, the grinding rate of balance zones of different copper.
Apply reverse Dc bias on the conductive structure faster at grinding rate, make it stop to grind, do not apply reverse Dc bias on the slower conductive structure, continue to grind until flattening surface and grind.
Carry out the optical monitoring of lapping process in the chemical mechanical planarization process of the present invention, grind when copper is near terminal point faster, apply reverse Dc bias, make it stop to grind.Do not add reverse Dc bias and grind on the slower copper, continue to grind until all copper flattening surfaces.
Use chemical milling agent according to cmp step of the present invention, Si oxide wherein and copper generation chemical reaction make copper become copper ion on the copper surface; Because the reverse Dc bias that applies makes it stop to grind,
Advantage of the present invention is by applying reverse Dc bias control grinding rate zone faster, make copper and circumferential surface planarization thereof, eliminating the generation that dish falls into and corrodes.
The present invention also has an advantage to be owing to contain the oxide of silicon in the chemical milling agent, produces copper ion with copper generation chemical reaction, firmly is adsorbed on the copper surface and stops to grind under the effect of reverse biased, makes flattening surface.
Description of drawings
Fig. 1 produces the schematic diagram that dish falls in the conventional chemomechanical copper grinding process.
Fig. 2 is the enlarged drawing that the local dish of copper falls among Fig. 1.
Fig. 3 A~3E is the process schematic diagram that cmp of the present invention is realized planarization.
Fig. 4 is the schematic diagram of Comparative Examples.
Description of reference numerals
1 substrate, 2 first dielectric layers (ILD)
3 barrier layers (stop layer), 4 second dielectric layers (IMD)
5 metal plugs, 6 contact holes
7 bronze medal conductive layers, 8 copper conductors
9 floating copper
Embodiment
The present invention is described in detail below in conjunction with accompanying drawing.
As shown in Figure 1, because the copper metal is different with the other materials such as the cmp speed of oxide dielectric layers around it, copper is softer, therefore is easy to generate to corrode and cause the dish of copper to fall into and cave in.Its uneven degree can reach 100~500A.
According to the present invention, in cmp, reduce by a conductor structure dish and fall into and the method that corrodes, comprising: form first dielectric layer 2 (ILD) on the substrate 1; On first dielectric layer 2, form a barrier layer (stop layer) 3; On barrier layer 3, form second dielectric layer 4 (IMD); Etching forms contact hole and contact hole through hole on first dielectric 2 and second dielectric layer 4, forms plug metal 5 in the first dielectric layer part through hole; Form ground floor (M1) metal wire contact hole 6, as shown in Figure 3A; Cover a bronze medal layer 7, and insert in the contact hole 6 to form conductive structure, shown in Fig. 3 B; Cmp removes the partially conductive layer.
In the chemical mechanical planarization process of copper, because the grinding rate difference of zones of different copper, therefore shown in Fig. 3 C, form the imbalance of the thickness of copper, the grinding rate of floating copper 9 parts that need remove is slow, and the copper grinding rate in contact hole zone is fast, when the copper grinding in contact hole zone has reached terminal point, the floating copper zone that need remove is residual in addition, if can remove floating copper 9 parts though continue grinding, can cause the copper 8 generation losses of the formation lead of contact hole, comprise that the copper dish falls into and depression, as shown in Figure 4, its uneven degree can reach 100~500A, thereby influences the planarization and the device performance of metal connecting line.
The present invention adopts the method that applies reverse biased to prevent that the copper dish from falling into and the generation of depression.The oxide that in chemical mechanical planarization process, contains acid silicon in the used chemical milling agent, its copper metal with the surface produces chemical reaction becomes the surface of copper ion at copper, and when not applying reverse biased, copper can continue to grind to be removed.And in chemical mechanical planarization process by the optical monitoring method, can detect the lapping process of zones of different copper, when grinding rate zone faster, as near the copper the contact hole 8, during near grinding endpoint, shown in Fig. 3 C, can on substrate, apply reverse biased, shown in Fig. 3 D.Because the effect of reverse biased, the copper ion on regional 8 bronze medal surfaces is combined in the surface firmly, and is not removed.The reverse biased that is applied can be 5~200V, and relatively good is 100V, and the time that applies is 1~50S, is generally 25S.And floating copper zone 9 grinding rates in a big way that are on the dielectric layer are slow with respect to contact hole near zone 8, again since itself and substrate isolated by dielectric layer, therefore do not apply reverse biased on it, continue grinding and when the whole planarization in surface, stop to grind, shown in Fig. 3 E.The smooth degree of the air spots that the method according to this invention obtains is less than 100A.

Claims (6)

1. one kind is reduced the method that the conductor structure dish falls into and corrodes in cmp, comprises
Form first dielectric layer on the substrate;
On first dielectric layer, form a barrier layer;
On the barrier layer, form second dielectric layer;
Form contact hole and contact hole via plug metal, described contact hole and contact hole via etch are formed on first dielectric and second dielectric layer, and described plug metal is formed in the through hole of first dielectric layer part;
Etching forms ground floor metal wire contact hole;
Form a bronze medal layer, and insert in the metal wire contact hole to form conductive structure;
Cmp removes the partially conductive layer with planarization;
Apply reverse Dc bias in the process of lapping, the grinding rate of balance zones of different copper;
Add reverse Dc bias on the conductive structure faster at grinding rate, make it stop to grind, do not add reverse Dc bias on the slower conductive structure, continue to grind until flattening surface and grind.
2. method according to claim 1 is characterized in that, carries out optical monitoring in the described chemical mechanical planarization process.
3. method according to claim 1 is characterized in that, by optical monitoring, grinds when copper is near terminal point faster in the described chemical mechanical planarization process, applies reverse Dc bias.
4. method according to claim 1 is characterized in that, grinds on the slower copper in the described chemical mechanical planarization process and does not apply bias voltage.
5. method according to claim 1 is characterized in that, described cmp, grinding agent contain the oxide of acid silicon at least.
6. method according to claim 5 is characterized in that, the oxide of the silicon of described acidity can generate copper ion with the copper reaction.
CNB2005100262575A 2005-05-27 2005-05-27 Method for reducing saucerization and etching of conductor structure in chemical mechanical lapping Expired - Fee Related CN100373589C (en)

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* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN101740330B (en) * 2008-11-17 2011-12-07 中芯国际集成电路制造(上海)有限公司 Method for chemical mechanical polishing and forming through hole
CN109605210A (en) * 2019-01-23 2019-04-12 长江存储科技有限责任公司 A kind of grinding head and chemical-mechanical grinding device

Citations (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US20020088709A1 (en) * 2000-06-29 2002-07-11 Akihisa Hongo Method and apparatus for forming interconnects, and polishing liquid and polishing method
JP2002337025A (en) * 2001-03-16 2002-11-26 Ebara Corp Polishing liquid and polishing method
US20030183530A1 (en) * 2002-03-26 2003-10-02 Taiwan Semiconductor Manufacturing Co., Ltd. Method for integrating an electrodeposition and electro-mechanical polishing process
US20040009668A1 (en) * 2001-08-28 2004-01-15 Catabay Wilbur G. Process for planarizing upper surface of damascene wiring structure for integrated circuit structures
JP2004209588A (en) * 2002-12-27 2004-07-29 Ebara Corp Polishing apparatus and polishing method

Patent Citations (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US20020088709A1 (en) * 2000-06-29 2002-07-11 Akihisa Hongo Method and apparatus for forming interconnects, and polishing liquid and polishing method
JP2002337025A (en) * 2001-03-16 2002-11-26 Ebara Corp Polishing liquid and polishing method
US20040009668A1 (en) * 2001-08-28 2004-01-15 Catabay Wilbur G. Process for planarizing upper surface of damascene wiring structure for integrated circuit structures
US20030183530A1 (en) * 2002-03-26 2003-10-02 Taiwan Semiconductor Manufacturing Co., Ltd. Method for integrating an electrodeposition and electro-mechanical polishing process
JP2004209588A (en) * 2002-12-27 2004-07-29 Ebara Corp Polishing apparatus and polishing method

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Assignee: Semiconductor Manufacturing International (Beijing) Corporation

Assignor: Semiconductor Manufacturing International (Shanghai) Corporation

Contract fulfillment period: 2009.4.29 to 2014.4.29 contract change

Contract record no.: 2009990000626

Denomination of invention: Method for reducing saucerization and etching of conductor structure in chemical mechanical lapping

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Record date: 2009.6.5

Assignee: Semiconductor Manufacturing International (Beijing) Corporation

Assignor: Semiconductor Manufacturing International (Shanghai) Corporation

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Denomination of invention: Method for reducing saucerization and etching of conductor structure in chemical mechanical lapping

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