CN100364301C

CN100364301C - Parallel Turbo coding-decoding method based on block processing for error control of digital communication

Info

Publication number: CN100364301C
Application number: CNB031174744A
Authority: CN
Inventors: 万科; 陈庆春; 范平志
Original assignee: Southwest Jiaotong University
Current assignee: Southwest Jiaotong University
Priority date: 2003-03-17
Filing date: 2003-03-17
Publication date: 2008-01-23
Anticipated expiration: 2023-03-17
Also published as: CN1455565A

Abstract

The present invention discloses a parallel Turbo coding-decoding method based on block processing for error control of digital communication. With the present invention, when processing block encoding of an element of information, a coding end can set the initiation and final states of each coding block of parallel encoding by adding a block disassembling processing module, a block merging processing module, and a block encoding module with return-to-zero processing. A decoding end supports the high-speed parallel block decoding of the Turbo code by adding the block disassembling processing module, the block merging processing module, and two decoding elements which are formed by adopting a plurality of soft input and soft output decoding modules of the block encoding in component decoding. The initial values of a forward state and a backward state of each encoding block are all set as a zero state, the parallel coding-decoding method based on the block processing can ensure the reliability of the Turbo decoding as well as can greatly reduce the decoding delay of the Turbo code.

Description

Parallel Turbo coding and decoding method based on block processing for digital communication error control

Technical Field

The invention relates to an error correction coding and decoding method in a digital communication system, in particular to a parallel Turbo coding and decoding method based on block processing in a digital communication system adopting Turbo (Turbo) codes.

Background

In digital communication systems, particularly wireless digital communication systems, error correction codes play an important role in securing reliable communication and improving communication quality. Error correction codes are also widely used to reduce the bit error rate in computer storage and computing systems to extend the trouble-free run time of the computer.

C. Bernou, a. Glavie houshi (c. Berrou, a. Glavieux, et. Al.) et al, 1993in "near shannon limitator-coreflecting coding and decoding: turbo codes coding and decoding method was first proposed in "Proc.1993 Int. Conf.communication, pp.1064-1070" (near Shannon Limited error correction coding and decoding scheme: turbo codes ",1993 International Commission on communications, pp.1064-1070). The Turbo code encoder is formed by connecting two recursive systematic convolutional codes (RSC) in parallel through a random interleaver, and code words with different code rates are generated after the encoded check bits are subjected to puncturing and puncturing. Since the two RSC component encoders RSC1 and RSC2 perform concatenated coding in a parallel manner, such a Turbo code is also called a Parallel Concatenated Convolutional Code (PCCC). Turbo codes skillfully combine convolutional coding with a random interleaver,the idea of random coding is realized. In the decoding process, the Turbo code approaches the maximum likelihood decoding by iterative decoding: the Turbo code adopts a Soft input Soft output (SISO, soft-InSoft-Out) decoding module during decoding, and the Turbo code is formed by serially cascading two SISO decoding modules SISO1 and SISO 2; the decoding module SISO1 carries out soft input and soft output decoding on the component code RSC1 to generate likelihood ratio information about each bit in the information sequence, and the external information (ExtrinsicInformation) in the likelihood ratio information is used as the prior information of SISO2 when carrying out soft input and soft output decoding on the component code RSC2 after being subjected to interleaving processing; the decoding module SISO2 carries out soft input and soft output decoding on the component code RSC2 to generate likelihood ratio information about each bit in an interleaving information sequence, and after the outer information (ExtrinsicInformation) is subjected to de-interleaving processing, the outer information is used as prior information of the next SISO1 when the component code RSC1 carries out soft input and soft output decoding; after multiple iterations, the external information of SISO1 and SISO2 tends to be stable, and the likelihood ratio asymptotic value approaches the maximum likelihood decoding of the whole code. C. Simulation research of Bernoulli et al shows that the parallel cascade Turbo code based on (37, 21) component RSC encoder iterates when the encoding packet length is 65536 and the encoding code rate is 1/2When the times reach 18 times, the error rate is reduced to 10 ^-5 The signal-to-noise ratio required by the following system is only 0.7dB, and the performance close to the shannon limit is achieved. Because of its excellent error correction performance, turbo codes have been a hot spot in the field of error correction coding in recent years, and have gained a lot of results. One of the main areas of research is around the work of Turbo code iterative decoding algorithms. Up to now, decoding algorithms such as maximum a posteriori probability decoding (MAP) Algorithm (including standard BCJR Algorithm, LOG-MAP Algorithm in LOG domain and its simplified MAX-LOG-MAP Algorithm, M-BCJR and T-BCJR algorithms for reduced state search, sliding window SW-BCJR Algorithm, OSA Algorithm which reduces standard BCJR Algorithm to include only forward recursion, etc.), soft-output Viterbi Algorithm (SOVA, soft-output Viterbi Algorithm), etc. have been proposed in order.

In research, analysis andin understanding the performance of Turbo codes, it has been found that the performance of Turbo codes is determined by the minimum effective code distance dmm of the code words when the Signal-to-noise ratio (SNR) is high and the Bit Error Rate (BER) is low, i.e. the performance of Turbo codes tends to approach the asymptote line of dmin during the SNR increase, which means that the so-called error floor (error floor) of Turbo codes occurring when the SNR is high will depend on dmin. M. Breynelin and J.B. Chamaecyparis pisifera (M.BreilingandJ.B.Huber) studies in the paper "UpperbondionMinimum distances of Turbo codes", IEEE transaction on communications, vol.49, no.5, 2001, pp.808-815 ("Upper bound for minimum code distance of Turbo code", IEEE communications, vol.49, no.5, 2001, pp.808 to 815) indicate that the minimum code distance of Turbo code cannot be larger than the square root of the code length. In general, increasing the interleaving length of the interleaver and using an appropriate interleaving method can increase d _min Thereby obtaining better error correction performance.

Turbo codes, while exhibiting excellent system performance, are typically long in code length for better error correction performance in digital communication systems, as previously described. Because of the iterative decoding adopted by Turbo code decoding, along with the increase of the encoding length of the Turbo code, the storage amount required by a Turbo code decoding algorithm and the calculation amount of the iterative decoding are increased, and the decoding delay is increased.

In order to reduce the Turbo code decoding delay as much as possible and meet the real-time transmission requirement in a digital communication system, various methods are proposed in many patents and documents to try to reduce the iterative decoding delay of the Turbo code. One of the more common methods is to use a pipelined Turbo decoding structure. Obviously, when a plurality of processors are used for processing the decoding operation of each decoding module in the pipeline, the decoding operation is faster than the iterative decoding of the Turbo code realized by a single processor, so that the iterative decoding time delay of the Turbo code is reduced to a certain extent. C. Bernou, a. Glavie houshi (c.berrou, a.glavieux, et.al.) et al in "Near Shannon lim. it error-correcting and decoding: turbo codes, "Proc.1993 int.Conf. Communication, pp.1064-1070, (" Turbo code "near Shannon Limited error correction coding scheme," 1993 international congress of communications, pages 1064 to 1070) paper first presents a pipelined Turbo decoding structure. The European patent EP1024601 of "Pipelined architecture to decoder parallel and serial concatenated codes" of TRW INC (US), 2000-08-02 ("pipeline decoding architecture for parallel and serial concatenated codes (Turbo codes)", TRW Inc., 8.2.2000) also provides a pipeline type of cascaded iterative decoding architecture. Although the decoding structure of Turbo code can reduce decoding delay to a certain extent when a pipelined decoding structure is realized by adopting a plurality of processors, the processing delay of each soft input soft output decoding unit in the pipelined decoding structure is still difficult to reduce, and especially when the coding packet is longer, the pipelined Turbo code decoding structure still has larger decoding delay.

In studies to further reduce Turbo code decoding latency, xu jiaming and wang cheng liang (Jah-MingHsu, chi-liang wang) were studied in "aparallel decoding scheme for Turbo CODES", ISCAS'98, volume:4, 1998, pp.445-448 ("Turbo code parallel decoding scheme", IEEE conference on circuits and systems, 1998, volume 4, pages 445 to 448) proposes a parallel decoding method based on block processing. In the scheme, a decoding end divides a received Turbo code with the length of L into W blocks with equal length; when Turbo code is decoded, the first SISO decoding module SISO1 adopts W processors to execute SISO decoding on W blocks of the component code RSC1 in parallel to generate likelihood ratio information about each bit in a block information sequence, the SISO decoding module combines the likelihood ratio information and uses the outer information (externcicinformation) after interleaving processing as the second SISO decoding module SISO2 when the SISO decoding is executed on W blocks of the component code RSC2 in parallelPrior information of (2); the decoding module SISO2 carries out soft input and soft output decoding on the component code RSC2, combines the likelihood ratio Information of each bit in the interleaving Information sequence to generate likelihood ratio Information, and takes external Information (Extrinsic Information) in the likelihood ratio Information as prior Information of the next time SISO1 when the component code RSC1 is subjected to block soft input and soft output decoding; and obtaining the block maximum likelihood decoding of the whole code through multiple iterations. As each SISO decoding module in the method comprises W SISO decoding modules, and the coding length processed by each SISO decoding module is reduced to 1/W in a non-block scheme, the parallel decoding method based on block processing can obviously reduce the decoding delay of Turbo codes. U.S. Dashgupta and K.R. Nana south (U.S. Dasguba and K.R. Narayanan) the chunking and Quicking methods of Xunmaiming and Quangkungchan-Lianwang were followed in "parallel decoding of Turbo codes Using SoftOutputT-Algorithms", IEEEcommunications letters, vol.5, no.8, AUGUST2001, pp352-354 (parallel Turbo decoding Algorithm Using Soft output T Algorithm, IEEE communication prompter, vol.5, no.8, 2001, pp.352 to 354) papers, butAnd a T-BCJR algorithm capable of reducing state search is adopted to replace a MAP algorithm so as to further reduce the decoding delay of the Turbo code. Research shows that the Turbo decoding method based on block processing can delay the decoding of Turbo codes from O (2 LM 2) ^m Reduction of/P) to O (2 LM 2) ^m WP), where P is the processing rate of the processor (unit: operation times/second), M is the iteration times set during Turbo decoding, and M is the encoding storage of the Turbo code. When the block decoding processing is performed, the error correction performance of the Turbo code is lost to some extent. In order to reduce the performance loss due to block decoding, xujiaming and Wang Queen beams (Jah-MingHsu, chin-LiangWang) are reported in the article "APARALLELDECODING SCHEME FOR URBOCODES", ISCAS'98, volume:4, 1998, pp.445-448 ("parallel decoding scheme for Turbo codes", IEEE conference on circuits and systems, 1998, volume 4, pages 445 to 448) proposes the use of neighbors in blockingThe method of overlapping bits between blocks improves the error correction performance; research results show that the more the number of bits overlapped with each other between adjacent blocks in the blocking process, the smaller the performance loss caused by block decoding is, and the performance is gradually close to the decoding performance of the traditional non-blocking method. It is apparent that the reason why the block parallel decoding performance can be improved by considering overlapping bits with each other between adjacent blocks at the time of blocking is that each block can relatively accurately determine the state of each block in the overlapping region from the overlapping bits. Obviously, the more the number of overlapping bits is, the more accurate the judgment of the state of the overlapping region is, and when the number of overlapping bits is sufficient, the judgment result of the initial or ending state of each block in the overlapping region is substantially consistent with the judgment result of the non-block time, so that the parallel decoding of the blocks is close to the decoding performance of the traditional non-block time.

Chinese CN1288292 patent, luhong flag, and qu Binyu, "a serial/parallel concatenated convolutional code decoding module and decoding implementation method thereof", shenzhen china hua is a technology limited corporation, 09.13 days 1999, also proposes a block decoding method of similar Turbo code, which divides the received code into N blocks, and then performs forward and backward iterative decoding on each block by respectively adopting m forward and backward iterative decoding modules; and on the basis of the forward iterative decoding output and the backward iterative decoding output, combining to obtain a complete log-likelihood ratio decoding output. Chinese patent No. CN1328386A, xuyouyun, li, song waves, rohan, "parallel sliding window maximum posterior probability algorithm and its high-speed Turbo code decoding module", institute of telecommunication transmission of information industries, shanghai university of traffic, 26 months 12 2001, also provides a similar Turbo code division block parallel decoding algorithm, which focuses on performing a certain balance between the multi-sliding window block parallel decoding processing speed and the decoding memory requirement, thereby facilitating the programmable logic device to implement high-speed Turbo decoding. Both of the above two patents relate to block parallel decoding processing at the decoding end, and do not consider block coding with return to zero at the Turbo coding end and its effect on Turbo code parallel decoding based on block processing. Xu jiaming and Wang cheng Liang (Jah-Ming Hsu, chi-Liang Wang) and u. Darhsupta and k.r. Nana (u.dasgupta and k.r. Narayan) do not give quantitatively the relationship between the number of overlapping bits and the parallel iterative decoding performance of the Turbo code block, although they give a qualitative relationship between the number of overlapping bits and the parallel iterative decoding performance of the Turbo code block. From a large number of simulation results, the block parallel decoding algorithm based on the overlapped bits can provide a sufficiently reliable error correction performance only when the number of the overlapped bits is sufficiently large. Obviously, the Turbo code parallel iterative decoding method based on the adjacent block overlapping bits faces the following problems in the concrete implementation:

for the determined coding length N, if the transmission reliability required by the digital communication system is higher, the more bits are required to be overlapped between adjacent blocks to ensure the decoding performance; therefore, the decoding efficiency of the block Turbo code parallel decoding method based on the overlapped bits is also reduced.

Disclosure of Invention

The invention aims to provide a novel parallel coding and decoding method of Turbo codes based on block processing, which can greatly reduce the decoding delay of the Turbo codes and ensure the reliability of the Turbo decoding.

The invention solves the technical problem, and adopts the technical scheme that:

a parallel Turbo coding and decoding method based on block processing for digital communication error control is disclosed, wherein the coding end directly performs a first component recursive system convolutional coding on an information element to obtain a first component coding code element, performs an interleaving processing to generate an interleaving information element, performs a second component recursive system convolutional coding to obtain a second component coding code element, and performs a puncturing processing on the first component coding code element, the second component coding code element and the information element which is not subjected to the system convolutional coding to obtain a Turbo coding code element; the decoding end carries out buffer processing on the received Turbo coding code element, depuncture processing is carried out to obtain an information element, a first component coding code element and a second component coding code element, the information element, the first component coding code element and the second component coding code element are sent to M decoding units which are more than or equal to 1, and decoding output is obtained after decoding, interweaving and deinterlacing processing, the decoding end is characterized in that:

and a coding end: the information elements need to be subjected to coding preprocessing: firstly, directly partitioning and splitting the block into N blocks, and then carrying out convolution coding on a first component recursive system with return-to-zero processing; secondly, the interleaving information elements generated by interleaving processing are firstly divided into N blocks which are more than or equal to 2 in a partitioning mode, and then the second component recursive system convolutional coding with the zeroing processing is carried out; merging the obtained first component coding code element and the second component coding code element and the information element which is not subjected to the systematic convolutional coding, and then performing puncturing processing;

and a decoding end: after depuncturing, the information element, the first component code element and the second component code element are decoded and preprocessed, and then sent to M decoding units for decoding, wherein two components of each decoding unit respectively adopt N soft input and soft output decoding modules for parallel decoding processing, the number N of the parallel decoding modules is the same as the number of blocks split by the encoding end, the initial values of the forward state metric alpha and the backward state metric beta used by the decoding processing are zero, and the decoding unit performs corresponding block merging processing and block splitting processing on the external information obtained after the parallel decoding processing; and the decoding unit carries out corresponding block merging processing and de-interleaving processing to obtain decoding output.

The invention has the beneficial effects that: by properly adjusting the Turbo coding structure, a coding preprocessing module, a block splitting processing module, a block merging processing module and a block coding module with return-to-zero processing are added, and the coding end sets the starting state and the ending state of each coding block to be zero while realizing the block coding processing of information elements. When the decoding end obtains the coding blocks processed by the plurality of soft input soft output decoding modules in the two-component decoding through the splitting of the block splitting processing module and the block merging processing module, the initial and termination states of each block do not need to be estimated from overlapped bits like the traditional block decoding method. As the initial values of the forward state and the backward state of each coding block are set to be zero states, the parallel decoding method based on block processing can greatly reduce the decoding delay of the Turbo code while ensuring the reliability of the Turbo decoding. And because the block coding with the return-to-zero is adopted, the number of the added return-to-zero tail bits after each coding block at the coding end is determined, and the length of each corresponding coding block at the decoding end is uniquely determined when the block splitting is carried out, which is a characteristic of facilitating the practical system implementation.

The specific process of the coding preprocessing of the coding end is as follows:

if the length L 'of the information element cannot be divided by N, adding a known dummy information element at the tail end of the information element with the length L' by the encoding preprocessing to increase the length of the dummy information element to the minimum number L which can be divided by N, and writing the adding position and the number of the dummy information element into the control head information of the encoding packet; the decoding unit at the decoding end deletes the added pseudo information element before decoding output according to the control header information of the coding packet;

if the length L' of the information element can be divided by N, the coding preprocessing does not carry out any processing on the information element and writes the information into the control head information of the coding packet; the decoding unit at the decoding end does not perform any processing on the decoded output according to the control header information of the encoded packet.

The coding end can realize the matching between the information element length set by the system and the block number N by adding a coding preprocessing module. In practical implementation, even if L 'cannot be divided by N, considering that L' is generally larger and N is generally smaller, the number of redundant dummy information elements required to be added by the encoding preprocessing module is very small, and the arithmetic complexity of the algorithm is in the order of O (N).

The return-to-zero processing mode of the recursive system convolutional coding processing of the first component and the second component with return-to-zero processing is that the two component coding processing returns the block coding returning to the zero state to zero after block coding each information element to generate a first component block coding code element and a second component block coding code element and a return-to-zero bit for returning the first component block coding code element and the second component block coding code element to zero, the length of the first component block coding code element and the length of the second component block coding code element are L/N + m, and m is the coding storage length of an RSC coding module.

The block merging processing and the puncturing processing of the encoding end of the present invention can adopt the following modes:

1) The specific mode of the blocking and merging treatment is as follows:

a) Firstly, directly splitting an information element which is not subjected to systematic convolutional coding into N blocks, and adding return-to-zero bits of the first and second component codes of the N blocks which correspond to each other in sequence to the tail end of each information element block; outputting N information element blocks with the length of L/N +2 x m and the same length and containing return-to-zero bits;

b) Forming a coding packet by the N information element blocks containing the return-to-zero bits obtained in the step a) and the sequentially corresponding N first component block coding code elements and second component block coding code elements, wherein the length of the coding packet is 3 xL +4 xNxm;

2) A perforation processing mode: carrying out mutually independent puncturing processing on each block in the coding packet; wherein the return-to-zero bits in the information element block are not punctured; the length of the code packet after the puncturing processing is R × L +4 × N × m, wherein 1/R is the code rate of the code adjusted by the puncturing module, and R is less than or equal to 3.

The code elements output by the two component RSC coding modules, together with unprocessed information elements and return-to-zero tail bits of the two component RSC coding modules when each information element is subjected to return-to-zero processing in a blocking mode, are sequentially merged into a complete code packet through the blocking merging processing module and then output: firstly, outputting an information element, a coding code element and a zero tail bit corresponding to a first information element block, then outputting an information element, a coding code element and a zero tail bit corresponding to a second information element block, and finally outputting an information element, a coding code element and a zero tail bit corresponding to an Nth information element block; the length of the code grouping after the block combination processing is 3 xL +4 xN xm, wherein m is the code storage length of the RSC coding module; the puncturing module performs puncturing processing on the combined code packet according to a puncturing mode, and does not perform puncturing processing on a part which belongs to the zeroing processing of each information element block coding in the code packet with the length of 3 xL +4 xNxm: specifically, the section to be subjected to the puncturing process is [4 × (k-1) × m +3 × (k-1) × L/N +1,4 × (k-1) × m +3 × k × L/N ], where k is in the range of 1 to N; the length of the code packet processed by the puncture module is R × L +4 × N × m, wherein 1/R is the code rate of the code adjusted by the puncture module, and R is less than or equal to 3.

The cache processing of the decoding end adopts a memorizer with the length of R multiplied by L +4 multiplied by N multiplied by m;

the depuncturing processing of the decoding end adopts a mode corresponding to the puncturing processing mode of the encoding end, and the depuncturing receiving coding packet with the column length of 3 xL +4 xN xm is recovered; the position of the added zero bits in the depunctured received code packet is specified by the puncturing pattern.

The decoding preprocessing of the decoding end of the invention carries out the following processing on the coding packet obtained by depuncturing reception:

(1) Sequentially adding first component return-to-zero bits to the tail ends of the N information element blocks to obtain information element blocks with the length of L/N + M and containing return-to-zero bits, and using the information element blocks and N first component block coding code elements with the length of L/N + M as input of first component N soft input and soft output decoding in M decoding units;

(2) Sequentially combining the N information elements into complete information elements with the length of L in blocks; then, interleaving information elements are obtained after interleaving processing, and the interleaving information elements are split into N equal-length interleaving information element blocks; and sequentially adding second component return-to-zero bits to the tail ends of the N interleaved information element blocks to obtain interleaved information element blocks with the length of L/N + M and containing return-to-zero bits, and using the interleaved information element blocks and N first component block coding code elements with the length of L/N + M as the input of second component N soft input and soft output decoding in M decoding units through a delay line.

The decoding end of the invention adopts a decoding unit number M which is usually more than or equal to 2, and each decoding unit realizes the pipelined iterative decoding of the Turbo code in a cascading way: the input of the first component N soft input soft output decoding in the first decoding unit is directly sent by the decoding preprocessing output, the input of the second component N soft input soft output decoding in the first decoding unit is sent by the decoding preprocessing output through the input delay line, the input of the first component N soft input soft output decoding in the subsequent decoding unit is sent by the input delay line of the second component of the previous decoding unit through the delay line, and the input of the second component N soft input soft output decoding in the subsequent decoding unit is sent by the input delay line of the first component of the decoding unit through the delay line.

The processing performed by the decoding unit in the present invention may be:

the input of the first component soft input soft output decoding processing and the second component soft input soft output decoding processing takes the information outside the blocks as input besides the output information of the decoding preprocessing; after decoding processing, outputting two pieces of output information with the length of L/N + m, namely block likelihood ratio decoding output or block external information output;

(1) The first decoding unit first component N soft input soft output decoding processing adopts N zero bits with the length of L/N + m as the blocking external information input, and the blocking external information of the first component N soft input soft output decoding except the first decoding unit is input into the second component blocking external information obtained by the previous decoding unit; decoding the input to obtain the block external information output with the length of L/N + m;

the method comprises the steps that after m bits at the tail of each piece of block external information are removed in the block combining process, N pieces of block external information are sequentially combined into complete first component external information with the length of L, the first component external information is divided into N blocks with the length of L/N after the N pieces of block external information are subjected to interleaving process, zero bits with the length of m are added at the tail of each block, and the first component block external information with the length of L/N + m is obtained;

(2) The external information input of the second component N soft input soft output decoding processing is the first component block external information of the decoding unit;

except the Mth decoding unit, the second component N soft input soft output decoding in the first M-1 decoding units obtains the block external information output with the length of L/N + M; then block combining processing is carried out, m bits at the tail of each piece of block external information are removed, and then N pieces of block external information are sequentially combined into complete second component external information with the length of L; after de-interleaving processing, the blocks are split into N blocks with the length of L/N, and zero bits with the length of m are added at the tail of each block to obtain second component extra-block information with the length of L/N + m;

the second component N soft input soft output decoding of the Mth decoding unit obtains the block likelihood ratio decoding output with the length of L/N + M; carrying out block combination processing, firstly removing m bits at the tail of each block likelihood ratio decoding output, and then combining N block likelihood ratio decoding outputs into a complete likelihood ratio decoding output with the length of L; and after de-interleaving processing, removing the pseudo information element in the decoded output by referring to the control header information of the received coding packet to obtain the decoded output with the system set length L'.

The length of data processed by the interleaving and the deinterleaving of the decoding end decoding unit and the interleaving of the encoding end is equal to L. The sample method continues to use the Turbo code length interleaver while carrying out block return-to-zero coding, thereby obtaining the minimum free code distance d basically same as the traditional Turbo coding method _min Therefore, the error correction performance of the Turbo code can be ensured, and the Turbo decoding delay can be greatly reduced. When the number N of the blocks is equal to 1, the Turbo code parallel coding and decoding method is evolved into the traditional coding and decoding method.

Drawings

The embodiments of the present invention are described below with reference to the drawings.

FIG. 1 is a diagram of a coding structure according to an embodiment of the present invention

FIG. 2 is a decoding structure diagram according to an embodiment of the present invention

FIG. 3 is a block diagram of a decoding preprocessing module according to the present invention

FIG. 4 is a block diagram of a component parallel SISO decoding block

FIG. 5 is a diagram of a second encoding structure according to an embodiment of the present invention

FIG. 6 is a diagram of a structure of three coding schemes according to an embodiment of the present invention

Example 1

Encoding process

Fig. 1 shows an implementation structure of Turbo code block coding.

The Turbo code block coding structure of the embodiment is composed of a coding preprocessing module, a block splitting processing module, a first component block recursive system convolutional coding module (RSC 1) with a return-to-zero processing module, a second component recursive system convolutional coding module (RSC 2) with a return-to-zero processing module, an interleaving processing module, a puncturing processing module and a coding output module.

Information elements with the length L' from the information source are subjected to encoding preprocessing, and information elements with the length L, which can be divided by N, are output. If the length L 'of the information element set by the system can be divided by N, the length L of the information element after the coding preprocessing module is equal to L'; if the length L 'of the information element set by the system can not be divided by N, the encoding preprocessing module adds the length L' to the tail end of the information element with the length L

After the known dummy information elements (e.g. zero bits) are obtained, they are extended to a length of

The information element of (2); here, the

Represents the smallest integer greater than or equal to L'/N; the Turbo code block coding mode can inform a decoding end whether to need decoding output and what position to remove a pseudo information element inserted by a coding end in coding preprocessing through control head information of a coding block; when L = L', the control head information will inform the decoding end that the decoding end does not need to decode the block after the block combination processingThe log-likelihood ratio decoding output with the length of L obtained by the processing of the interleaving module is processed; in that

When the decoding end needs the control head informationAfter the block combination processing, the likelihood ratio decoding output with the length of L obtained by the de-interleaving processing is deleted from the position L' +1, the length of L added by the encoding end in the encoding preprocessing is

The dummy information element of (1).

One path of information elements with the length of L is controlled by the block splitting processing module, the information elements are blocked according to the length of L/N and sent to the first component recursive system convolutional coding for return-to-zero processing, the other path of interleaved information elements is obtained after interleaving processing, and the interleaved information elements are blocked according to the length of L/N and sent to the second component recursive system convolutional coding for return-to-zero processing under the control of the block splitting processing module; the two coding modules RSC1 and RSC2 code the information element block with the length of L/N and return to a zero state, and then the coding processing of the next information element block with the length of L/N is carried out.

Code element Y output by two component RSC coding module _1，k ，Y _2，k Together with the unprocessed itoms and the zero tail bits t of the two component RSC encoding modules at the time of the zero processing of each itom block _1，k ，t _2，k Under the control of the partitioning and splitting processing module, a complete code packet is sequentially merged and output through partitioning and merging processing according to the following modes:

first, the information element, coding code element and zero tail bit corresponding to the first information element block are output (wherein the superscript represents the block serial number)

Then outputting information element, coded code element and zero tail bit corresponding to the second information element block

Finally, information element, code element and return-to-zero bit corresponding to the Nth information element block;

the code packet after the block opening and closing processing is divided into

{{X ⁽¹⁾ ，Y ₁ ⁽¹⁾ ，Y ₂ ⁽¹⁾ ；X _t ⁽¹⁾ ，Y _1t ⁽¹⁾ ，Y _2t ⁽¹⁾ }，{X ⁽²⁾ ，Y ₁ ⁽²⁾ ，Y ₂ ⁽²⁾ ；X _t ⁽²⁾ ，Y _1t ⁽²⁾ ，Y _2t ⁽²⁾ }，…，{X ^(N) ，Y ₁ ^(N) ，Y ₂ ^(N) ；X _t ^(N) ；Y _1t ^(N) ，Y _2t ^(N) It can be seen that the above coded packet is formed by an information element X with the addition of a return-to-zero bit _k First component encoded symbol Y _1，k Second component code symbol Y _2，k The length is 3 xL +4 xN x m, and m is the code storage length of the RSC coding module.

Under the control of the block splitting processing module, the puncturing module performs puncturing processing on the combined coding packets by referring to a puncturing mode, and does not perform puncturing processing on a part which belongs to the coding zeroing processing of each information element block coding in the coding packets with the length of 3 xL +4 xNxm during the puncturing processing: specifically, the section to be subjected to the puncturing process is [4 × (k-1) × m +3 × (k-1) × L/N +1,4 × (k-1) × m +3 × k × L/N ], where k has a value ranging from 1 to N, and the corresponding data to be subjected to the puncturing process are:

{{X ⁽¹⁾ ，Y ₁ ⁽¹⁾ ，Y ₂ ⁽¹⁾ }，{X ⁽²⁾ ，Y ₁ ⁽²⁾ ，Y ₂ ⁽²⁾ }，…，{X ^(N) ，Y ₁ ^(N) ，Y ₂ ^(N) }}

the length of the code packet after the puncturing processing is R × L +4 × N × m, wherein 1/R is the code rate of the code adjusted by the puncturing module, and R is less than or equal to 3.

It can be seen that the difference between the encoded code word output by the encoding end after block encoding and the traditional encoded code word is that blocks are divided in the code word by taking R × L/N as a unit, and some tail bits for encoding block zeroing are added behind each block; the length of the code word after the whole block coding is increased compared with the length of the traditional code word, and the increased tail bit length for the zero resetting of the coding blocks is 4 multiplied (N-1) multiplied by m. Considering that the number of blocks N is generally small, the number of redundant bits added by block coding is substantially negligible compared to the whole coded codeword. In addition, different from the conventional Turbo coding for puncturing, the Turbo coding module using block return to zero coding needs to perform puncturing in blocks except for the last 4m return to zero tail bits, because there are 4 × (N-1) × m tail bits for block return to zero in the middle of the code word after block coding and the puncturing cannot be performed.

Decoding process

Fig. 2 shows a second component parallel decoding implementation structure of the Turbo code based on block processing in the embodiment.

The Turbo code parallel decoding structure based on block processing consists of a cache module, a depuncturing module and a decoding moduleThe processing module and the assembly line type decoding structure are formed by cascading 2M basic decoding units, a block merging processing module, a de-interleaving module and a splitting processing module; each basic decoding unit comprises a first component N parallel Soft Input Soft Output (SISO) block decoding module, a second component N parallel Soft Input Soft Output (SISO) block decoding module, a block combining processing module, a block splitting processing module, an interleaving module, a de-interleaving module and a delay line. In the figure, X _k 、

、L _a，k 、

、Y _1，k 、Y _2，k The preceding "\" slash indicates N-way parallel input, with X _k For example, it represents X ¹ _h 、X ² _h 、…、X ^N _h The N paths of the input signals are input in parallel.

The Turbo code parallel decoding structure firstly stores coding code elements acquired after baseband de-mapping from a receiving end of a block data communication system in a cache module, wherein the length of a memory of the cache module is R multiplied by L +4 multiplied by N multiplied by m; and updating the cache content in a first-in first-out manner. And then the data is sent to decoding pretreatment after depuncturing treatment; the depuncturing processing uses a puncturing mode corresponding to the puncturing processing of the coding end to recover and obtain a depuncturing receiving coding packet with the length of 3 xL +4 xNxm; specifically, the depuncturing process does not depuncture the part of each information element block coding return-to-zero process in the coding block with the length of R × L +4 × N × m, but only depuncture the corresponding first component and second component coding code element in the interval of [4 × (k-1) × m + R × L/N +1,4 × (k-1) × m + R × k × L/N ], the value of k is in the range of 1 to N; where the number of zero bits added via the depuncture process is (3-R) L, and the location in the depuncture received encoded packet where the zero bits were added is specified by the puncturing pattern.

FIG. 3 shows the decoding preprocessing module of the present embodimentAnd (5) block structure. The decoding preprocessing module carries the corresponding information element X containing the return-to-zero bit in the received encoded packets of the de-puncturing reception _k First component encoded symbol Y _1，k A second component encoded symbol Y _2，k And extracting a first component zero-returning tail bit t from the zero-returning bits _1，k And a second component nulling tail bit t _2，k And obtaining the information element input and component code element input of N first component soft input soft output decoding modules in the following M decoding units, and the interleaving information element input and component code element Y required by N second component soft input eight soft output decoding modules _1，k ，Y _2，k Inputting, namely:

(1) The split processing in the decoding preprocessing combines the separated N information element blocks with the extracted corresponding N first component return-to-zero tail bits to generate the information element input of N first component soft input soft output decoding in the subsequent M decoding units, namely the information element X containing the first component return-to-zero bits _k (ii) a The combination method of each information element block and the corresponding first component zero-returning tail bit comprises the steps of adding the corresponding first component zero-returning tail bit at the tail end of each information element block, wherein the length of each combined information element block is L/N + m; n first component encoded symbols Y _1，k Inputting component code elements directly sent to N first component soft input soft output decoding in the subsequent M basic decoding units, wherein the length of the component code elements is L/N + M;

(2) The decoding preprocessing combines the extracted N information element blocks into a complete information element, and the N information element blocks are combined in sequence: firstly, outputting an information element corresponding to a first information element block, then outputting an information element corresponding to a second information element block until an information element corresponding to an Nth information element block is output, wherein the length of the combined information element is L; after the combined information elements are subjected to interleaving processing, the combined information elements are split again into N interleaving information element blocks with equal length; the decoding pretreatment divides the divided N interleaved information element blocks and the corresponding N second component return-to-zero tail bitsCombining to generate the interleaving information element input of N second component soft input soft output decoding in the following M basic decoding units, i.e. the information element containing the second component return-to-zero bit

The combination method of each interleaved information element block and the corresponding first component zero-returning tail bit comprises the steps of adding the corresponding second component zero-returning tail bit at the tail end of each interleaved information element block, wherein the combined interleaved information element block is L/N + m in length; n second component encoded symbols Y _2k And directly inputting the component coding code elements which are directly sent to N second component soft input and soft output decoding in the subsequent M basic decoding units, wherein the length of the component coding code elements is L/N + M.

In this way, the decoding end can split the information element, the first component code element, the interleaving information element and the second component code element for subsequent decoding through depuncturing processing and decoding preprocessing. Different from the traditional Turbo decoding for depuncturing, the Turbo decoding module adopting block decoding has the advantage that the depuncturing module also needs to perform depuncturing processing in blocks except that the last 4m tail bits returning to zero can not be depunctured, because 4 x (N-1) x m tail bits for block returning to zero in the middle of the code word after block coding can not be depunctured.

Fig. 2 and 4 show that N blocks output after decoding preprocessing are all L/N + m, and after m zero tail bits are added to the tail end, the Information element block, N first component coded symbols and N first component zero tail bits are combined and sent to a first group of N parallel soft input soft output decoding modules (SISO 11 to SISO 1N) to perform block parallel decoding, so as to obtain N blocks of likelihood ratio decoding output block LLRs and Extrinsic Information (Extrinsic Information) Le, wherein the lengths of the N blocks are all L/N + m { satisfies the relationship LLR = ax + _k +L _a，k +L _e，k The parameter alpha is a Turbo code component iterative decoding parameter (equal to 2/sigma in the case of Gaussian channel) ² )，L _a，k For input information of SISO decoding block, L _e，k For outgoing foreign lettersInformation); decoding output is processed by block combination, after the last m bits in the information output except the N parallel decoding modules are removed, the decoding output combines and outputs the first component external information with the output length of L according to the sequence of firstly outputting SISO11 external information, then outputting SISO12 external information and finally outputting SISO1N external information; after interleaving processing is carried out on the external information decoding output, block splitting processing is carried out to split the external information decoding output into N blocks, and zero bits with the length of m are added at the tail of each first component external information output block to obtain first component block external information with the length of (L/N + m); n blocks of second component coding code elements which are sent by a delay line and split by decoding preprocessing, N interleaved information element blocks of second components containing return-to-zero tail bits, and N pieces of first component external information obtained by the splitting processing of the blocks are sent to N blocks of second components for soft input and soft output decoding (SISO 21 to SISO 2N) to execute block parallel decoding, and the parallel decoding process is the same as that of N decoding modules of the first components;

the decoding end adopts the number M of decoding units equal to the iterative decoding times in the parallel Turbo code decoding based on the block processing, namely the decoding end realizes the pipeline type iterative decoding of the Turbo code through the cascade connection of M decoding units.

FIG. 4 shows the structure of a second component parallel SISO decoding consisting of N standard Turbo soft input soft output (SISO 11, SISO12, \8230;, SISO 1N) decoding modules, the structure of the second component parallel SISO decoding being substantially the same as it, denoted for its N decoding modules SISO21, SISO22, \8230;, SISO 2N; the information input by the first component parallel SISO decoding module comprises the following information: (1) Noise-containing information element X decoded for a first component _k For the second component decoded interleaved information element containing noise

(2) Sequence of noisy component-encoded symbols Y _1，k Or Y _2，k (ii) a (3) External information L _e，k . The extrinsic information of the first component SISO decoding module comes from the second component decoding module of the previous decoding unitThe external information of (2) is output; the extrinsic information of the second component SISO decoding module comes from the first component of the present decoding unitAnd outputting the external information of the SISO decoding module. The extrinsic information input to the first decoding unit is set to zero bits. SISO decoding module can use MAP, log-MAP, max-Log-MAP decoding algorithm;

taking MAP algorithm as an example, the algorithm for implementing SISO decoding is as follows

n∈1，2，…，N

Forward iteration: when h =1 to L/N, m, m' epsilon {0,1, \8230;, 2 ^M-1 }

And (3) reverse iteration: when h = L/N-1 to 1; m, m' epsilon {0,1, \8230, 2 ^M-1 }

External information: h =1,2, \8230, N; m, m' epsilon {0,1, \8230, 2 ^M-1 }

k＝h+(n-1)N

Wherein

The input and output processing method of the decoding unit to the two component soft input and soft output decoding modules is as follows:

(1) The first component SISO11, SISO12, \ 8230of M decoding units, SISO1N soft input soft output decoding obtains N blocked information elements X with length of L/N + M by decoding preprocessing module _k (X ¹ _h 、 X ² _h 、…、X ^N _h ) And a first component encoded symbol Y _1，h (Y ¹ _1，k 、Y ² _1，h 、…、Y ^N _1，h ) Except for the first translationCode unit and outer information L of outer, first component SISO11, SISO12, \ 8230;, SISO1N soft input soft output decoding module _a，h (L ¹ _a，h 、L ² _a，h 、…、L ^N _a，h ) The second component SISO21, SISO22, \8230ofthe former decoding unit, SISO2N soft input and soft output decoding module; the outer information of SISO1N soft input and soft output decoding module fixes the decoded unit as zero bit outer information with length of L/N + m; the first component SISO11, SISO12, \ 8230, SISO1N soft input soft output decoding module obtains the block external information output L with the length of L/N + m after decoding ¹ _e1，h 、L ² _e1，h 、…、L ^N _e1，h (ii) a The block combining processing module eliminates the last m bits in the output of the outer information of SISO11, SISO12, \8230, SISO1N decoding module, and combines the sequence of outputting the outer information of SISO11, then outputting the outer information of SISO12 and finally outputting the outer information of SISO1N, and outputs the decoding output L of the first component outer information with the output length L _e1，k (ii) a The combined first component external information with the length of L is output to an interleaving module to be interleaved and then to a block splitting moduleIt splits into equal-length N first component out-of-block informationThe length of each first component block external information is L/N; the blocking and splitting processing adds zero bits with the length of m at the tail of each first component external information output block to obtain N first component blocking external information outputs with the length of L/N + m;

(2) A second component SISO21, SISO22, \8230ofM decoding units, a SISO2N soft input soft output decoding module obtains N interleaving information elements X with the length of L/N + M of the blocks by a decoding preprocessing module _h (X ¹ _h 、X ^- _h 、…、

) And a second component encoded symbol Y _2，k (Y ¹ _2，h 、Y ² _2，h 、…、Y ^N _2，h ) Second component SISO21, SISO22, \ 8230, and outer information L of SISO2N soft input and soft output decoding module _a，k (L ¹ _a，h 、L ² _a，h 、…、L ^N _a，h ) The decoding unit is provided by a first component SISO11, SISO12, \8230;, SISO1N soft input soft output decoding module; the second component SISO21, SISO22, \8230, SISO2N soft input soft output decoding module obtains the block likelihood ratio decoding output LLR with the length of L/N + m after decoding ¹ 、LLR ² 、 LLR ^N Or out-of-block information output L ¹ _e2，h 、L ² _e2，h 、…、L ^N _e2，h (ii) a In the first to M-1 decoding units except the Mth decoding unit, after the second component SISO21, SISO22, \8230;, the block combining processing module after the SISO2N soft input soft output decoding module rejects the last M bits in the output of the information outside the SISO21, SISO22, \8230;, the SISO2N decoding module outputs the information L outside the SISO21 according to the first ¹ _e2，h Then outputs SISO22 extrinsic information L ² _e2，h 8230and finally outputSISO2N extrinsic information L ^N _e2，h Combining and outputting second component extrinsic information with the length L; sending the combined second component external information with the length of L to a de-interleaving module, and sending the combined second component external information to a block splitting processing module to split the combined second component external information into N second component block external information with equal length; and the blocking splitting processing module adds zero bits with the length of m at the tail of each second component blocking external information to obtain second component blocking external information output with the length of L/N + m. And the second component SISO21, SISO22, \8230ofthe Mth decoding unit, the length of the SISO2N soft input soft output decoding module is L/N + M of the block likelihood ratio decoding output LLR ¹ 、LLR ² 、LLR ^N After M decoding unitsThe block merging processing module carries out merging processing; the block merging processing module merges to obtain a decoding output with the length of L according to the following mode: the block combining processing module firstly eliminates m bits at the tail of each likelihood ratio decoding output, then outputs SISO21 likelihood ratio decoding output, then outputs SISO22 likelihood ratio decoding output, and finally outputs the sequence of SISO2N likelihood ratio decoding output, and combines and outputs likelihood ratio decoding output with the length of L; and after the deinterleaving module executes deinterleaving processing on the likelihood ratio decoding output with the length of L, the control head information of the received coding packet is referred to, and after the pseudo information in the decoding output is eliminated, the decoding output with the length of L' set by the system is obtained.

In the Turbo code parallel decoding structure based on block processing, the processed data length of each interleaving module and each de-interleaving module is equal to L.

The Turbo decoding structure based on block processing supports high-speed parallel block decoding of Turbo codes; because the initial values of the forward state and the backward state of each coding block are set to be zero states, the parallel coding and decoding method based on the block processing can perform lossless decoding, the Turbo decoding reliability is ensured, and the decoding delay of the Turbo code is reduced to 1/N of the traditional serial Turbo code decoding. In the codec structure of this embodiment, the data length processed by each interleaving module is equal to L.

A parallel coding and decoding method based on block processing is realized through block coding at a coding end and block parallel decoding at a decoding end. Different from the prior documents and patents, the invention adopts a parallel decoding method based on the block in decoding, and also adopts a block coding method with return-to-zero at the coding end. By adding a block splitting processing module, a block merging processing module and a block coding module with a zeroing processing, the coding end sets the starting state and the ending state of each block to be zero while realizing the block coding processing of the information elements. The decoding end supports the high-speed parallel decoding of the Turbo code by adding a block splitting processing module, a block merging processing module and a decoding unit formed by a plurality of soft input and soft output decoding modules aiming at block coding in two component decoding. Because the coding end adopts the block coding processing with the return-to-zero, the initial values of the forward state and the backward state of each block are set to be in a zero state.

Example two

Fig. 5 shows a second implementation structure of Turbo code block coding. Unlike the first embodiment, each component RSC encoder uses N encoding modules with return-to-zero processing to encode the information elements Xk in parallel.

The Turbo code block coding structure of the embodiment comprises a coding preprocessing module, a block splitting processing module, a block merging processing module, a first component N parallel-working recursive system convolutional coding (RSC 11, RSC12, \ 8230;, RSC 1N) module with a zeroing process, a second component N parallel-working recursive system convolutional coding (RSC 21, RSC22, \ 8230;, RSC 2N) module with a zeroing process, an interleaving module and a puncturing module.

The information element with the length L' from the information source passes through the coding preprocessing module, and the information element with the length L and capable of being evenly divided by N is output. L = L 'if L' is divisible by N; if L' cannot be divided exactly by N, then

(wherein

Represents greater than or equal to

The smallest integer of (a). The Turbo code block encoder can inform a decoding end whether to need and what position to remove a pseudo information element inserted by the encoding end during encoding preprocessing when decoding is output through control head information of encoding blocks; when L = L', the control head information informs a decoding end that the combination of the partitioned combination processing module is not needed, and then the log-likelihood ratio decoding output with the length of L after the processing of the de-interleaving module is processed; in that

Then, the control head information will inform the decoding end that it needs to combine the blocks, then the de-interleaved likelihood ratio decoding output with length L will delete the length L added by the encoding end in the encoding preprocessing from the position L' +1

The dummy information element of (1).

One path of information elements with the length of L is divided into N blocks with the length of L/N by a block dividing and processing module, and N recursive system convolutional coding modules RSC11, RSC12, \8230thatcarry out parallel coding and RSC1N with return-to-zero processing are simultaneously sent; and the other path of interleaved information elements processed by the interleaving module are also divided into N blocks of information elements with equal length after being subjected to the block splitting processing module, and are simultaneously sent to N RSC encoding modules RSC21, RSC22, \8230, RSC2N of the second component to execute parallel block encoding. The RSC parallel encoding modules of the two components both execute block encoding with return-to-zero processing, namely 2N parallel RSC encoding modules of the two components return to a zero state after executing block encoding on each block of information element. RSC parallel encoding process of two components is that RSC11 in the first component encoder processes the first block sent by the block splitting processing module, RSC12 processes the second block sent by the block splitting processing module, and RSC1N processes the Nth information element block sent by the block splitting processing module; also a second component parallel encoder encodes blocks of N interleaved information elements in parallel.

Code element Y output by two component RSC coding module _1，k ，Y _2，k Along with the unprocessed itoms and the zero tail bits t of the two component RSC encoding modules in the zero processing of each itom block _1，k ，t _2，k The method of block merging and puncturing is the same as that of the first embodiment. And finally outputting the code element.

The decoding processing method is the same as the first embodiment. In the codec structure of this embodiment, the data length processed by each interleaving module is equal to L.

EXAMPLE III

Fig. 6 shows a third implementation structure of Turbo code block coding.

The Turbo code block coding structure of this embodiment is different from the first and second embodiments in that the return-to-zero processing of each coded block by the RSC coding module used in this embodiment is implemented under the control of the block splitting processing module. Specifically, the blocking and splitting processing module realizes the zero return processing of the information element blocking and coding by controlling a reverse generation element branch of the RSC coder.

The Turbo code block coding module consists of a coding preprocessing module, a block splitting processing module, a block merging processing module, a first component block recursive systematic convolutional coding (RSC) module I (RSC 1), a second component recursive systematic convolutional coding module II (RSC 2), an interleaving module, a puncturing module and a coding output module;

the information element with length L' from the information source is firstly processed by the encoding preprocessing module, and the information element with length L which can be evenly divided by N is output. The information element with the length of L output by the coding preprocessing module is divided into N information elements with equal length by the block dividing processing module in one path, m zero bits are added at the tail of each block, the information elements are sent to a first component block recursive system convolutional coding module (RSC 1) for coding, after the RSC1 codes the L/N information elements, the block processing module controls to disconnect a reverse generation element branch of the RSC1, and the zero bits added by the block processing module realize the zero return processing; the other path of interleaved information elements processed by the interleaving module is divided into N equal-length information elements by the block processing module, m-bit zero bits are added at the tail of each block, the N equal-length information elements are sent to a second component block recursive system convolutional coding module II (RSC 2) for coding, the block processing module controls to disconnect a reverse generation element branch of the RSC2 after the RSC2 codes the L/N bit information elements, and the zero return processing of the M bit zero bits added by the block processing module is realized; the two encoders RSC1, RSC2 will return to the zero state after encoding each block information element.

Code element Y output by two-component RSC coding module _1，k ，Y _2，k Together with the unprocessed itoms and the zero tail bits t of the two component RSC encoding modules at the time of the zero processing of each itom block _1，k ，t _2，k The method of block merging and puncturing is the same as in the first and second embodiments. And finally outputting the code element.

It should be noted here that the block splitting processing module may also control the component RSC encoding module to implement the zeroing process after the information element block encoding by using other methods. For example, the block splitting processing module may add m zero bits at the end of each block information element, and the block splitting processing module performs multiplication operation on the m zero bits and the RSC reverse generator at the block tail to perform return-to-zero encoding processing of the RSC information element block. The decoding processing method is the same as the first embodiment. In the codec structure of this embodiment, the data length processed by each interleaving module is equal to L.

Claims

1. A parallel Turbo coding and decoding method based on block processing for digital communication error control is disclosed, wherein the coding end directly performs a first component recursive system convolutional coding on an information element to obtain a first component coding code element, performs an interleaving processing to generate an interleaving information element, performs a second component recursive system convolutional coding to obtain a second component coding code element, and performs a puncturing processing on the first and second component coding code elements and the information element which is not subjected to the system convolutional coding to obtain a Turbo coding code element; the decoding end carries out buffer processing on the received Turbo coding code element, de-puncturing processing is carried out to obtain an information element, a first component coding code element and a second component coding code element, and the information element, the first component coding code element and the second component coding code element are sent to M decoding units which are more than or equal to 1 to obtain decoding output after decoding, interweaving and de-interweaving processing, and the decoding output method is characterized by comprising the following steps of:

and (3) a coding end: the information elements need to be subjected to coding preprocessing: firstly, directly partitioning the block into N blocks, and then carrying out convolution coding on a first component recursive system with return-to-zero processing; secondly, dividing the interleaving information elements generated by the interleaving into N blocks which are more than or equal to 2, and then carrying out second component recursive systematic convolutional coding with zeroing processing; combining the obtained first component coding element and the second component coding element with the information element which is not subjected to the systematic convolutional coding, and then performing puncturing processing;

and a decoding end: after depuncturing, the information element, the first component code element and the second component code element are obtained and sent to M decoding units for decoding after decoding pretreatment, two components of each decoding unit respectively adopt N soft input and soft output decoding modules for parallel decoding treatment, the number N of the parallel decoding modules is the same as the number of the blocks split by the encoding end, the initial values of the forward state metric alpha and the backward state metric beta used by the decoding treatment are zero, the external information obtained after the parallel decoding treatment is carried out corresponding block merging treatment and block splitting treatment by the decoding unit; and the decoding unit carries out corresponding block merging processing and de-interleaving processing to obtain decoding output.

2. The block processing-based parallel Turbo coding and decoding method for error control in digital communications according to claim 1, wherein: the specific process of the coding preprocessing of the coding end is as follows:

if the length L 'of the information element cannot be divided by N, adding a known dummy information element at the tail end of the information element with the length L' by the encoding preprocessing to increase the length to the minimum number L which can be divided by N, and writing the adding position and number of the dummy information element into the control head information of the encoding packet; the decoding unit at the decoding end deletes the added pseudo information element before decoding output according to the control header information of the coding packet;

if the length L' of the information element can be divided by N, the encoding preprocessing does not process the information element any more, and writes the information into the control head information of the encoding grouping; the decoding unit at the decoding end does not perform any processing on the decoded output according to the control header information of the encoded packet.

3. The block processing-based parallel Turbo coding and decoding method for error control in digital communications according to claim 2, wherein: the return-to-zero processing mode of the recursive system convolutional coding processing of the first component and the second component with return-to-zero processing is that after each information element is subjected to block coding, the block coding returning to the zero state is subjected to return-to-zero processing to generate a first component block coding code element and a second component block coding code element and return-to-zero bits enabling the first component block coding code element and the second component block coding code element to return to zero, the length of the first component block coding code element and the length of the second component block coding code element are L/N + m, and m is the coding storage length of an RSC coding module.

4. The parallel Turbo coding and decoding method based on block processing for error control of digital communication according to claim 3, wherein the encoding end:

1) The specific way of the block merging treatment is as follows:

2) A perforation processing mode: performing mutually independent puncturing processing on each block in the coding packet; wherein the zero bits in the information element block are not punctured; the length of the code packet after the puncturing processing is R × L +4 × N × m, wherein 1/R is the code rate of the code adjusted by the puncturing module, and R is less than or equal to 3.

5. The block-processing-based parallel Turbo coding and decoding method for error control of digital communications according to claim 4, wherein:

the depuncturing processing of the decoding end adopts a mode corresponding to the puncturing processing mode of the encoding end to recover to obtain a depunctured received coding packet with the length of 3 xL +4 xNxm; the position of the added zero bits in the depunctured received code packet is specified by the puncturing pattern.

6. The parallel Turbo coding and decoding method based on block processing for error control of digital communication according to claim 5, wherein the decoding pre-processing at the decoding end performs the following processing on the coding packets obtained by the de-puncturing processing:

(1) Sequentially adding first component zeroing bits to the tail ends of the N information element blocks to obtain information element blocks with the length of L/N + M and containing the zeroing bits, and using the information element blocks and N first component block coding code elements with the length of L/N + M as input of first component N soft input and soft output decoding in M decoding units;

7. The block-processing-based Turbo coding and decoding method for error control in digital communications according to claim 6, wherein the number of decoding units M adopted by the decoding end is greater than or equal to 2, and each decoding unit implements pipelined iterative decoding of Turbo codes in a cascaded manner: the input of the first component N soft input soft output decoding in the first decoding unit is directly sent by the decoding preprocessing output, the input of the second component N soft input soft output decoding in the first decoding unit is sent by the decoding preprocessing output through the input delay line, the input of the first component N soft input soft output decoding in the subsequent decoding unit is sent by the input delay line of the second component of the previous decoding unit through the delay line, and the input of the second component N soft input soft output decoding in the subsequent decoding unit is sent by the input delay line of the first component of the decoding unit through the delay line.

8. The block-processing-based parallel Turbo coding and decoding method for error control in digital communications according to claim 7, wherein the decoding unit performs the processes of:

the input of the first component soft input and soft output decoding processing and the second component soft input and soft output decoding processing takes the information outside the blocks as input besides the output information of the decoding preprocessing; after decoding processing, outputting two pieces of output information with the length of L/N + m, namely block likelihood ratio decoding output or block external information output;

(2) The external information input of the second component N soft input soft output decoding processing is the external information of the first component block of the decoding unit;

except the Mth decoding unit, the second component N soft input soft output decoding in the first M-1 decoding units obtains the information output outside the blocks with the length of L/N + M; then, block combining processing is carried out, m bits at the tail of each piece of block external information are removed, and then the N pieces of block external information are sequentially combined into complete second component external information with the length of L; after de-interleaving processing, splitting the blocks into N blocks with the length of L/N, and adding zero bits with the length of m at the tail of each block to obtain second component block external information with the length of L/N + m;

the decoding unit carries out soft output decoding on N soft inputs of the second component of the Mth decoding unit to obtain the decoding output of the block likelihood ratio with the length of L/N + M; carrying out block combination processing, firstly removing m bits at the tail of each block likelihood ratio decoding output, and then combining N block likelihood ratio decoding outputs into a complete likelihood ratio decoding output with the length of L; and then, after de-interleaving processing, referring to the control head information of the received coding packet, and eliminating a pseudo information element in decoding output to obtain decoding output with the system set length of L'.

9. The block-processing-based parallel Turbo codec module interleaving and deinterleaving module for digital communication error control according to claim 1, wherein: the data length processed by interleaving, deinterleaving and interleaving at the encoding end in the decoding end decoding unit is equal to L.