CN100364112C - Wafer type diode capable of surface mounting - Google Patents
Wafer type diode capable of surface mounting Download PDFInfo
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- CN100364112C CN100364112C CNB031568904A CN03156890A CN100364112C CN 100364112 C CN100364112 C CN 100364112C CN B031568904 A CNB031568904 A CN B031568904A CN 03156890 A CN03156890 A CN 03156890A CN 100364112 C CN100364112 C CN 100364112C
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Abstract
The present invention relates to a wafer type diode with surface installation, and provides a semiconductor assembly. The semiconductor assembly improves heat conduction characteristic, can bear high working temperature, have simple structure, simplify manufacture process, reduce volume, decrease cost, and can be directly arranged on an electronic circuit. The present invention is provided with semiconductor wafer grains, an upper semiconductor of different types, and a lower semiconductor of which the bottom is provided with a first electric conduction metal layer. A first insulating layer is arranged among the upper semiconductor and the semiconductor wafer grains, and thus, the upper semiconductor and the semiconductor wafer grains are separated and insulated. The first insulating layer is respectively provided with a center part and a circumferential part of a third electric conduction metal layer. The side edges of the upper semiconductor, the semiconductor wafer grains and the lower semiconductor are provided with a second electric conduction metal layer which is conducted with the first electric conduction metal layer and a third electric conduction metal layer.
Description
Technical field
The invention belongs to semiconductor subassembly, particularly a kind of surface-mountable wafer diode.
Background technology
The basic structure of the general diode element of commonly using on the market comprise the silicon crystal grain, respectively be welded in the silicon crystal grain both ends of the surface two conductive metal sheets and be welded in the lead of two conductive metal sheet another sides respectively so as to being connected with other electronic circuit.
In the diode element manufacturing process of commonly using, after silicon crystal grain and conductive metal sheet are combined into one, need the silicon crystal grain is carried out etch processes, wait finish etch processes after, need to see through again the encapsulation process program, in silicon crystal grain and conductive metal sheet periphery packaging insulating colloid, promptly make general diode element.
In the processing procedure of the diode element of commonly using, after the silicon crystal grain is finished etch processes, all be it to be encapsulated with resin or other colloid.Because resin or colloid and hot temperature is not high so as to encapsulation, so when it is used as the rectifier cell of high power input current, or when being used in hot environment, very easily have deep love for decreasing because of height, cause the relevant electronic equipment can't normal operation, have a strong impact on the useful life and the quality of electronic equipment, and cause the many puzzlements in the maintenance; In addition, owing to the encapsulating housing that forms with resin or colloid, must take a certain size space, so the volume of the diode element that order is commonly used can't further dwindle all the time.
Summary of the invention
The purpose of this invention is to provide a kind ofly improve thermal conduction characteristic, can bear than elevated operating temperature, simple in structure, simplify processing procedure, reduced volume, reduce cost, can directly be installed on the surface-mountable wafer diode on the electronic circuit.
The present invention has semiconductor grain and is arranged at semiconductor on the p+ N-type semiconductor N of the upper and lower end face of semiconductor grain, under the n+ type respectively, and following semiconductor bottom is provided with first conductive metal layer; Semiconductor-on-insulator and semiconductor grain are provided with first insulating barrier, and this first insulating barrier separates into semiconductor-on-insulator and semiconductor grain the central authorities and the peripheral part of mutually insulated; Semiconductor-on-insulator end face middle body is provided with the 3rd conductive metal layer to be equivalent to forming a welding conducting end on semiconductor-on-insulator; Semiconductor-on-insulator end face peripheral part is provided with the 3rd conductive metal layer; Reaching down in semiconductor-on-insulator, semiconductor grain, the semiconductor lateral margin is provided with second conductive metal layer, the 3rd conductive metal layer of one end of second conductive metal layer and semiconductor-on-insulator end face peripheral part is conducted, its other end and semiconductor grain reach down, and the first conductive metal layer lateral margin of semiconductor bottom is conducted, to make semiconductor-on-insulator, semiconductor grain and semiconductor short circuit down, to be equivalent to forming another welding conducting end on the semiconductor down.
Wherein:
Semiconductor grain is the n N-type semiconductor N.
Central authorities that the semiconductor-on-insulator end face separates with first insulating barrier and the 3rd conducting metal series of strata of peripheral part are with the plating mode setting.
Be provided with two horizontal grooves of parallel interval from the semiconductor-on-insulator end face along the X-axis etching, be provided with two vertical grooves of parallel interval along the Y direction etching, this two vertical groove and two horizontal grooves are ccontaining for first insulating barrier, and pass semiconductor grain and arrive semiconductor down.
First insulating barrier that is placed in semiconductor-on-insulator and semiconductor grain two vertical grooves and the two horizontal grooves is the glass dielectric layer with the glass cream sintering.
Following semiconductor bottom is along Y direction etching conduit; The bottom of conduit system keeps suitable distance with longitudinal and transverse bottom portion of groove, and the width of this conduit in X-direction approximately corresponding to the two adjacent described width of containing along the vertical groove of Y-axis; The first conducting metal series of strata that are arranged at down the semiconductor bottom are sintered in the conduit.
Be sintered in down that coating is provided with second insulating barrier on first conductive metal layer in the semiconductor base channel road.
The glass dielectric layer of second insulating barrier for forming by the glass cream sintering.
The second conducting metal series of strata are arranged at semiconductor-on-insulator, semiconductor grain and following semiconductor lateral margin with sintering processing.
Because the present invention has semiconductor grain and the upper and lower semiconductor of different shaped, following semiconductor bottom is provided with first conductive metal layer; Semiconductor-on-insulator and semiconductor grain are provided with and it are separated into mutually insulated and be respectively equipped with the central authorities of the 3rd conductive metal layer and first insulating barrier of peripheral part; The semiconductor lateral margin is provided with second conductive metal layer of conducting first and third conductive metal layer under semiconductor-on-insulator, semiconductor grain reach.Semiconductor-on-insulator and semiconductor grain are separated into central authorities and periphery two parts of mutually insulated by first insulating barrier, the 3rd conductive metal layer that is coated in the semiconductor-on-insulator middle body forms the welding conducting end, is coated in semiconductor-on-insulator peripheral part the 3rd conductive metal layer and is conducted to be equivalent to forming another welding conducting end on the semiconductor down by the following semiconductor of second conductive metal layer and first conductive metal layer and bottom in regular turn.So, can be under need not the processing of follow-up canned program form two two independent welding conducting end of upper and lower semiconductor conducting respectively in its same top, welding conducting end so as to as mounted on surface (SMD) time, because simple in structure, processing procedure convenience, and under the situation that need not carry out follow-up encapsulation fully, make in a large number, not only significantly promote speed of production, reduced manufacturing cost, more need not the packaging insulating colloid because of surface-mountable wafer diode, so also significantly improved its thermal conduction characteristic, prolonged its useful life.Not only improve thermal conduction characteristic, can bear than elevated operating temperature, and simple in structure, simplify processing procedure, reduced volume, reduce cost, can directly be installed on the electronic circuit, thereby reach purpose of the present invention.
Description of drawings
Fig. 1, for fabrication steps one schematic diagram of the present invention (diffusing out the p+ type semiconductor layer) in the wafer end face.
Fig. 2, for fabrication steps two schematic diagrames of the present invention (diffusing out the n+ type semiconductor layer) in the wafer bottom surface.
Fig. 3, be fabrication steps three schematic diagrames of the present invention (in wafer top, the bottom surface forms groove and conduit is laterally analysed and observe).
Fig. 4, be fabrication steps three schematic diagrames of the present invention (in wafer top, the bottom surface forms groove and conduit is vertically analysed and observe).
Fig. 5, be A portion partial enlarged drawing among Fig. 3.
Fig. 6, be B portion partial enlarged drawing among Fig. 4.
Fig. 7, for fabrication steps four schematic diagrames of the present invention (forming first insulating barrier laterally analyses and observe).
Fig. 8, for fabrication steps four schematic diagrames of the present invention (forming first insulating barrier vertically analyses and observe).
Fig. 9, for fabrication steps five schematic diagrames of the present invention (forming first conductive metal layer laterally analyses and observe).
Figure 10, for fabrication steps five schematic diagrames of the present invention (forming first conductive metal layer vertically analyses and observe).
Figure 11, for fabrication steps six schematic diagrames of the present invention (forming second insulating barrier laterally analyses and observe).
Figure 12, for fabrication steps six schematic diagrames of the present invention (forming second insulating barrier vertically analyses and observe).
Figure 13, be fabrication steps seven schematic diagrames of the present invention (analysing and observe along vertical several channel laterals that form) in the wafer end face.
Figure 14, for fabrication steps eight schematic diagrames of the present invention (forming second conductive metal layer in the wafer end face laterally analyses and observe).
Figure 15, for fabrication steps nine schematic diagrames of the present invention (forming the 3rd conductive metal layer laterally analyses and observe).
Figure 16, for fabrication steps nine schematic diagrames of the present invention (forming the 3rd conductive metal layer vertically analyses and observe).
Figure 17, for fabrication steps ten schematic diagrames of the present invention (cutting the gradation finished product laterally analyses and observe).
Figure 18, for fabrication steps ten schematic diagrames of the present invention (cutting the gradation finished product vertically analyses and observe).
Figure 19, for structural representation cutaway view of the present invention.
Embodiment
As shown in figure 19, the surface-mountable wafer diode 50 of the present invention has and is n N-type semiconductor N semiconductor grain 10, is respectively equipped with to the p+ N-type semiconductor N and is the upper and lower semiconductor 11,12 of different shaped of n+ N-type semiconductor N at semiconductor grain 10 upper and lower end faces.Following semiconductor 12 bottoms are provided with first conductive metal layer 40; Be provided with parallel interval two vertical groove 21 and the two horizontal grooves 20 that pass semiconductor 12 under semiconductor grain 10 and the arrival from semiconductor-on-insulator 11 end faces along X-axis and Y direction etching, first insulating barrier, 30, the first insulating barriers 30 that are installed with the central authorities that separate so as to semiconductor-on-insulator 11 and semiconductor grain 10 and peripheral part in two vertical grooves 21 and two horizontal grooves 20 are the glass dielectric layer with the glass cream sintering; Semiconductor-on-insulator 11 end face middle bodies are provided with the 3rd conductive metal layer 42 to be equivalent to forming a welding conducting end on semiconductor-on-insulator 11; Semiconductor-on-insulator 11 end face peripheral parts are provided with the 3rd conductive metal layer 42; Reaching down in semiconductor-on-insulator 11, semiconductor grain 10, semiconductor 12 lateral margins are provided with second conductive metal layer 41, one end of second conductive metal layer 41 and semiconductor-on-insulator 11 peripheral parts the 3rd conductive metal layer 42 are conducted, its other end system reaches down with semiconductor grain 10, and first conductive metal layer, 40 lateral margins of semiconductor 12 bottoms are conducted, to make semiconductor-on-insulator 11, semiconductor grain 10 and semiconductor 12 short circuits down, to be equivalent to forming another welding conducting end on the semiconductor 12 down.
So, can be under need not the processing of follow-up canned program form in its same top two respectively be the semiconductor-on-insulator 11 of p+ N-type semiconductor N and be two independent conducting end of welding of following semiconductor 12 conductings of n+ N-type semiconductor N, the welding conducting end so as to as mounted on surface (SMD) time.
Following semiconductor 12 bottoms are along Y direction etching conduit 22; The width that the bottom system and longitudinal and transverse groove 21,20 bottoms of conduit 22 keep suitable distance and width to be contained corresponding to two adjacent vertical grooves 21 approximately in X-direction; First conductive metal layer 40 that is arranged at down semiconductor 12 bottoms is to be sintered in the conduit 22, and is provided with second insulating barrier 31 that is coated on first conductive metal layer 40 in conduit 22.The glass dielectric layer of second insulating barrier 31 for forming by the glass cream sintering.
Second conductive metal layer 41 is to be arranged at semiconductor-on-insulator 11, semiconductor grain 10 and following semiconductor 12 lateral margins with sintering processing.
Manufacture method of the present invention mainly is to utilize diffusion (diffusion) technology, forms the upper and lower semiconductor of different shaped for p+ and n+ N-type semiconductor N of predetermined thickness respectively in the upper and lower end face of semiconductor crystal wafer (wafer); Utilize statue again, etching, cloth is planted and semiconductor fabrication techniques such as sintering, on wafer, produce several diodes respectively, by insulating barrier semiconductor-on-insulator and wafer area are divided into the central authorities and the peripheral part of mutually insulated on the semiconductor-on-insulator of each diode upper surface, be coated with conductive metal layer on the semiconductor of its middle body as the welding conducting end, its peripheral part then coating conducting extremely plays the semiconductor lateral margin to form the conductive metal layer of another welding conducting end, so, can form on the same end face of several diodes respectively with on, the two welding conducting end that following semiconductor is conducted are produced the diode finished product that can supply mounted on surface (SMD).
The surface-mountable wafer diode manufacture method of the present invention comprises the steps:
Step 1
Form the p+ type semiconductor layer
As shown in Figure 1, can earlier the boron ions diffusion be gone into the semiconductor crystal wafer 10a top for the n type, forming predetermined thickness is the semiconductor-on-insulator 11 of p+ N-type semiconductor N.
Step 2
Form the n+ type semiconductor layer
As shown in Figure 2, the phosphonium ion deep diffusion is gone into bottom for the semiconductor crystal wafer 10a of n type, forming predetermined thickness is the following semiconductor 12 of n+ N-type semiconductor N, so, promptly produces semiconductive material wafer 13.
Though be that form predetermined thickness respectively in the top, the bottom that are the semiconductor crystal wafer 10a of n type be the semiconductor-on-insulator 11 of p+ N-type semiconductor N and be the following semiconductor 12 of n+ N-type semiconductor N with ion diffusion, also can utilize other diffusion method or cloth planting technology, in the top of the semiconductor crystal wafer (wafer) of p type or n type, bottom (or the end, top) form semiconductor-on-insulator that predetermined thickness is the n+ N-type semiconductor N and be the following semiconductor of p+ N-type semiconductor N (or be the following semiconductor of n+ N-type semiconductor N for the semiconductor-on-insulator of p+ N-type semiconductor N reaches).
Step 3
Form several first and second groove and conduits
As Fig. 3, Fig. 4, Fig. 5, shown in Figure 6, utilize statue and trench etched technology, in semiconductive material wafer 13 tops, etch several spaces and first groove 20 and second groove 21 parallel to each other along Y-axis and X-direction respectively according to required actual size; The degree of depth of first and second groove 20,21 all need be passed p+ N-type semiconductor N 11 and is the semiconductor crystal wafer 10a of n type, and arrival is following semiconductor 12 positions of n+ N-type semiconductor N; In the bottom of semiconductive material wafer 13, also utilize statue and trench etched technology, according to required actual size, etch several interval and conduits 22 parallel to each other at bottom position for semiconductor 12 under the n+ N-type semiconductor N along X-direction; The bottom of each conduit 22 system keeps suitable distance with first and second groove 20,21 bottoms, and the width contained corresponding to two adjacent second grooves 21 approximately in X-direction of its width.
Step 4
Form first insulating barrier
As Fig. 7, shown in Figure 8, to evenly modulate the glass paste that mixes with glass powder and glue inserts in first and second groove 20,21 at semiconductive material wafer 13 tops, and it is carried out sintering processes, the glass paste that sintering is finished forms first insulating barrier 30 in first and second groove 20,21, be p+ N-type semiconductor N semiconductor-on-insulator 11 and the two parts that separated into mutually insulated for the semiconductor crystal wafer 10a of n type in order to do what be positioned at first and second groove 20,21 both sides by 30 orders of first insulating barrier.
Step 5
Form first conductive metal layer
As Fig. 9, shown in Figure 10, insert metal cream in number in the conduits 22, as materials such as copper cream, silver paste, gold pastes, and it is carried out sintering, in each conduit 22, to form first conductive metal layer 40 respectively.
Step 6
Form second insulating barrier
As Figure 11, shown in Figure 12, with glass powder and glue evenly the glass paste that mixes of modulation insert in several conduits 22 and be coated on first conductive metal layer 40; Also glass paste can be coated in the bottom of whole semiconductive material wafer 13, and it is carried out sintering processes, the glass of finishing in order to do sintering just can form second insulating barrier 31 in the bottom of semiconductive material wafer 13.
Step 7
Form several grooves
As shown in figure 13, utilize statue and trench etched technology, be formed in first groove 20 and offer groove 23 respectively between first insulating barrier 30 corresponding to adjacent per two in semiconductive material wafer 13 tops along Y direction, the degree of depth of each groove 23 just arrives first conductive metal layer, 40 positions.
Step 8
Form second conductive metal layer
As shown in figure 14, with metal cream, insert in several grooves 23 at semiconductive material wafer 13 tops as copper cream, silver paste, gold paste etc., and it is carried out sintering, in each groove 23, form second conductive metal layer 41 respectively, and make second conductive metal layer 41 and 40 conductings of first conductive metal layer.
Step 9
Form the 3rd conductive metal layer
As Figure 15, shown in Figure 16, at semiconductive material wafer 13 tops corresponding to plating the above conducting metal of one deck at least in the electroless plating mode for p+ N-type semiconductor N semiconductor-on-insulator 11 and second conductive metal layer, 41 positions, as nickel or gold, form the 3rd conductive metal layer 42.
The cutting gradation
As Figure 17, shown in Figure 180, corresponding to the middle position between each groove 23 and two adjacent first conductive metal layers 40, along X-axis and Y direction,, can produce the surface-mountable wafer diode 50 of several the present invention respectively to for the semiconductor crystal wafer 10a of n type cuts gradation.
As shown in figure 19, what first insulating barrier 30 will be positioned at first and second groove 20,21 both sides on the surface-mountable wafer diode 50 of the present invention is p+ N-type semiconductor N semiconductor-on-insulator 11 and central authorities and the periphery two parts that separate into mutually insulated for the semiconductor grain 10 of n type, so when center of top of the present invention for after being coated with the 3rd conductive metal layer 42 on the p+ N-type semiconductor N semiconductor-on-insulator 11, promptly be equivalent on the p+ of middle body N-type semiconductor N 11, form the welding conducting end; As for periphery of the present invention is that p+ N-type semiconductor N semiconductor-on-insulator 11 is after being coated with the 3rd conductive metal layer 42, can be in regular turn being conducted for semiconductor 12 under the n+ N-type semiconductor N by second conductive metal layer 41 and first conductive metal layer 40 and bottom, must pay special attention at this is to be semiconductor grain 10 lateral margins of n type because second conductive metal layer 41 is a direct sintering for p+ N-type semiconductor N semiconductor-on-insulator 11 reaches, and one end system is conducted with the 3rd conductive metal layer 42 of apical margin, its other end system respectively with being conducted for n N-type semiconductor N crystal grain 10 and first conductive metal layer, 40 lateral margins of root edge, lateral margin is the semiconductor-on-insulator 11 of p+ N-type semiconductor N so second conductive metal layer 41 can directly make, for reaching, n N-type semiconductor N crystal grain 10 is semiconductor 12 short circuits under the n+ N-type semiconductor N, so top of the present invention periphery is after p+ N-type semiconductor N semiconductor-on-insulator 11 peripheral parts are coated with the 3rd conductive metal layer 42, promptly be equivalent on for semiconductor 12 under the n+ N-type semiconductor N, form another welding conducting end.So, can be under need not the processing of follow-up canned program form in its same top two respectively be p+ N-type semiconductor N semiconductor-on-insulator 11 and be two independent conducting end of welding of semiconductor 12 conductings under the n+ N-type semiconductor N, the welding conducting end so as to as mounted on surface (SMD) time.
In sum, the surface-mountable wafer diode 50 that the present invention produces is because simple in structure, processing procedure convenience, and under the situation that need not carry out follow-up encapsulation fully, make in a large number, not only significantly promote speed of production, reduced manufacturing cost, more need not the packaging insulating colloid because of surface-mountable wafer diode 50, so also significantly improved its thermal conduction characteristic, prolonged its useful life.In addition; the palpus special declaration; though the surface-mountable wafer diode 50 of the present invention can not carry out using under the situation of follow-up encapsulation; only when actual fabrication; be not limited thereto, it can utilize other encapsulation technology and material, encapsulates being exposed to outer p+ type, n type or n+ N- type semiconductor N 11,10,12; with protection p+ type, n type or n+ N- type semiconductor N 11,10,12, make it be difficult for oxidation or impaired.
Claims (9)
1. surface-mountable wafer diode, it has semiconductor grain; It is characterized in that the upper and lower end face of described semiconductor grain is respectively equipped with semiconductor under p+ type semiconductor-on-insulator, the n+ type, following semiconductor bottom is provided with first conductive metal layer; Semiconductor-on-insulator and semiconductor grain are provided with first insulating barrier, and this first insulating barrier separates into this semiconductor-on-insulator and semiconductor grain the central authorities and the peripheral part of mutually insulated; Semiconductor-on-insulator end face middle body is provided with the 3rd conductive metal layer to be equivalent to forming a welding conducting end on semiconductor-on-insulator; Semiconductor-on-insulator end face peripheral part is provided with the 3rd conductive metal layer; Reaching down in semiconductor-on-insulator, semiconductor grain, the semiconductor lateral margin is provided with second conductive metal layer, the 3rd conductive metal layer of one end of second conductive metal layer and semiconductor-on-insulator end face peripheral part is conducted, its other end and semiconductor grain reach down, and the first conductive metal layer lateral margin of semiconductor bottom is conducted, to make semiconductor-on-insulator, semiconductor grain and semiconductor short circuit down, to be equivalent to forming another welding conducting end on the semiconductor down.
2. surface-mountable wafer diode according to claim 1 is characterized in that described semiconductor grain is the n N-type semiconductor N.
3. surface-mountable wafer diode according to claim 1, the 3rd conducting metal series of strata that it is characterized in that central authorities that described semiconductor-on-insulator end face separates with first insulating barrier and peripheral part are with the plating mode setting.
4. surface-mountable wafer diode according to claim 1, it is characterized in that being provided with along the X-direction etching two horizontal grooves of parallel interval from described semiconductor-on-insulator end face, be provided with two vertical grooves of parallel interval along the Y direction etching, this two vertical groove and two horizontal grooves are ccontaining for first insulating barrier, and pass semiconductor grain arrival semiconductor down.
5. surface-mountable wafer diode according to claim 4 is characterized in that described first insulating barrier that is placed in semiconductor-on-insulator and semiconductor grain two vertical grooves and the two horizontal grooves is the glass dielectric layer with the glass cream sintering.
6. surface-mountable wafer diode according to claim 4 is characterized in that described semiconductor down bottom is along Y direction etching conduit; The bottom of conduit and longitudinal and transverse bottom portion of groove keep suitable distance, and the width of this conduit in X-direction approximately corresponding to the two adjacent described width of containing along the vertical groove of Y direction; First conductive metal layer that is arranged at down the semiconductor bottom is sintered in the conduit.
7. surface-mountable wafer diode according to claim 6 is characterized in that coating is provided with second insulating barrier on described first conductive metal layer that is sintered in down in the semiconductor base channel road.
8. surface-mountable wafer diode according to claim 7 is characterized in that the glass dielectric layer of described second insulating barrier for being formed by the glass cream sintering.
9. surface-mountable wafer diode according to claim 1 is characterized in that the described second conducting metal series of strata are arranged at semiconductor-on-insulator, semiconductor grain and following semiconductor lateral margin with sintering processing.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CNB031568904A CN100364112C (en) | 2003-09-11 | 2003-09-11 | Wafer type diode capable of surface mounting |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CNB031568904A CN100364112C (en) | 2003-09-11 | 2003-09-11 | Wafer type diode capable of surface mounting |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| CN1595663A CN1595663A (en) | 2005-03-16 |
| CN100364112C true CN100364112C (en) | 2008-01-23 |
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| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| CNB031568904A Expired - Fee Related CN100364112C (en) | 2003-09-11 | 2003-09-11 | Wafer type diode capable of surface mounting |
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| Country | Link |
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| CN (1) | CN100364112C (en) |
Citations (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US5925924A (en) * | 1995-07-26 | 1999-07-20 | International Business Machines Corporation | Methods for precise definition of integrated circuit chip edges |
| JP2002359328A (en) * | 2001-03-29 | 2002-12-13 | Hitachi Ltd | Semiconductor device |
| TW541598B (en) * | 2002-05-30 | 2003-07-11 | Jiun-Hua Chen | Integrated chip diode |
-
2003
- 2003-09-11 CN CNB031568904A patent/CN100364112C/en not_active Expired - Fee Related
Patent Citations (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US5925924A (en) * | 1995-07-26 | 1999-07-20 | International Business Machines Corporation | Methods for precise definition of integrated circuit chip edges |
| JP2002359328A (en) * | 2001-03-29 | 2002-12-13 | Hitachi Ltd | Semiconductor device |
| TW541598B (en) * | 2002-05-30 | 2003-07-11 | Jiun-Hua Chen | Integrated chip diode |
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| Publication number | Publication date |
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| CN1595663A (en) | 2005-03-16 |
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Granted publication date: 20080123 Termination date: 20110911 |