CN100405615C

CN100405615C - Integrated wafer diode

Info

Publication number: CN100405615C
Application number: CNB021320470A
Authority: CN
Inventors: 陈俊华; 祝孝平
Original assignee: Individual
Current assignee: Individual
Priority date: 2002-09-09
Filing date: 2002-09-09
Publication date: 2008-07-23
Anticipated expiration: 2022-09-09
Also published as: CN1482685A

Abstract

The present invention relates to an integrated wafer diode. A diffusion technique is utilized to respectively form a p+ type semiconductor and an n+ type semiconductor with a final thickness (or an n+ and p+ type semiconductor) on the top and the bottom of a semiconductor wafer, and the semiconductor fabrication technique of figure carving, distributive planting, sintering, etc. is utilized to respectively manufacture a plurality of diodes on the wafer, wherein the lateral margin of each diode is sealed by insulating glass. The p+ type semiconductor and the n+ type semiconductor on both end surfaces of the diode are respectively formed with a conductive metal layer. The partial surface of one of the conductive metal layers is coated with an insulating material, which makes the other conductive metal layer conducted to the insulating material on the other end by a conductive metal layer sintered on the insulating glass. The wafer diode of the present invention can be directly arranged on an associated electronic circuit without a subsequent packaging program, can also effectively improve the heat conduction performance of the diode to ensure that the diode can bear higher working temperature, and the volume of the diode is largely reduced.

Description

Integrated wafer diode

Technical field

The present invention relates to the structure of diode, especially finger is a kind of can be in the manufacturing process of diode crystal particle, directly make the wafer diode that two welding conducting end are positioned at same end face (top or bottom), make effective thermal conduction characteristic that improves diode, and significantly dwindle its volume with glass packaging.

Background technology

General diode element of commonly seeing on the market, its basic structure comprises a silicon crystal grain, the biend of this silicon crystal grain is welded with a conductive metal sheet respectively, and the another side of these conductive metal sheets is welded a lead more respectively, and these leads of mat are connected with other electronics stitch.In the manufacturing process of the diode element that this kind commonly seen, after this silicon crystal grain and conductive metal sheet are combined into one, need this silicon crystal grain is carried out etch processes, after waiting to finish etch processes, need again by the encapsulation process program, in this silicon crystal grain and conductive metal sheet periphery, encapsulation one insulation colloid is promptly made general diode element.

Commonly use in the processing procedure of diode element at these, after silicon crystal grain is finished etch processes, all be with resin or other colloid, it is encapsulated, because the heat resisting temperature of these resins or colloid is not high, Gu Dangqi is used as the rectifier cell of high power input current, or when being used in hot environment, very easily Yin Gaore and impaired causes relevant electronic equipment can't normally use, and has a strong impact on the useful life and the quality of electronic equipment, and cause many puzzlements in the maintenance, in addition, owing to these resins or the formed encapsulating housing of colloid, must take a certain size space, so make these volumes of commonly using diode element, can't further dwindle all the time.

Summary of the invention

Because existing problems on the existing diode, the invention people adheres to this industry experience for many years of being engaged in, and by continuous effort research and experiment, develops a kind of integrated wafer diode.

A purpose of the present invention, be on the same end (top or bottom) at each diode, form two and independently weld conducting end, make that respectively this welding conducting end can the p+ and the n+ N-type semiconductor N of this diode be conducted respectively with respectively, make produced wafer diode, but possess the characteristic of a mounted on surface (surfacemounting) type element, can directly be installed on the relevant electronic circuit.

Another object of the present invention is in manufacturing process, can utilize glass sintering to handle, and directly insulating glass is coated on this crystal grain periphery, with effective thermal conduction characteristic that improves diode, guarantees that it can bear bigger working temperature, and significantly dwindles its volume.

Another purpose of the present invention is to need not under the processing of follow-up canned program, can produce the diode finished product that can supply mounted on surface (SMD).

For reaching above-mentioned purpose, integrated wafer diode of the present invention, mainly be to utilize diffusion (diffusion) technology, top and bottom at semiconductor wafer (wafer), form the p+ and the n+ N-type semiconductor N (or n+ and p+ N-type semiconductor N) of a predetermined thickness respectively, utilize statue again, etching, cloth is planted and semiconductor fabrication techniques such as sintering, on this wafer (Wafer), produce a plurality of diodes respectively, respectively the lateral margin of this diode gives involution with insulating glass, on the p+ of its biend and the n+ N-type semiconductor N, then be formed with a conductive metal layer respectively, on the local surfaces of a conductive metal layer wherein, and be coated with an insulating material, and make this another conductive metal layer can pass through the another conductive metal layer of institute's sintering on this insulating glass, conducting is to this insulating material of other end.

Wafer diode of the present invention need not follow-up canned program, can directly be installed on the relevant electronic circuit, also can effectively improve the thermal conduction characteristic of diode, guarantees that it can bear bigger working temperature, and significantly dwindles its volume.

For can be more specifically and clearly express design concept of the present invention, architectural feature and fabrication schedule, enumerate the embodiment of several internal organs now, and cooperate diagram, be described in detail as follows:

Description of drawings

Figure 1 shows that in a preferred embodiment of the present invention generalized section after diffusing out the p+ type semiconductor layer on the wafer;

Fig. 2 a and 2b are depicted as in this preferred embodiment, utilize statue and trench etched technology X-X and the Y-Y cross-sectional view after forming a plurality of rectangular recess on the wafer;

Fig. 3 a and 3b are depicted as in this preferred embodiment, X-X after diffusing out the n+ type semiconductor layer on the wafer and Y-Y cross-sectional view;

Fig. 4 a and 4b are depicted as in this preferred embodiment, insert metal cream in these grooves, and it is carried out X-X and Y-Y cross-sectional view behind the sintering;

Figure 5 shows that in this preferred embodiment, on the X-X of cross section, be positioned at the position between two adjacent the first metal layers,, utilize statue and trench etched technology, offer the X-X cross-sectional view behind the conduit along Y direction;

Fig. 6 a and 6b are depicted as in this preferred embodiment, and with crystalline substance of heap of stone or cloth planting technology, in the bottom of this wafer, crystalline substance of heap of stone or cloth plant X-X and the Y-Y cross-sectional view behind the silicon dioxide layer;

Figure 7 shows that in this preferred embodiment, utilize statue and trench etched technology, between two adjacent conduits,, offer the X-X cross-sectional view behind the groove along Y direction;

Figure 8 shows that in this preferred embodiment, in the position of these conduits and groove, insert metal cream, and it is carried out sintering, form the X-X cross-sectional view behind second and third metal level;

Fig. 9 a and 9b are depicted as in this preferred embodiment, utilize statue and trench etched technology, along Y direction, and X-X and Y-Y cross-sectional view after offering another conduit and another groove above this wafer;

Figure 10 a and 10b are depicted as in this preferred embodiment, with glass paste, insert in this conduit and the groove, and it is carried out X-X and Y-Y cross-sectional view after the sintering processes;

Figure 11 shows that in this preferred embodiment by this wafer end face, along Y direction, the glass in this conduit respectively carries out the post-job X-X cross-sectional view of borehole;

Figure 12 a and 12b are depicted as in this preferred embodiment, in this wafer end face, to the scope of these slotted eyes, form X-X and Y-Y cross-sectional view behind the 4th metal level corresponding to the upper surface of this p+ N-type semiconductor N;

Figure 13 a and 13b are depicted as in this preferred embodiment, and in this wafer end face, corresponding to the position of this p+ N-type semiconductor N, sintering goes out X-X and the Y-Y cross-sectional view behind one deck insulating glass;

Figure 14 a and 14b are depicted as in this preferred embodiment, this wafer is cut gradation after, the X-X of this wafer diode finished product and Y-Y cross-sectional view;

Figure 15 a and 15b are depicted as in another preferred embodiment of the present invention, the X-X of this wafer diode finished product and Y-Y cross-sectional view.

Embodiment

The present invention is a kind of integrated wafer diode and method for making thereof, mainly be to utilize diffusion technique, top and bottom at the semiconductor wafer, form the different shaped semiconductor of a predetermined thickness respectively, on this wafer, produce a plurality of diodes more respectively, respectively the lateral margin of this diode gives involution with insulating glass, on the different shaped semiconductor surface of its biend, be formed with a conductive metal layer respectively, on the local surfaces of a conductive metal layer wherein, and be coated with an insulating material, make this another conductive metal layer can pass through the another conductive metal layer of institute's sintering on this insulating glass, conducting to this insulating material of other end on, and with this conductive metal layer, on the same end face of this diode, form two and independently weld conducting end, make this welding conducting end respectively can be respectively with this diode respectively on the different shaped semiconductor be conducted, make it under the processing that need not the back canned program, can produce diode finished product for mounted on surface.The present invention is referred to as integrated wafer diode (IntegratedChip Diode is called for short ICD) with it in follow-up description.

Because, in the processing procedure of this integrated wafer diode, along the X-X and the produced structure of Y-Y section of aforesaid semiconductor material, and inequality, so the present invention will specialize its difference on X and Y-axis cross-section structure in each following embodiment explanation.

In a preferred embodiment of the present invention, can be earlier in wafer 10 (wafer) top of a n N-type semiconductor N, consult shown in Figure 1ly, ions diffusion is gone into the upper strata of this n type wafer 10, forms the p+ N-type semiconductor N 11 of a predetermined thickness; Utilize statue and trench etched technology again, in n type wafer 10 bottoms, according to required actual size, etch a plurality of rectangular recess 20, consult shown in Fig. 2 a, for making the X-X schematic cross section of the required wafer of four wafer diodes, wherein be presented at and offer 2 rectangular recess 20 on the X-X cross section, consult shown in Fig. 2 b, offer 4 rectangular recess 20 on the Y-Y vertical section for making the Y-Y vertical section schematic diagram of the required wafer of a wafer diode, wherein being presented at; Then, the present invention diffuses into phosphonium ion the bottom of this n type wafer 10 again, forms the n+ N-type semiconductor N 12 of a predetermined thickness, consults X-X shown in Fig. 3 a, the 3b and Y-Y cross-sectional view; Then, in these grooves 20, insert metal cream (as copper cream, silver paste, gold paste ... wait material) again, and it is carried out sintering, consult X-X shown in Fig. 4 a, the 4b and Y-Y cross-sectional view, respectively not form a first metal layer 13 in this groove 20; Treat that the present invention is again on section X-X, be positioned at the position of 13 of two adjacent the first metal layers, along Y direction, utilize statue and trench etched technology, offer a conduit 21, consult X-X cross-sectional view shown in Figure 5, the degree of depth of this conduit 21 need be passed this n+ N-type semiconductor N 12, arrives the n N-type semiconductor N position of this wafer 10; Then, build brilliant method (in this other bright embodiment with CVD (Chemical Vapor Deposition) again, also can utilize PVD (Physical Vapor Deposition) or PCVD brilliant methods of heap of stone such as (Photon-induce Chemical Vapor Deposition)) or the cloth planting technology, bottom in this wafer 10, promptly this metal level 13 and this conduit 21 surfaces brilliant (or cloth is planted) upward of heap of stone go out a silicon dioxide layer 14, consult X-X shown in Fig. 6 a, the 6b and Y-Y cross-sectional view, with first insulating barrier of this silicon dioxide layer 14 as this wafer diode.

Especially note at this, be in this embodiment, though be with ion diffusion, top and bottom at a n N-type semiconductor N wafer 10, form the P+ N-type semiconductor N 11 and the n+ N-type semiconductor N 12 of a predetermined thickness, but the interest field that the present invention advocated, be not limited thereto, press all this skill personages that is familiar with,, utilize other diffusion method or cloth planting technology according to the disclosed technology contents of the present invention, wafer 10 (wafer) top and bottom (or bottom and top) in a n type or p N-type semiconductor N, form the n+ N-type semiconductor N and the p+ N-type semiconductor N (or p+ N-type semiconductor N and n+ N-type semiconductor N) of a predetermined thickness, should still belong to the alleged semiconductor crystal wafer of the present invention, close first Chen Ming.

Then, in this embodiment, utilize statue and trench etched technology again, in between two adjacent conduits 21, along Y direction, offer a groove 22, consult X-X cross-sectional view shown in Figure 7, the degree of depth of this groove 22 is to pass insulation material layer 14 (being silicon dioxide layer) and arrival the first metal layer 13; Then, again in the position respectively at these conduits 21 and groove 22, insert metal cream (as: copper cream, silver paste, gold paste ... wait material), and it is carried out sintering, to form second and

third metal level

15 and 16 respectively, consult X-X cross-sectional view shown in Figure 8, make the 3rd metal level 16 just can pass through this first metal layer 13, be conducted with this n+ N-type semiconductor N 12, and as on the wafer diode of the present invention in order to a weld metal layers of this n+ N-type semiconductor N 12 of conducting.

Then, in this embodiment, utilize statue and trench etched technology again, along Y direction, in the position of these wafer 10 tops corresponding to second and

third metal level

15 and 16, offer another conduit 31 and another groove 32 respectively, consult the X-X cross-sectional view shown in Fig. 9 a, wherein the degree of depth of this another conduit 31 just arrives this silicon dioxide layer 14, the degree of depth of this another groove 32 is then passed this n+ N-type semiconductor N 12, arrive this first metal layer 13, and,, offer a groove 33 respectively then in the position of these wafer 10 tops corresponding to 13 of adjacent this first metal layers along X-direction, consult the Y-Y cross-sectional view shown in Fig. 9 b, the degree of depth of this groove 33 just arrives this silicon dioxide layer 14.

Then, the present invention will evenly modulate the glass paste that mixes by glass powder and glue again, insert in these

grooves

32,33, consult X-X shown in Figure 10 a, the 10b and Y-Y cross-sectional view, and it is carried out sintering processes, make the

glass

34,35 and 36 of finishing sintering, just can be coated on the lateral margin of wafer diode of the present invention, finish encapsulation this wafer diode lateral margin; Then, again by these wafer 10 end faces, along Y direction, glass 34 in this conduit 31 respectively carries out the borehole operation, excavates unnecessary glass, only keep the part that is enough to encapsulate this wafer diode lateral margin, consult X-X cross-sectional view shown in Figure 11, and make slotted eye 40 degree of depth of being excavated, just can arrive this second metal level 15; Then, again respectively at these wafer 10 end faces, corresponding to the upper surface of this p+ N-type semiconductor N 12 to the scope of these slotted eyes 40, insert low-temperature metal cream (as copper cream, silver paste, gold paste ... wait material), and it is carried out sintering, consult Figure 12 a, X-X shown in the 12b and Y-Y cross-sectional view, to form the 4th metal level 41, make this second metal level 15 just can pass through the 4th metal level 41, be conducted with this p+ N-type semiconductor N 11, and make this second metal level 15 can be used as on the wafer diode of the present invention another weld metal layers in order to this P+ N-type semiconductor N 11 of conducting.

At last, again in these wafer 10 end faces, position corresponding to this P+ N-type semiconductor N 11, coating one deck insulating glass slurry, and it is carried out sintering processes, consult X-X shown in Figure 13 a, the 13b and Y-Y cross-sectional view,, finish encapsulation this wafer diode end face on this p+ N-type semiconductor N 11, to form an insulating glass layer 42; Then, respectively along X and Y-axis,, this wafer 10 is cut gradation again corresponding to the position of this another conduit 31, another groove 32 and groove 33, plural the wafer diode 50 of finishing encapsulation be can produce, X-X shown in Figure 14 a, the 14b and Y-Y cross-sectional view consulted.In this embodiment, respectively on the same end face (bottom) of this wafer diode 50, be formed with two weld metal layers (being second and third metal level 15 and 16) independently, make that respectively this weld metal layers can the p+ and the n+ N-type semiconductor N of this diode be conducted the welding conducting end during as mounted on surface (SMD) respectively with respectively.

The present invention makes it be difficult for oxidation for protection respectively this metal level on this wafer diode 50, can it be electroplated again, and with on this metal level respectively, forms protective layer; Then, in regular turn this wafer diode is respectively tested and packed again, so, can be under the situation that need not follow-up canned program processing, produce the wafer diode finished product that can supply mounted on surface (SMD), not only can significantly dwindle its volume, and characteristic is led in the pass that can effectively improve diode.

In another embodiment of the present invention, the X-X of its finished product 60 and Y-Y cross-section structure, shown in Figure 15 a, 15b, identical with previous embodiment, also be to utilize diffusion technique and trench etched technology, in the top and the bottom of semiconductor wafer 10, form p+ and n+ N-

type semiconductor N

11 and 12 of a predetermined thickness respectively, in this formed groove in n+ N-type semiconductor N 12 bottoms, insert metal cream again, and it is carried out sintering, respectively to form a first metal layer 13 in this groove respectively; Go up brilliant (or cloth is planted) of heap of stone in these metal level 13 surfaces again and go out-silicon dioxide layer 14, make with first insulating barrier of this silicon dioxide layer 14 as this wafer diode.Then, utilize statue and trench etched technology again, on this silicon dioxide layer 14 corresponding to the position of 13 of adjacent the first metal layers, along Y direction, offer a groove, the degree of depth of this groove just arrives the first metal layer 13, in these grooves, inserts metal cream again, and it is carried out sintering, to form one second metal level 61, make this second metal level 61 just can pass through this first metal layer 13, be conducted with this n+ N-type semiconductor N 12.

Then, in this another embodiment, utilize statue and trench etched technology again, respectively along X and Y direction, in the position of these wafer 10 tops corresponding to 13 of adjacent the first metal layers, offer a groove 62, the degree of depth of this groove 62 is then passed this n+ N-type semiconductor N 12, arrives this first metal layer 13, and on the X-X section, in 62 of two adjacent grooves, along Y direction, other offers a conduit 63, and the degree of depth of this conduit 63 just arrives this n+ N-type semiconductor N 12, make this P+ N-type semiconductor N 11 on the X-X section, separated into two partly.

Then, this another embodiment will evenly modulate the glass paste that mixes by glass powder and glue again, insert in these conduits 63, the groove 62 and the upper surface of a part of P+ N-type semiconductor N 11, and to its disconnected sintering processes, make the

glass

74,75 and 76 of finishing sintering, just can be coated on the lateral margin of won ton sheet type diode of the present invention, finish encapsulation this wafer diode lateral margin; Then, again by this wafer end face, along Y direction, to the glass 74 in second metal level, the 61 pairing grooves 62, carry out the borehole operation, excavate unnecessary glass, only keep the part that is enough to encapsulate this wafer diode lateral margin, and make slotted eye 80 degree of depth of being excavated, just can arrive this second metal level 61; Then, again respectively at this wafer end face, corresponding to coated with glass not should ++ in the upper surface of N-type semiconductor N 12 and these slotted eyes 80, insert low-temperature metal cream, and it is carried out sintering, to form one the 3rd metal level 64 and the 4th metal level 65 respectively, make the 4th metal level 65 can pass through this second metal level and this

first metal layer

61 and 13 in regular turn, be conducted with this n+ N-type semiconductor N 12, and make the 4th metal level 65 can be used as on the wafer diode of the present invention weld metal layers in order to this n+ N-type semiconductor N 12 of conducting, the 3rd metal level 64 then can be conducted with this p+ N-type semiconductor N 11, as on the wafer diode of the present invention in order to another weld metal layers of this P+ N-type semiconductor N 11 of conducting.So, this another embodiment can be on the same end face (top) of this wafer diode 60 respectively, formation two is weld metal layers (i.e. the 3rd and the 4th metal level 64 and 65) independently, make that respectively this weld metal layers can the p+ and the n+ N-

type semiconductor N

11 and 12 of this diode be conducted the welding conducting end during as mounted on surface (SMD) respectively with respectively.

Though the present invention discloses as above with preferred embodiment; right its is not in order to qualification the present invention, any those who are familiar with this art, without departing from the spirit and scope of the invention; when can doing a little change and retouching, so the present invention's protection range is as the criterion when looking claims scope person of defining.

Claims

1. integrated wafer diode, it is characterized in that: utilize diffusion technique, biend at the semiconductor wafer, form veriform first semiconductor and second semiconductor of a predetermined thickness respectively, on this wafer, produce a plurality of diodes more respectively, respectively the lateral margin of this diode gives involution with insulating glass, wherein be formed with the first metal layer on first semiconductor surface of an end face, be provided with first groove in the position that is positioned between adjacent the first metal layer, on the surface of this first metal layer and this groove, be coated with an insulation material layer, second metal level is set on the insulation material layer in first groove, side insulating glass in the lateral margin of described respectively this diode arrives this insulation material layer from the second semiconductor end face, the 3rd metal level is positioned at second metal level, one side and passes insulation material layer and contacts with the first metal layer, in this side insulating glass, be provided with and pass the 4th metal level that insulation material layer arrives this second metal level, second semiconductor of this diode other end passes insulation material layer and this second metal level conducting by the 4th metal level, on the first semiconductor end face of this diode, form two by second metal level and the 3rd metal level and independently weld conducting end, make respectively this welding conducting end can be respectively with this diode respectively on veriform first and second semiconductors be conducted.

2. integrated wafer diode, it is characterized in that: utilize diffusion technique, biend at the semiconductor wafer, form veriform first and second semiconductors of a predetermined thickness respectively, on this wafer, produce a plurality of diodes more respectively, respectively offer a conduit on this diode, this conduit passes second semiconductor of an end face, its degree of depth just arrives first semiconductor of other end, make this second semiconductor be separated into two partly, respectively the lateral margin of this diode and this conduit give involution with insulating glass, wherein be formed with the first metal layer on the surface of the first semiconductor end face, the first metal layer is provided with insulation material layer, at adjacent insulating material interlayer second metal level being set passes insulation material layer and contacts with the first metal layer, side insulating glass in the lateral margin of described respectively this diode arrives second metal level from the second semiconductor end face, the 4th metal level that arrives this second metal level is set in this side insulating glass, at the second semiconductor end face the 3rd metal level is set, on the second semiconductor end face of this diode, form two by the 3rd metal level and the 4th metal level and independently weld conducting end, make respectively this welding conducting end can be respectively with this diode respectively on veriform semiconductor be conducted.