CN100359491C - Addressing space extending method of 16M syllable data storage based on MCS-51 structure - Google Patents
Addressing space extending method of 16M syllable data storage based on MCS-51 structure Download PDFInfo
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Abstract
The present invention relates to an addressing space extending method of a 16M byte data memory on the basis of an MCS-51 structure, which is based on an 8051 system. A time sharing multiplexing method is used to carry out auxiliary design in a segment form to the data memory. The addressable data memory space of 16M bytes is divided into 256 pages, 256 page addresses are determined by high eight bit data addresses, and each page is provided with the data addressing space of 64 K bytes. Page inside addresses are determined by middle eight bit data addresses and low eight bit data addresses in the data addresses. The addressing space of an external data memory is extended to 16 M bytes from 64 K bytes under the conditions that an address bus is not increased, and the entire instruction system is not changed. Thereby, a microcontroller based on the MCS-51 structure can carry out calculation with large data amount. The addressing space extending method of a 16M byte data memory on the basis of an MCS-51 structure can be applied to a single chip microcontroller based on the 8051 instruction system, and can also be applied to other microcontrollers, microprocessors, etc.
Description
Technical field
The present invention relates to a kind of 16M byte data memory addressing space extending method of the microprocessor based on Intel MCS-51 framework, can be applicable to the single chip microcontroller of MCS-51 instruction system, also can be applicable to fields such as other microcontroller, microprocessor.
Background technology
Data-carrier store (Data Memory) is to be used for one section storage space of store data, and microcontroller or microprocessor can be read pending data in this section space, also can be being write this section space by particular procedure data later.
Microprocessor based on Intel MCS-51 framework has 16 bit address buses, data memory space that can addressing 64K byte.For the very huge particular system of data operation quantity, such as digital image processing system, the quantity of information of every two field picture is just very huge, if this system also comprises functions such as knowledge-base management, knowledge self study, the data memory space of 64K byte will can not satisfy the demand of this type systematic far away so.Again owing to the microcontroller based on the IntelMCS-51 framework is to use a class processor very widely, use with a long history, abundant third party's support software and emulation tool are arranged, by numerous slip-stick artists are familiar with, therefore if can not increase under the situation of address bus again neither changing order set, the addressing space of expanding data storer will improve the performance of 8051 framework microcontrollers greatly to the 16M byte.
Summary of the invention
The object of the present invention is to provide a kind of data-carrier store addressing space extending method based on the MCS-51 framework, do not increase at address bus, under the constant situation of whole instruction system, the external data memory addressing space extends to the 16M byte from the 64K byte, thereby makes the microcontroller based on the MCS-51 framework can move the extremely complicated program of big quantity algorithm.
For achieving the above object, design of the present invention is as follows:
Realize addressing capability, do not revise the instruction set compatible mutually, and adopt the auxiliary design method that data-carrier store is carried out segmentation with standard 8051 based on the 16M byte data storer of MCS-51 framework.The data space that is about to addressable 16M byte is divided into 256 pages or leaves, and page address has 256 page addresss by the decision of high eight-bit data address.The data addressing space that the 64K byte is arranged in each page is by eight and the interior address of decision page or leaf, low eight bit data address in the data address.The most-significant byte of data pointer page register (DATA POINTER PAGE) storage 24 bit data memory addressing space address; The least-significant byte of data pointer least-significant byte register (DPL) storage 24 bit data memory addressing space address; 8 of the centres of data pointer most-significant byte register (DPH) storage 24 bit data memory addressing space address.
According to above-mentioned design, the present invention adopts following technical proposals:
A kind of 16M byte data memory addressing space extending method based on the MCS-51 framework, based on 8051 systems, it is characterized in that adopting the method for time-sharing multiplex, the data storer is carried out the segmentation Aided Design, the data space of addressable 16M byte is divided into 256 pages or leaves, page address is determined by the high eight-bit data address, have 256 page addresss, the data addressing space that the 64K byte is arranged in each page, by eight and the interior address of decision page or leaf, low eight bit data address in the data address, address bus do not increase with the constant situation of whole instruction system under, the external data memory addressing space is extended to the 16M byte from the 64K byte;
Its concrete steps are:
A. set page address special function register DPTR_PAGER, determine the high eight-bit data address;
B. setting data pointer register DATA_POINTER determines low 16 bit data addresses;
C. condition that produces according to page address and situation is different, following two kinds of situations is considered in the generation of data page address in the space extended operation of data memory addressing, and set coherent signal:
(a) page address that directly provides of user;
(b) page address that upgrades automatically;
D. condition that produces according to data pointer and situation is different, following three kinds of situations is considered in the generation of data pointer in the space extended operation of data memory addressing, and set coherent signal:
(a) data pointer that directly provides of user;
(b) data pointer is from increasing one (INC DPTR) instruction;
(c) data pointer is from subtracting one (DEC DPTR) instruction;
E. external data memory address XRAMA content of registers determines;
The method of above-mentioned setting page address special function register DPTR_PAGER is:
The address of determining page address special function register DPTR_PAGER is 95H, and size is 8, the interior content decision of register thus of the high eight-bit address of data-carrier store 16M byte addressing space;
After the system reset, the value of DPTR_PAGER is #00H; The value of DPTR_PAGER can also be upgraded automatically by system except can being defined voluntarily by the user.
The method of above-mentioned setting data pointer special function register DATA_POINTER is:
Data pointer special function register DATA_POINTER has 16, the interior content decision of register thus of low 16 bit address of data-carrier store 16M byte addressing space, and DATA_POINTER is made up of DPL register and DPH register.The DPL register is being deposited the least-significant byte data of DATA_POINTER; The DPH register is being deposited the most-significant byte data of DATA_POINTER;
After the system reset, the value of DATA_POINTER is #0000H; The value of DATA_POINTER can also be upgraded automatically by system except can being defined voluntarily by the user.
The concrete steps that above-mentioned two kinds of situations according to the page address generation are divided into phasing pass signal are:
A. relevant with the User Defined page address register and signal:
REG_RESULT: the page address content eight bit register that the user defines voluntarily;
DPTR_PAGER_WRITE: to page address special function register DPTR_PAGER carry out write operation with imitating signal;
When the DPTR_PAGER_WRITE signal was high level, the value of REG_RESULT write in the page address special function register DPTR_PAGER;
B. produce when striding page when page address, must be because of INC_DPTR instruction or the DEC_DPTR instruction causes the value of data pointer register DPTR_PAGER to become #0000H by #FFFFH or #0000H becomes #FFFFH, thereby a page phenomenon appears striding, at this moment data pointer register DPTR_PAGE content will increase " 1 " automatically or subtract " 1 ", the 16M external data memory insert when realizing striding access to web page or subtract page or leaf.
The concrete steps that above-mentioned three kinds of situations according to the data pointer generation are divided into phasing pass signal are:
A.PC_CON[12]: MOV_DPTR, the decoded signal of #16addr instruction;
DP_EN: data pointer enable signal;
In first clock period of second machine cycle of instructing, if PC_CON[12] be high level, then DP_EN becomes the high level useful signal; In second clock period of second machine cycle of instructing, if the DP_EN signal is effective, then 16 bit data pointer values are admitted among the data pointer register DATA_POINTER;
B.PC_CON[14]: the decoded signal of INC_DPTR instruction;
In the 4th clock period of first machine cycle of instructing, if PC_CON[14] be the high level useful signal, then DP_EN becomes the high level useful signal; In first clock period of second machine cycle of instruction,, then add 16 bit data pointer values after upgrading and be admitted among the data pointer register DATA_POINTER if the DP_EN signal is effective;
C.PC_CON[17]: the decoded signal of DEC_DPTR instruction;
In the 4th clock period of first machine cycle of instructing, if PC_CON[17] be the high level useful signal, then DP_EN becomes the high level useful signal; In first clock period of second machine cycle of instruction,, then subtract 16 bit data pointer values after upgrading and be admitted among the data pointer register DATA_POINTER if the DP_EN signal is effective.
The method of above-mentioned setting external data memory address XRAMA content of registers is:
Totally 24 in external data memory address XRAMA register is being stored 24 specific address of data-carrier store; XRAMA is made up of data-carrier store page address register DPTR_PAGER and XRAMA_TP register; Data-carrier store page address register DPTR_PAGER is storing the most-significant byte address; The XRAMA_TP register-stored low 16 bit address;
High eight-bit in the XRAMA register of external data memory address and middle eight are sent by the timesharing of PORT2 mouth; Low eight and 8 bit data signals in the XRAMA register of external data memory address are by PORT0 mouth timesharing transmission, so total address bus still is 16.
The method of above-mentioned setting special function register DPL is:
The address of determining special function register DPL is 82H, and size is 8, the interior content decision of register thus of low eight bit address of data-carrier store 16M byte addressing space;
After the system reset, the value of DPL is #00H; The value of DPL can also be upgraded automatically by system except can being defined voluntarily by the user.
The method of above-mentioned setting special function register DPH is:
The address of determining special function register DPH is 83H, and size is 8, the interior content decision of register thus of centre eight bit address of data-carrier store 16M byte addressing space;
After the system reset, the value of DPH is #00H; Its value of DPH can also be upgraded automatically by system except can being defined voluntarily by the user.
The concrete steps of above-mentioned definite REG_RESULT content of registers are:
The value of 8 REG_RESULT registers comes from 8 program storage input data register PROGDI, and the content of PROGDI is made up of 8 bit data of external program memory data line output, is the content of the data-carrier store page address of user oneself definition; PROGDI links to each other with PORT0I, and PORT0I is 8 bit data input ports of microcontroller, and PORT0I can be connected on the external program memory DOL Data Output Line.
The concrete steps of above-mentioned definite DPTR_PAGER_WRITE signal are:
1 DPTR_PAGER_WRITE signal is write enable signal SFR_WRITE_EN[25 by 1 special function register] decision; When the value of 8 destination address register DESTIN_ADDR is #15H, SFR_WRITE_EN[25] put one, when the value of DESTIN_ADDR is other any values, SFR_WRITE_EN[27] by zero setting; The value of DESTIN_ADDR is by 8 program storage input data register PROGDI decision, and PROGDI is connected on the PORT0I, and PORT0I is 8 bit data input ports of microcontroller, and it can be connected on the external program memory DOL Data Output Line.
The concrete steps of above-mentioned definite DP_EN signal are:
DP_EN has three sources.In the 4th clock period of first machine cycle of instruction, if decoded signal PC_CON[14] high level is effective, and then DP_EN puts one; In the 4th clock period of first machine cycle of instruction, if decoded signal PC_CON[17] high level is effective, and then DP_EN puts one; In first clock period of second machine cycle of instruction, if decoded signal PC_CON[12] high level is effective, and then DP_EN puts one; Other any situation, DP_EN is by zero setting.
The concrete steps of above-mentioned definite XRAMA_TP content of registers are:
PC_CON[5] signal is the decoded signal of MOVX@Ri class instruction, its significant level is a high level;
Work as PC_CON[5] for for the moment, be that the instruction of MOVX@Ri class is just processed, at this moment, the value of XRAMA_TP is by the decision of the value in value on the PORT2 mouth and the SOURCE_DI register, and the content that the SOURCE_DI register is deposited is determined and goes up the value in certain unit on the data-carrier store; PORT2 deposits the high eight-bit of XRAMA_TP; The SOURCE_DI register is deposited low eight of XRAMA_TP;
As PC_CON[5] when being zero, i.e. instruction beyond the MOVX@Ri class instruction is just processed, and this moment, the value of XRAMA_TP was exactly the value of data pointer register DATA_POINTER.
The present invention compared with prior art, have following conspicuous outstanding substantive distinguishing features and remarkable advantage: the present invention is based on 8051 systems, adopt the method for time-sharing multiplex, do not increase at address bus, under the constant situation of whole instruction system, the external data memory addressing space extends to the 16M byte from the 64K byte, thereby makes the microcontroller based on the MCS-51 framework can carry out the great computing of data volume.This 16M byte program memory addressing space extending method based on the MCS-51 framework can be applicable to the single chip microcontroller based on 8051 instruction systems, also can be applicable to fields such as other microcontroller, microprocessor.
Description of drawings:
Fig. 1 is the data memory structure that 16M byte data memory addressing space extending method adopts.
Fig. 2 is a time-sharing multiplex bus method synoptic diagram.
Fig. 3 is an access external data memory read sequential chart.
Fig. 4 is an access external data memory write sequential chart.
Fig. 5 is MOV 95H, #0AAH User Defined page address instruction sequencing figure.
Fig. 6 is that page address is from increasing an instruction sequencing figure.
Fig. 7 is that page address is from subtracting an instruction sequencing figure.
Embodiment
Details are as follows for a preferred embodiment of the present invention:
This 16M byte data memory addressing space extending method based on the MCS-51 framework adopts following data memory structure (see figure 1)
● data address (DATAADDRESS): the specific address of data-carrier store internal element, totally 24, the data memory space of addressable 16M byte.
● data pointer (DATA POINTER): data memory space is divided into 256 pages or leaves virtually, the space size of each page is the 64K byte, totally 16 of data pointers are the addresses of each page internal element, and its value is identical with low 16 bit address of data address.
● page address (PAGE ADDRESS): data memory space is waited to be divided into 256 pages or leaves virtually, and each page or leaf all has an address, is called page address, and totally 8, from 00H to FFH, its value is identical with the high eight-bit address of data address.
From this data memory structure as can be seen, data memory space is waited to be divided into 256 pages virtually, and the size of each page is the 64K byte, has so just formed the addressing space of 16M byte.Thereby expanded the capacity of data-carrier store greatly, made microcontroller can carry out the great computing of data volume based on the MCS-51 framework.For the figure place that keeps address bus is consistent with standard 8051, the present invention has adopted the method (see figure 2) of time-sharing multiplex address bus:
● the PORT0 mouth: one group of 8 I/O mouth of microcontroller, its timesharing transmit the least-significant byte address and the 8 bit data signals of 24 bit data addresses.
● the PORT2 mouth: one group of 8 I/O mouth of microcontroller, its timesharing transmits the most-significant byte address of 24 bit data addresses, i.e. centre 8 bit address of page address and 24 bit data addresses.
● latch 1 (LATCH_1): the least-significant byte address of these latches 24 bit data addresses.
● latch 2 (LATCH_2): the most-significant byte address of these latches 24 bit data addresses.
● address latch enable signal (ALE): when the address latch signal was effective, the least-significant byte of 24 bit data addresses and most-significant byte were latching to latch 1 and latch 2 respectively.
● read/write signal
The signal low level is effective, is connected on external data memory OE signal wire and the WE signal wire.
As can be seen from Figure 2, when ale signal is effective, latch 1 and latch 2 latch the least-significant byte and the most-significant byte of 24 bit data addresses respectively, in next system clock cycle, ale signal is invalid, 8 of the centres of 24 bit data addresses directly export in the middle of the external data memory on the 8 bit address signal wires from the PORT2 mouth, have realized the expansion in the 16M byte data memory addressing space of standard 8051 with the method for this time-sharing multiplex address bus.Its basic read/write sequential is seen Fig. 3 and Fig. 4:
● system clock (CLOCK): the frequency of operation when system moves.
● the machine cycle (MACHINE CYCLE): the machine cycle was made up of several clock period, M the clock period of CNPM representative in N machine cycle.
Read signal among the figure
And write signal
The width difference, this is the signal that reads because of data
Can before address stable, set up, and can not influence finally reading of data.But for write signal
Just must be after data and address be all stablized effectively could be effectively, simultaneously as long as write signal
Have individual pulse that the write data storer is just had and data can be write in the entry data memory, think that the data that guarantee to write external data memory are correct,
Signal can guarantee correct the writing of data well effectively at the C4P1 beat.
Specific implementation method is:
Page address register DPTR_PAGER of definition in the special function register (SFR) that standard 8051 keeps, the address is 95H.
Page address register DPTR_PAGER is defined as follows:
| Bit 7 | Bit 6 | Bit 5 | Bit 4 | Bit 3 | Bit 2 | Bit 1 | Bit 0 |
DPTR_PAGER address: 95H
The user wants the specific page address contents to carry out write operation to this special function register.Data pointer returns the 0th page after the system reset, and page address is 00H.When trans-sectoral visit occurring, page address can add one automatically, perhaps subtracts one.
(1) scheme of 16M byte data memory addressing space extending method:
Because 16M byte data storer is divided into 256 pages, design of each page and standard 8051 basically identicals seem particularly important so how to design the page address sequential relationship.The source of page address is except that the page address that reset back acquiescence page address 00H and user write, and will consider to stride automatically the situation of page or leaf when design.
(2) dependent instruction sequential chart:
A. User Defined page address (see figure 5)
75 95 AA are MOV 95H, the machine code of #0AAH instruction, and 95H is the address of page address special function register DPTR_PAGER, #0AAH is user-defined page address.
Clock period in this instruction, PORT0 reads the operational code 75 of this instruction from program storage; At the CLP1 of this instruction, user-defined page address numerical value #0AAH deposits the REG_RESULT register in; At this instruction CLP4, the DPTR_PAGER_WRITE signal is effective, becomes high level; The rising edge of first clock period behind this order fulfillment, the temporary page address #0AAH of REG_RESULT register imports among the page address special function register DPTR_PAGER, and this moment, the most-significant byte of external data memory address register XRAMA was updated to user-defined page address value #0AAH.
B. stride page or leaf automatically
1. page address is from increasing a (see figure 6)
A3 is the machine code of INC DPTR instruction, and before this instruction was performed, the value of DPTR data pointer was #0FFFFH; Page address is 55.
In the previous clock period of this instruction, the PORT0 mouth reads in this instruction operation code A3 from program storage; At this instruction CLP1, the value of data pointer becomes #0000H from increasing after one from #0FFFFH; The rising edge of first clock period behind this order fulfillment, the value of page address special function register DPTR_PAGER be from increasing to 56, realized that external data memory strides a page function automatically.
2. page address is from subtracting a (see figure 7)
A5 is the machine code of DEC DPTR instruction, and before this instruction was performed, the value of DPTR data pointer was #0000H; Page address is 55.
In the previous clock period of this instruction, the PORT0 mouth reads in this instruction operation code A5 from program storage; At this instruction CLP1, the value of data pointer becomes #0FFFFH from subtracting after one from #0000H; The rising edge of first clock period behind this order fulfillment, the value of page address special function register DPTR_PAGER be from being kept to 54, realized that external data memory strides a page function automatically.
Claims (12)
1. 16M byte data memory addressing space extending method based on the MCS-51 framework, based on 8051 systems, it is characterized in that: the method that adopts time-sharing multiplex, the data storer is carried out the segmentation Aided Design, the data space of addressable 16M byte is divided into 256 pages or leaves, page address is determined by the high eight-bit data address, have 256 page addresss, the data addressing space that the 64K byte is arranged in each page, by eight and the interior address of decision page or leaf, low eight bit data address in the data address, address bus do not increase with the constant situation of whole instruction system under, make portion's data-carrier store addressing space extend to the 16M word from the 64K byte;
Its concrete steps are:
A. set page address special function register DPTR_PAGER, determine the high eight-bit data address;
B. setting data pointer register DATA_POINTER determines low 16 bit data addresses;
C. condition that produces according to page address and situation is different, following two kinds of situations is considered in the generation of data page address in the space extended operation of data memory addressing, and set coherent signal:
(a) page address that directly provides of user;
(b) page address that upgrades automatically;
D. condition that produces according to data pointer and situation is different, following three kinds of situations is considered in the generation of data pointer in the space extended operation of data memory addressing, and set coherent signal:
(a) data pointer that directly provides of user;
(b) data pointer is from increasing one (INC DPTR) instruction;
(c) data pointer is from subtracting one (DEC DPTR) instruction;
E. external data memory address XRAMA content of registers determines.
2. the 16M byte data memory addressing space extending method based on the MCS-51 framework according to claim 1 is characterized in that the method for described setting page address special function register DPTR_PAGER is:
The address of determining page address special function register DPTR_PAGER is 95H, and size is 8, the interior content decision of register thus of the high eight-bit address of data-carrier store 16M byte addressing space;
After the system reset, the value of DPTR_PAGER is #00H; The value of DPTR_PAGER can also be upgraded automatically by system except can being defined voluntarily by the user.
3. the 16M byte data memory addressing space extending method based on the MCS-51 framework according to claim 1 is characterized in that the method for described setting data pointer special function register DATA_POINTER is:
Data pointer special function register DATA_POINTER has 16, the interior content decision of register thus of low 16 bit address of data-carrier store 16M byte addressing space, and DATA POINTER is made up of DPL register and DPH register; The DPL register is being deposited the least-significant byte data of DATA_POINTER; The DPH register is being deposited the most-significant byte data of DATA_POINTER;
After the system reset, the value of DATA_POINTER is #0000H; The value of DATA_POINTER can also be upgraded automatically by system except can being defined voluntarily by the user.
4. the 16M byte data memory addressing space extending method based on the MCS-51 framework according to claim 1 is characterized in that described two kinds of situations that produce according to page address divide into the concrete steps that phasing closes signal and be:
A. relevant with the User Defined page address register and signal:
REG_RESULT: the page address content eight bit register that the user defines voluntarily;
DPTR_PAGER_WRITE: to page address special function register DPTR_PAGER carry out write operation with imitating signal;
When the DPTR_PAGER_WRITE signal was high level, the value of REG_RESULT write in the page address special function register DPTR_PAGER;
B. produce when striding page when page address, must be because of INC_DPTR instruction or the DEC_DPTR instruction causes the value of data pointer register DPTR_PAGER to become #0000H by #FFFFH or #0000H becomes #FFFFH, thereby a page phenomenon appears striding, at this moment data pointer register DPTR_PAGE content will increase " 1 " automatically or subtract " 1 ", the 16M external data memory insert when realizing striding access to web page or subtract page or leaf.
5. the 16M byte data memory addressing space extending method based on the MCS-51 framework according to claim 1 is characterized in that described three kinds of situations that produce according to data pointer divide into the concrete steps that phasing closes signal and be:
A.PC_CON[12]: MOV DPTR, the decoded signal of #16addr instruction;
DP_EN: data pointer enable signal;
In first clock period of second machine cycle of instructing, if PC_CON[12] be high level, then DP_EN becomes the high level useful signal; In second clock period of second machine cycle of instructing, if the DP_EN signal is effective, then 16 bit data pointer values are admitted among the data pointer register DATA_POINTER;
B.PC_CON[14]: the decoded signal of INC DPTR instruction;
In the 4th clock period of first machine cycle of instructing, if PC_CON[14] be the high level useful signal, then DP_EN becomes the high level useful signal; In first clock period of second machine cycle of instruction,, then add 16 bit data pointers after upgrading if the DP_EN signal is effective
Value is admitted among the data pointer register DATA_POINTER;
C.PC_CON[17]: the decoded signal of DEC_DPTR instruction;
In the 4th clock period of first machine cycle of instructing, if PC_CON[17] be the high level useful signal, then DP_EN becomes the high level useful signal; In first clock period of second machine cycle of instruction,, then subtract 16 bit data pointer values after upgrading and be admitted among the data pointer register DATA_POINTER if the DP_EN signal is effective.
6. the 16M byte data memory addressing space extending method based on the MCS-51 framework according to claim 1, the method that it is characterized in that described setting external data memory address XRAMA content of registers is: totally 24 in external data memory address XRAMA register, storing 24 specific address of data-carrier store; XRAMA is made up of data-carrier store page address register DPTR_PAGER and XRAMA_TP register; Data-carrier store page address register DPTR_PAGER is storing the most-significant byte address; The XRAMA_TP register-stored low 16 bit address;
High eight-bit in the XRAMA register of external data memory address and middle eight are sent by the timesharing of PORT2 mouth; Low eight and 8 bit data signals in the XRAMA register of external data memory address are by PORT0 mouth timesharing transmission, so total address bus still is 16.
7. the 16M byte data memory addressing space extending method based on the MCS-51 framework according to claim 3 is characterized in that the method for described setting special function register DPL is:
The address of determining special function register DPL is 82H, and size is 8, the interior content decision of register thus of low eight bit address of data-carrier store 16M byte addressing space;
After the system reset, the value of DPL is #00H; The value of DPL can also be upgraded automatically by system except can being defined voluntarily by the user.
8. the 16M byte data memory addressing space extending method based on the MCS-51 framework according to claim 3 is characterized in that the method for described setting special function register DPH is:
The address of determining special function register DPH is 83H, and size is 8, the interior content decision of register thus of centre eight bit address of data-carrier store 16M byte addressing space;
After the system reset, the value of DPH is #00H; The value of DPH can also be upgraded automatically by system except can being defined voluntarily by the user.
9. the 16M byte data memory addressing space extending method based on the MCS-51 framework according to claim 4 is characterized in that the concrete steps of described definite REG_RESULT content of registers are:
The value of 8 REG_RESULT registers comes from 8 program storage input data register PROGDI, and the content of PROGDI is made up of 8 bit data of external program memory data line output, is the content of the data-carrier store page address of user oneself definition; PROGDI links to each other with PORT0I, and PORT0I is 8 bit data input ports of microcontroller, and PORT0I can be connected on the external program memory DOL Data Output Line.
10. the 16M byte data memory addressing space extending method based on the MCS-51 framework according to claim 4 is characterized in that the concrete steps of described definite DPTR_PAGER_WRITE signal are:
1 DPTR_PAGER_WRITE signal is write enable signal SFR_WRITE_EN[25 by 1 special function register] decision; When the value of 8 destination address register DESTIN_ADDR is #15H, SFR_WRITE_EN[25] put one, when the value of DESTIN_ADDR is other any values, SFR_WRITE_EN[27] by zero setting; The value of DESTIN_ADDR is by 8 program storage input data register PROGDI decision, and PROGDI is connected on the PORT0I, and PORT0I is 8 bit data input ports of microcontroller, and PORT0I can be connected on the external program memory DOL Data Output Line.
11. the 16M byte data memory addressing space extending method based on the MCS-51 framework according to claim 5 is characterized in that the concrete steps of described definite DP_EN signal are:
DP_EN has three sources; In the 4th clock period of first machine cycle of instruction, if decoded signal PC_CON[14] high level is effective, and then DP_EN puts one; In the 4th clock period of first machine cycle of instruction, if decoded signal PC_CON[17] high level is effective, and then DP_EN puts one; In first clock period of second machine cycle of instruction, if decoded signal PC_CON[12] high level is effective, and then DP_EN puts one; Other any situation, DP_EN is by zero setting.
12. the 16M byte data memory addressing space extending method based on the MCS-51 framework according to claim 6 is characterized in that the concrete steps of described definite XRAMA_TP content of registers are:
PC_CON[5] signal is the decoded signal of MOVX@Ri class instruction, its significant level is a high level; Work as PC_CON[5] for for the moment, be that the instruction of MOVX@Ri class is just processed, at this moment, the value of XRAMA_TP is by the decision of the value in value on the PORT2 mouth and the SOURCE_DI register, and the content that the SOURCE_DI register is deposited is determined and goes up the value in certain unit on the data-carrier store; PORT2 deposits the high eight-bit of XRAMA_TP; The SOURCE_DI register is deposited low eight of XRAMA_TP;
As PC_CON[5] when being zero, i.e. instruction beyond the MOVX@Ri class instruction is just processed, and this moment, the value of XRAMA_TP was exactly the value of data pointer register DATA_POINTER.
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| CN102110462B (en) * | 2009-12-25 | 2015-09-30 | 旺宏电子股份有限公司 | Addressing one stores the method and apparatus of integrated circuit |
| CN102541745B (en) * | 2010-12-31 | 2015-10-21 | 上海海尔集成电路有限公司 | The addressing method of micro controller data storer and microcontroller |
| CN104809079B (en) * | 2015-04-14 | 2018-01-16 | 昆腾微电子股份有限公司 | The access method and device of paging registers |
| CN112071219B (en) * | 2020-09-18 | 2022-08-26 | 深圳市奥拓电子股份有限公司 | Adapter plate, LED display box body and LED display screen |
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