CN100358238C - Data correcting system and its method - Google Patents
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- CN100358238C CN100358238C CNB021415560A CN02141556A CN100358238C CN 100358238 C CN100358238 C CN 100358238C CN B021415560 A CNB021415560 A CN B021415560A CN 02141556 A CN02141556 A CN 02141556A CN 100358238 C CN100358238 C CN 100358238C
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Abstract
The present invention relates to a data replying system and a method thereof, which comprises an over sampling circuit, a phase detecting circuit, a data selecting circuit, a data overlapping/skipping detecting circuit and a data correcting circuit, wherein the over sampling circuit uses an n-time frequency for the over sampling of an input signal, the phase detecting circuit receives an over sampling signal sampled by the over sampling circuit to be matched with the final over sampling signal of the last time to carry out phase detection, the data selecting circuit receives the phase signal detected by the phase detecting circuit, divides the over sampling signal into n sets and selects one set of m bit data as output, the data overlapping /skipping detecting circuit determines whether a data overlapping /skipping condition occurs according to the relationship of the phase signal and the phase signal of the last time, and when the data overlapping/skipping condition occurs, the data correcting circuit corrects the data.
Description
Technical field
The invention relates to a kind of data answering system and method thereof, refer to a kind of system and method that data is replied in sequence transmission especially.
Background technology
In the high speed sequence transmission, in the problem that can produce clock pulse crooked (clock skew) to sequence data (serial data) when taking a sample, its main cause is the recovery clock pulse (recovered clock) and sampled sequence data out of phase with the phase place (phase) that decides sample time, a kind of direct solution was promptly carried out sampling (Over Sampling) to sampled sequence data, avoided issuable clock pulse crooked by improving sampling frequency.At United States Patent (USP) the 5th, 905, No. 769 case promptly proposes a kind of based on crossing the crooked problem of clock pulse that is produced when sampling is taken a sample to sequence data with solution, it is to use the phase place signal of a last data window, come the data of this sub-sampling data window is revised, when yet the phase place signal of a data window comes the data of this sub-sampling data window revised in this kind utilization, have the problem that in time to revise, when especially the phase change that causes when clock pulse is crooked only appears at this sub-sampling data window, phase place signal according to a last data window comes the data bits of this sub-sampling data window is revised, not only can't in time revise, the result who also leads to errors easily simultaneously is so knownly give improved necessity in order to solve the crooked technology reality of clock pulse.
Summary of the invention
Main purpose of the present invention is to provide a kind of data answering system and method thereof, can solve the crooked problem of clock pulse immediately.
Another object of the present invention is in the sequence transmission, can revise the crooked problem of clock pulse immediately.
For achieving the above object, data answering system of the present invention mainly comprises:
One crosses sample circuit, and it carried out sampling with the n overtones band to an input signal;
One detecting phase circuit, it receives this and crosses the mistake sample signal that sample circuit is taken a sample, and cooperation finishing touch last time is crossed sample signal to carry out detecting phase; And
One data selecting circuit receives the measured phase place signal of this detecting phase circuit, will be somebody's turn to do sample signal and be divided into n group and choose one group of m bit data and export.
Described system also comprises:
One data is overlapping/skip over circuit for detecting, receive the phase place signal that this detecting phase circuit is exported, and cooperate the phase place signal of last time, whether decision has the overlapping or situation that data skips over of data and exports a relevant state signal; And
One data is positive circuit more, the m bit data of being exported by the data selecting circuit and last time finishing touch cross in the sample signal, according to data overlapping/the state signal that skips over circuit for detecting output carries out the data corrigendum to choose m+1 or m or m-1 bit data, exports the correct data of a m bit.
In the described system, this detecting phase circuit comprises:
One transition detector is in order to the mistake sample signal of detecting this sampling and a plurality of transition that last time, finishing touch was crossed sample signal; And
One digit is divided into the n group with these transition, selects to have one group of maximum transition, and exports corresponding phase place signal.
In the described system, this data is overlapping/skip over circuit for detecting output overlapping, skip over and the normal condition signal with representative respectively have data overlapping, have data to skip over and non-avaible overlapping with the situation that skips over.
In the described system, this data more positive circuit includes first in first out buffering unit, and inputs to this first in first out buffering unit according to this state signal to choose m+1 or m or m-1 bit data, and this first in first out buffering unit exports the correct data of this m bit.
In the described system, when this state signal was an overlap condition signal, this first in first out buffering unit accepted this m-1 bit data.
In the described system, when this state signal is one when skipping over the state signal, this first in first out buffering unit accepts this m+1 bit data.
In the described system, when this state signal was a normal condition signal, this first in first out buffering unit accepted this m bit data.
Data answering method of the present invention comprises following steps:
(A) cross sampling procedure, a document signal that is received was carried out sampling, and produce a succession of sample signal of crossing with the n overtones band;
(B) extraction step should a succession ofly be crossed sample signal, took out a nk+1 bit and crossed sample signal;
(C) transition detecting step is crossed nk transition of sample signal in order to detect this nk+1 bit, these transition signals is divided into the n group and exports this n group transition signal;
(D) select step, selection has a group of maximum transition, exports a phase place signal; And
(E) data is chosen step, should a succession ofly cross sample signal and be divided into n group output data, and according to this phase place signal, choose and export wherein one group of m bit output data.
Described method also comprises:
(F) overlapping/skip over the detecting step, receive this phase place signal, cooperate the phase place signal of last time, export a state signal; And
(G) data corrigendum step by this group m bit output data with should go up a succession of finishing touch of crossing sample signal of pen and cross in the sample signal, is carried out data and is corrected to choose m+1 or m or m-1 bit data according to this state signal, to export the correct data of a m bit.
Description of drawings
For making further understanding structure of the present invention, feature and purpose thereof, elaborate as the back with accompanying drawing and preferred embodiment:
Fig. 1 is a calcspar of the present invention.
Fig. 2 is the timing figure that crosses sample circuit of the present invention.
Fig. 3 is the circuit diagram of detecting phase circuit of the present invention.
Fig. 4 is the schematic diagram of best data choice point of the present invention.
Fig. 5 is the circuit diagram of money of the present invention section selecting circuit.
Fig. 6 is the overlapping schematic diagram of institute's generation data of the present invention.
The schematic diagram that Fig. 7 skips over for institute of the present invention generation data.
Fig. 8 for data of the present invention overlapping/skip over the pseudo code of circuit for detecting.
Fig. 9 is the more pseudo code of positive circuit of data of the present invention.
Figure 10 is a flow chart of data answering method of the present invention.
Embodiment
One preferred embodiment of relevant data answering system of the present invention, please refer to calcspar shown in Figure 1, its comprise one cross sample circuit (Over Sampler) 10, one detecting phase circuit (Phase DetectCircuit) 20, one data selecting circuit (Data Picking Circuit) 30, one data overlapping/skip over more positive circuit (DataCorrection Circuit) 50 of circuit for detecting (Dara Overlap/Skip Detect Circuit) 40 and one data.Wherein, this crosses the sampling that sample circuit 10 is done input signal multiple frequence, and be a unit with a plurality of input signals, exporting it and cross sample signal, in present embodiment, is input signal done frequency tripling sampling and to be a unit with 10 bits input news, be the example explanation, and after sample signal is accumulated to 30 excessively,, once export detecting phase circuit 20 and data selecting circuit 30 simultaneously to so obtain 30 mistake sample signal.
After sample signal is crossed in 30 of detecting phase circuit 20 receptions, cooperate inner finishing touch last time that is kept to cross sample signal to carry out detecting phase, and the phase place that obtains delivered to data selecting circuit 30 and data overlapping/skip over circuit for detecting 40, data selecting circuit 30 is according to the measured phase place of detecting phase circuit 20, cross sample signal with these 30 and be divided into three groups and choose one group of 10 bit data the most suitable with the data of outputing to more in the positive circuit 50, data is overlapping/skip over the phase place that circuit for detecting 40 receiving phase circuit for detecting 20 are exported, the phase place that cooperates last time, whether decision has the overlapping or situation that data skips over of data, and the result after will judging delivers to more positive circuit 50 of data, data more positive circuit 50 foundations has the overlapping or situation that data skips over of non-avaible, 10 bit datas that decision is exported by data selecting circuit 30 and last time finishing touch mistake sample signal in the data of totally 11 bits, choose 11 or 10 or 9 bit datas and carry out the data corrigendum, to export the correct data of one 10 bits.
In the shown sequential chart of Fig. 2, crossing sample circuit 10 is regularly input signal to be taken a sample with the sampling frequency of frequency tripling, to obtain 30 mistake sample signal S[29:0], wherein S29 is sampled at first and S0 is sampled at last, S0 ' is the sampled mistake sample signal of finishing touch that goes up pen one 10 bit input signals, and S29 " be the sampled mistake sample signal of the first stroke of one 10 bit input signals of starting writing; and cross sample circuit 10 is after crossing sample signal and being accumulated to 30, once simultaneously it is exported to detecting phase circuit 20 and data selecting circuit 30.
Fig. 3 shows the circuit structure of aforementioned detecting phase circuit 20, mainly form by a transition detector (Transition Dectector) 21 and one 22 of digits (Tally), change detector 21 and comprise 30 XOR locks, wait the XOR lock thus, cross sample signal S[29:0 for 30 of input] and last time last neighbor in twos that crosses sample signal S0 ' make the mutual exclusion exclusive disjunction mutually to detect transition (Transition), and S[29:0] and S0 ' totally 31 documents can measure 30 transition, be numbered PA[9:0 respectively], PB[9:0], and PC[9:0], wherein, Pan=S
3n+2, 1. S3n, PBn=S
3n+1, 1. S
3n+2, PCn=S
3n, 1. S3
N+1, central n=0-9 promptly when PCn is 1, represents S
3nAnd S
3n+1Between transition are arranged, when PBn is " 1 ", the expression S
3n+1And S
3n+2(or S
3n-1) between transition are arranged, when PAn is " 1 ", the expression S
3n+2(or S
3n-1) and S
3nBetween transition are arranged.
The function of digit 22 has one group of maximum transition for selecting, and exports corresponding phase place signal.One embodiment is for having a maximum-value selector 225 and three groups of adders 221,222 and 223, it is divided into PA[9:0 with 30 transition], PB[9:0] and PC[9:0] three groups of indivedual additions, be that 221 couples of PA9-PA0 of adder carry out add operation and obtain the SumA signal, 222 couples of PB9-PB0 of adder carry out add operation and obtain the SumB signal, 223 couples of PC9-PC0 of adder carry out add operation and obtain the SumC signal, become 1 and became for 0 opportunity of taking place by 1 in order to the differentiation data by 0, SumA signal value is S
3n+2(or S
3n-1) and S
3nBetween transition number of times summation is arranged, SumB signal value is S
3n+1And S
3n+2(or S
3n-1) between transition number of times summation is arranged, SumC signal value is S
3nAnd S
3n+1Between transition number of times summation is arranged, maximum-value selector 225 is selected a phase place signal relevant with maximum from the output valve of aforesaid three adders 221,222 and 223, for example, when SumA signal value is maximum, the phase place signal of output is phase place A (Phase A), and when SumB signal value was maximum, the phase place signal of output was phase place B (Phase B), when SumC signal value was maximum, the phase place signal of output was phase place C (Phase C).
Compare SumA, SumB and SumC signal value, if SumA signal value maximum when promptly this phase place signal is phase place A (Phase A), represents that then data is at S
3n+2(or S
3n-1) and S
3nBetween the transition number of times maximum, show that as A place among Fig. 4 in order to select a stable and correct data, choice point should be far away more good more from transition, therefore should select S
3n+2Be used as correct data, promptly the B place is best data choice point among Fig. 4; Similarly, if SumB signal value maximum when promptly this phase place signal is phase place B (Phase B), represents that then data is at S
3n+1And S
3n+2(or S
3n-1) between the transition number of times maximum, therefore should select S
3nBe used as correct data; If SumC signal value maximum when promptly this phase place signal is phase place C (Phase C), represents that then data is being S
3nAnd S
3n+1Between the transition number of times maximum, therefore should select S
3n+2Be used as correct data.
One embodiment of this maximum-value selector 225 is for comprising three comparators, these comparators compare the magnitude relationship of appointing both among SumA, SumB and the SumC three respectively, promptly obtain (SumA, SumB), (SumB, SumC) and (SumC, SumA) magnitude relationship is promptly learnt what person's maximum among SumA, SumB and the SumC.
Fig. 5 shows the structure of this data selecting circuit 30, and it is crossed sample signal with these 30 and is divided into S
3n+2={ S29, S26 ..., S2}, S
3n+1={ S28, S25 ..., S1} and S
3n={ S27, S24 ..., three groups of signals such as S0}, the phase place signal of being exported according to detecting phase circuit 20, these three groups of signals are chosen one group of signal the most suitable as data dat[9:0] output, if when the phase place signal exported of detecting phase circuit 20 is Phase A, data dat[9:0] be S
3n+1={ S28, S25 ..., S1}, also dat9=S28, dat8=S25 ... dat0=S1; When if the phase place signal that detecting phase circuit 20 is exported is Phase B, data dat[9:0] then be S
3n={ S27, S24 ..., S0}; When if the phase place signal that detecting phase circuit 20 is exported is Phase C, data dat[9:0] then be S
3n+2={ S29, S26 ..., S2}.
Though the sample circuit 10 of crossing of the present invention is taken a sample input signal with the frequency sample of frequency tripling forever regularly, yet have via the input signal of transmission channel or cable and to delay or leading phenomenon, this kind phenomenon can produce the overlapping or problem that data skips over of data, overlapping or the problem that data skips over of data for convenience of description, suppose that input signal is is a unit with 3 bits, and 3 bit datas are defined as a data window (Data Window, DW), Fig. 6 is used for the overlapping problem that produces of detail file, in the 1st data window, the phase place signal is Phase A, so S
3n+2(or S
3n-1) and S
3nBetween the transition number of times maximum, show as A place among Fig. 6, because of present embodiment is to fix the sampling of 3 frequencys multiplication, so best data choice point should be the average distance sampling point farthest from the A place, that is at the B place of Fig. 6;
In the 2nd data window, the phase place signal is Phase B, so S
3n+1And S
3n+2(or S
3n-1) between the transition number of times maximum, show as C place among Fig. 6, and the D place that best data choice point is Fig. 6; In the 3rd data window, the phase place signal is Phase C, so S
3nAnd S
3n+1Between the transition number of times maximum, show as E place among Fig. 6, among its best data choice point such as Fig. 6 shown in the F, the mistake sample signal of T1, T2 in Fig. 6, according to aforesaid detecting phase circuit 20 and data selecting circuit 30, it all can be exported as correct data, yet the mistake sample signal of this T1, T2 is with respect to data DATA-OL, so data DATA-OL can be output twice, and the overlapping problem of generation data.
Similarly, come detail file to skip over the problem that is produced at Fig. 7, in the 1st data window, the phase place signal is Phase A, so S
3n+2(or S
3n-1) and S
3nBetween the transition number of times maximum, show as A place among Fig. 7, and best data choice point is the average distance sampling point farthest from the A place, that is at the B place of Fig. 7;
In the 2nd data window, the phase place signal is Phase C, so S
3nAnd S
3n+1Between the transition number of times maximum, show as the G place of Fig. 7, and best data choice point is the H place at Fig. 7; In the 3rd data window, the phase place signal is Phase B, so S
3n+1And S
3n+2(or S
3n-1) between the transition number of times maximum, show as I place among Fig. 7, the J place that its best data choice point is Fig. 7, the mistake sample signal of data DATA-SK in Fig. 7 can be sampled at T3, T4, but according to aforesaid detecting phase circuit 20 and data selecting circuit 30, it can not be output, so data DATA-SK can be left in the basket and the problem that the generation data skips over.
For solve aforesaid data overlapping/problem that skips over, data is overlapping/skip over the phase place signal that circuit for detecting 40 receiving phase circuit for detecting 20 are exported, cooperate a phase place signal in the data window, judge that whether data is arranged when data selecting circuit 30 is chosen data is overlapping, data skips over, or the two all the situation that does not take place, and the state signal (Status) after will judging exports more positive circuit 50 of data to, if the phase place signal in this data window is phase place B (Phase B), and the phase place signal in the last data window is phase place C (Phase C), it then is the situation of Fig. 6, that is the overlapping problem of data arranged, state signal this moment (Status) is Overlap, if the phase place signal in this data window is phase place C (Phase C) and phase place signal in the last data window is phase place B (Phase B), it then is the situation of Fig. 7, that is the problem that has data to skip over, state this moment (Status) is Skip, if not be above-mentioned two kinds of situations, state (Status) then is Normal.Data is overlapping/skip over that circuit for detecting 40 can (Hardware Description Language HDL) realizes via the hardware description language of for example Verilog or VHDL by the pseudo code (Pseudo Code) of Fig. 8.
Data more positive circuit 50 according to data overlapping/skip over the defeated state (Status) of circuit for detecting 40,10 bit datas of being exported by data selecting circuit 30 with decision and last time finishing touch cross among the sample signal S0 ', choose 11 or 10 or 9 bits and carry out the data corrigendum, this data correct data of the permanent output of positive circuit 50 10 bits more at last, wherein, when state is Overlap, as shown in Figure 6, data more positive circuit 50 keeps the data that solves in the last data window, and because dat9 has occurred at last document, so the data that solves in the inferior data window is only used 9 data dat[8:0], according to sequencing import a first in first out unit (First ln First Out, FIFO) in; When state is Skip, as shown in Figure 7, data more positive circuit 50 keeps the data that solves in the last data window, and the data that solves in the current data window is used 10 data dat[9:0], add the mistake sample signal S0 ' of finishing touch in the last data window, and with two groups of data totally 11 documents import in the first in first out unit according to sequencing; When state is Normal, then with data more positive circuit 50 keep the data that solves in the last data window, and the data that this time solves in data window is used 10 data dat[9:0], import in the first in first out device according to sequencing; This first in first out device is exported the correct data data[9:0 of 10 bits in regular turn at last].
This data more positive circuit 50 can be realized via the hardware description language of for example Verilog or VHDL by the pseudo code (Pseudo Code) of Fig. 9.
Figure 10 is the flow chart that further shows data answering method of the present invention, at first, imports a list entries signal in step S301; In step S302 (cross sampling procedure), regularly the list entries signal is taken a sample with the sampling frequency of frequency tripling) to obtain 30 mistake sample signal S[29:0; In step S303 (extraction step), should a succession ofly cross sample signal, take out a 30+1 bit and cross sample signal, it was sample signal S[29:0 that this 30+1 bit is crossed sample signal] and last time last crossed sample signal S0 '.
In step S304 (transition detecting step), cross 30 transition of sample signal in order to detect this 30+1 bit, cross sample signal S[29:0] and last time last neighbor in twos who crosses sample signal S0 ' make the mutual exclusion exclusive disjunction mutually to detect transition, and export one 30 transition signals and these transition signals be divided into 3 groups of PA[9:0), PB[9:0) and PC[9:0) transition signal, wherein, PAn=S
3n+2, 1. S3n, PBn=S
3n+1, 1. S
3n+2, PCn=S
3n, 1. S3
N+1, central n=0-9 promptly when PCn is " 1 ", represents S
3nAnd S
3n+1Between transition are arranged, when PBn is " 1 ", the expression S
3n+1And S
3n+2(or S
3n-1) between transition are arranged, when PAn is " 1 ", the expression S
3n+2(or S
3n-1) and S
3nBetween transition are arranged.
In step S305 (selection step), by these 3 groups of transition signal PA[9:0], PB[9:0) and PC[9:0] in, selection has a group of maximum transition, the phase place signal that output one is correlated with, that is PA9-PA0 carried out add operation and obtain the SumA signal, PB9-PB0 is carried out add operation and obtains the SumB signal, PC9-PC0 is carried out add operation and obtains the SumC signal, SumA as a result from aforesaid three add operations, select a maximum and the phase place signal relevant among SumB and the SumC with this maximum, for example, when SumA signal value is maximum, the phase place signal of output is phase place A (Phase A), and when SumB signal value was maximum, the phase place signal of output was phase place B (Phase B), when SumC signal value was maximum, the phase place signal of output was phase place C (Phase C).
In step S306 (data is chosen step), cross sample signal with these 30 and be divided into 3 groups of output data S
3n+2={ S29, S26 ..., S2}, S
3n+2={ S28, S25 ..., S1} and S
3n={ S27, S24 ..., three groups of signals such as S0}, and be dependent on this phase place signal of exporting among the step S305, these three groups of signals are chosen one group of signal the most suitable as 10 bit data dat[9:0] output, when being Phase A as if this phase place signal of exporting among the step S305, data dat[9:0] be S
3n={ S28, S25 ..., S1}, also dat9=S28, dat8=S25 ... dat0=S1; When if the phase place signal that detecting phase circuit 20 is exported is Phase B, data dat[9:0] then be S
3n={ S27, S24 ..., S0}; When if the phase place signal that detecting phase circuit 20 is exported is Phase C, data dat[9:0] then be S
3n+2=S29, S26 ..., S2}.
In step S307 (overlapping/as to skip over and detect step), this phase place signal of exporting among the receiving step S305, cooperate a phase place signal in the data window, if the phase place signal in this data window is phase place B (Phase B), and the phase place signal in the last data window is phase place C (Phase C), the overlapping problem of data is promptly arranged, state signal this moment (Status) is Overlap, if the phase place signal in this data window is phase place C (Phase C) and phase place signal in the last data window is phase place B (PhaseB), the problem that promptly has data to skip over, state this moment (Status) is Skip, if not be above-mentioned two kinds of situations, state signal (Status) then is Normal.
In step S308 (data corrigendum step), organize 10 bits output data and should go up a succession of finishing touch of crossing sample signal of pen and cross in the sample signal by this, according to this state signal of exporting among the step S307 with choose 10+1 10 or the 10-1 bit data carry out data corrigendum, to export the correct data data[9:0 of one 10 bits].
By above explanation as can be known, the present invention can solve the crooked problem of clock pulse.
It should be noted that the foregoing description is for convenience of explanation, the non-the foregoing description that only limits to of the interest field that the present invention advocated, and all technical though relevant with the present invention all belong to category of the present invention.
Claims (9)
1, a kind of data answering system comprises:
One crosses sample circuit, with the n overtones band one input signal is taken a sample, and produces a plurality of sample signal;
One detecting phase circuit receives this a plurality of sample signal, detects the transition of these a plurality of sample signal, and exports a phase place signal; And
One data selecting circuit receives these a plurality of sample signal and this phase place signal, should a plurality of sample signal be divided into the n group and chooses one group of m bit data and export;
One data is overlapping/skip over circuit for detecting, receive this phase place signal, and cooperate the phase place signal of last time, whether decision has the overlapping or situation that data skips over of data and exports a state signal; And
One data is positive circuit more, accepts this m bit output data, according to this state signal this m bit output is corrected, and exports the correct data of a m bit.
2, the system as claimed in claim 1 is characterized in that, this detecting phase circuit comprises:
One transition detector in order to detect the transition of this sample signal, produces a plurality of transition signals; And
One digit is divided into the n group with this transition signal, selects to have one group of maximum transition, and exports this phase place signal.
3, the system as claimed in claim 1 is characterized in that, that this state signal can show is overlapping, skip over and normal condition with representative respectively have data overlapping, have data to skip over and non-avaible overlapping with the situation that skips over.
4, the system as claimed in claim 1, it is characterized in that, this data more positive circuit comprises first in first out buffering unit, and input to this first in first out buffering unit to choose m+1 or m or m-1 bit data according to this state signal, and this first in first out buffering unit exports the correct data of this m bit.
5, system as claimed in claim 4 is characterized in that, when this state signal was an overlap condition, this first in first out buffering unit accepted this m-1 bit data.
6, system as claimed in claim 4 is characterized in that, when this state signal is one when skipping over state, this first in first out buffering unit accepts this m+1 bit data.
7, system as claimed in claim 4 is characterized in that, when this state signal was a normal condition, this first in first out buffering unit accepted this m bit data.
8, a kind of data answering method, the method includes the steps of:
With the n overtones band document signal that is received is carried out sampling, and produced a plurality of sample signal;
Nk transition signal exported in the transition of nk+1 sample signal of detecting, and this transition signal is divided into n group and output n group transition signal;
In n group transition signal, selection has a group of maximum transition, exports a phase place signal; And
This sample signal is divided into n group output data, and, chooses and export wherein one group of m bit output data according to this phase place signal;
One data is overlapping/skip over circuit for detecting, receive this phase place signal, and cooperate the phase place signal of last time, whether decision has the overlapping or situation that data skips over of data and exports a state signal; And
One data is positive circuit more, accepts this m bit output data, according to this state signal this m bit output is corrected, and exports the correct data of a m bit.
9, method as claimed in claim 8 is characterized in that, also comprises:
According to this phase place signal and last time the phase place signal, export a state signal;
Temporary this m bit output data is corrected this m bit data according to this state signal, and is exported the correct data of a m bit.
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| CNB021415560A CN100358238C (en) | 2002-09-02 | 2002-09-02 | Data correcting system and its method |
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|---|---|---|---|
| CNB021415560A CN100358238C (en) | 2002-09-02 | 2002-09-02 | Data correcting system and its method |
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| CN100358238C true CN100358238C (en) | 2007-12-26 |
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| CN1232319A (en) * | 1998-03-12 | 1999-10-20 | 日本电气株式会社 | Over-sampling type clock recovery circuit with power consumption reduced |
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| US6222419B1 (en) * | 1998-03-12 | 2001-04-24 | Nec Corporation | Over-sampling type clock recovery circuit using majority determination |
| JPH11341087A (en) * | 1998-05-26 | 1999-12-10 | Fujitsu Ltd | Clock reproducing circuit for four value fsk system |
| US20020030522A1 (en) * | 2000-05-11 | 2002-03-14 | Satoshi Nakamura | Oversampling clock recovery circuit |
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| CN1481072A (en) | 2004-03-10 |
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