CN103604968A - System for eliminating burrs erroneously generated by peak detection - Google Patents
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Abstract
The invention provides a system for eliminating burrs erroneously generated by peak detection. According to the system, a maximum value and minimum value sorting function is increased to accurately store a sampling sequence of a maximum value and a minimum value, so that signals are sorted respectively according to two sequences in an ascending state and a descending state and the burrs are not erroneously generated at the edge.
Description
Technical field
The present invention relates to digital storage oscilloscope data sampling field, especially eliminate peak value and detect the system that by mistake produces burr.
Background technology
Data sampling, it is digital oscilloscope major part that data processing and data show, data sampling is exactly that digital to analog converter carries out digital quantization sampling to simulating signal, and sampled data is postponed being flushed in storer, waits for data processing.Sampling is as the basis of the data processings such as digital oscilloscope wave form analysis computing, and sampling interval is less is that sampling rate is higher, and display waveform just more approaches original signal; It is exactly digital to analog converter in high sampling rate down-sampled data that peak value detects, and maximal value detected, in minimum value data input reservoir when different in one group of sampled data of the corresponding extraction yield N of base gear.
But existing peak value detection mode does not keep former sampling time sequence to the maximal value gathering and minimum value when storing, but use acquiescence mode, with the order Dmin fixing, Dmax or Dmax, Dmin sorts, but two kinds of orders exist simultaneously in the rising of signal and decline state, if adopt acquiescence mode to sort, must there is a kind of order meeting mistake, on the waveform edge showing, there is burr, take square wave as example, as Figure 1-1, in figure, select Dmax, Dmin order, at waveform rising edge, point Dmin, Dmax selects this order sequential mistake, on waveform, there is burr, as shown in Figure 1-2, in figure, select Dmin, Dmax order, at waveform negative edge, some Dmax, Dmin selects this order sequential mistake, occurs burr on waveform.
Summary of the invention
Technical matters to be solved: the invention provides the system that peak value detection produces burr by mistake of eliminating for above problem, the present invention has increased the ranking function of maximal value and minimum value, store strictly according to the facts the sampling order of maximal value and minimum value, like this in the rising of signal and decline state respectively according to two kinds of order sequences, on edge, just can not increase burr by mistake.
Technical scheme: in order to overcome the above problems, to the invention provides and eliminate the system that peak value detection produces burr by mistake, comprise PLL, ADC, CLK1, CLK2, reduction of speed processor module, peak detection block, reservoir;
Described PLL is phaselocked loop, and the ADC required clock frequency of sampling is provided;
Described ADC provides the data-signal of analog-converted numeral;
Described CLK1 is ADC sampling clock, and CLK2 is the clock of data output after reduction of speed, and reduction of speed coefficient is 2
n, meet CLK2=CLK1/2
n;
Described reduction of speed processing module is to utilize string to turn and technology, and data bit is expanded, and the data-signal of ADC output is synchronous through CLK1, is input to reduction of speed processor module;
Described peak detection block comprises peak value parallel detection module, peak value serial detection module, output switch, N digit counter; Described peak value parallel detection module becomes the data of ADC into 2 after reduction of speed processor module
nindividual parallel data, relatively exports large value and little value between two by comparer at different levels, through n level, relatively obtains maximal value and minimum value;
Described peak value serial detection module comprises maximum value detector, minimum detector, maximal value and minimum value through the output of peak value parallel detection module are input to respectively in corresponding maximum value detector and minimum detector, contrast with maximal value and the minimum value of last time respectively, the maximal value that the maximal value of new input is greater than last time just remains the maximal value of newly input, otherwise the maximal value that keeps last time, the minimum value that the minimum value of new input is less than last time just remains the minimum value of newly input, otherwise keeps the minimum value of last time constant;
Described N digit counter is the number of times of counting input maximal value and minimum value, N digit counter is counted CLK2, often carry out a clock, counter adds 1, when N digit counter does not complete counting, output switch disconnects, when N digit counter completes counting, output switch is closed, and final maximal value and final minimum value are input in reservoir;
It is characterized in that: described peak value parallel detection module also comprises S1 comparer, data are also exported and are indicated position Pmax.i or Pmin.i when comparer at different levels is relatively exported large value and little value between two; And i=2
n-2, n is positive integer; Output sequence signal S1 when relatively selecting maximal value and minimum value through n level, wherein the 1st grade has 2
n-1individual comparer, the 2nd grade has 2
n-2individual large value comparer and 2
n-2little value comparer, the like in n level, have 1 large value comparer and 1 little value comparer; Described sequence signal S1 is that Smax and Smin relatively obtain through S1 comparer, described Smax and Smin be output maximal value and minimum value 2
nposition in individual data, this position is that Pmin.i is definite by signs at different levels position Pmax.i, method is as follows:
First according to afterbody, be the sign position Pmax.i of n level comparer, Pmin.i, determines that maximal value and minimum value are upper half or the bottom halfs of getting, and described upper half is 2
nthe first half of individual data, bottom half is 2
nthe latter half of individual data; And then be the sign position of n-1 level comparer according to penultimate stage, in halfth district, place, dwindle again the position that half scope is determined maximal value and minimum value; Recursion one-level forward in the same way again, at place, halfth district dwindles the position that half scope is determined maximal value and minimum value again, and recursion, finally determines that maximal value and minimum value are 2 so layer by layer
nparticular location in individual data;
At the 1st grade relatively time, when one be value greatly, another is little value, Pmax.i and Pmin.i are negate relations, that is: during Pmax.i=1, when Pmin.i=0 or Pmax.i=0, Pmin.i=1;
When Smax>Smin, sequence signal S1=1, data output sequence: Dmin, Dmax, is propradation, when Smax<Smin, sequence signal S1=0, data output sequence: Dmax, Dmin, for being decline state;
Described peak value serial detection module also comprises S2 comparer, and described peak detection block also comprises switch, sequence;
Described peak value serial detection module is exported a sequence signal S2 when selecting final maximal value and final minimum value, described sequence signal S2 is that in peak value serial detection module, maximal value update times FNmax and minimum value update times FNmin relatively obtain through S2 comparer, maximal value and minimum value through the output of peak value parallel detection module are input to respectively in corresponding maximum value detector and minimum detector, contrast with maximal value and the minimum value of last time respectively, if the maximal value of new input is greater than, the maximal value of last time just remains the maximal value of newly input and update times FNmax adds 1, otherwise keep maximal value and the update times FNmax of last time constant, if the minimum value of new input is less than, the minimum value of last time just remains the minimum value of newly input and update times FNmin adds 1, otherwise keep minimum value and the update times FNmin of last time constant,
Maximal value update times FNmax and minimum value update times FNmin input S2 comparer, if it is that maximal value update times is greater than minimum value update times that FNmax is greater than FNmin, sequence signal S2=1, data output sequence: Dmin, Dmax, it is propradation, if it is that maximal value update times is less than minimum value update times that FNmax is less than FNmin, sequence signal S2=0, data output sequence: Dmax, Dmin, for being decline state, if it is that maximal value update times equals minimum value update times that FNmax equals FNmin, differentiation sequentially again, can be included in rising or decline state,
When N=1, switch disconnects, and maximal value and the minimum value of the output of peak value parallel detection module, without peak value serial detection module, be directly inputted to after sequence in reservoir, and the sequencing of maximal value and minimum value output is determined in sequence according to sequence signal S1; When N>1, switch is closed, peak value parallel detection module output maximal value and minimum value are synchronous through CLK2, be input to peak value serial detection module, when N digit counter completes counting, the final maximal value of output and final minimum value are input in reservoir after sequence, and the sequencing of final maximal value and final minimum value output is determined in sequence according to sequence signal S2.
Beneficial effect: the present invention has increased the ranking function of maximal value and minimum value, stores the sampling order of maximal value and minimum value strictly according to the facts, like this in the rising of signal and decline state respectively according to two kinds of order sequences, on edge, just can not increase burr by mistake.
Accompanying drawing explanation
Waveform rising edge burr in the present invention of Fig. 1-1
Dotted line is correct tactic waveform, and solid line is the burr waveform that wrong sequence is arranged.
Waveform negative edge burr in Fig. 1-2 the present invention
Dotted line is correct tactic waveform, and solid line is the burr waveform that wrong sequence is arranged.
Waveform propradation in the present invention of Fig. 2-1.
Waveform decline state in the present invention of Fig. 2-2.
Waveform equivalent state in the present invention of Fig. 2-3.
Peak value in Fig. 3 the present invention detects entire block diagram.
Peak value parallel detection schematic diagram in Fig. 4 the present invention.
Peak value serial in Fig. 5 the present invention detects schematic diagram.
Embodiment
Below in conjunction with Figure of description, the invention will be further described.
Embodiment
If Fig. 2-1 is to as shown in Fig. 5, eliminate peak value and detect the system that by mistake produces burr, comprise PLL, ADC, CLK1, CLK2, reduction of speed processor module, peak detection block, reservoir;
Described PLL is phaselocked loop, and the ADC required clock frequency of sampling is provided;
Described ADC provides the data-signal of analog-converted numeral;
Described CLK1 is ADC sampling clock, and CLK2 is the clock of data output after reduction of speed, and reduction of speed coefficient is 2
n, meet CLK2=CLK1/2
n;
Described reduction of speed processing module is to utilize string to turn and technology, and data bit is expanded, and the data-signal of ADC output is synchronous through CLK1, is input to reduction of speed processor module;
Described peak detection block comprises peak value parallel detection module, peak value serial detection module, switch, sequence, output switch, N digit counter;
As shown in Figure 4, during n=3,2
n=8 o'clock, described peak value parallel detection module becomes the data of ADC 8 parallel datas after reduction of speed processor module, by comparer, compare between two, in the time of the large value of output and little value, also export and indicate position Pmax.i or Pmin.i, through 3 grades, relatively obtain maximal value and minimum value, the signal of output sequence simultaneously S1, described 3 grades of first order in relatively relatively comprise comparer 1 to 4, the second level relatively comprises large value comparer 5 to 6, little value comparer 7 to 8, the third level relatively comprises large value comparer 9 and little value comparer 10; Described sequence signal S1 is that Smax and Smin relatively obtain through S1 comparer, described Smax and Smin be the maximal value of output and minimum value in the position of 8 data, this position is that Pmin.i is definite by sign at different levels position Pmax.i:
First according to afterbody, be 3rd level comparer, be worth greatly the sign position Pmax.6 of comparer 9, the sign position Pmin.6 of little value comparer 10, determines that maximal value is the upper half (D getting
a, D
b, D
c, D
d) bottom half (D that large value comparer 5 is still got
e, D
f, D
g, D
h) being worth greatly comparer 6, minimum value is the upper half (D getting
a, D
b, D
c, D
d) be little value comparer 7, the bottom half (D still getting
e, D
f, D
g, D
h) be little value comparer 8;
And then according to the sign position of the 2nd grade of comparer, determine the position of maximal value and minimum value, if maximal value is to get big value comparer 5, minimum value is the little value comparer 7 of getting, according to the sign position Pmax.4 of large value comparer 5, the sign position Pmin.4 of little value comparer 7, in halfth district, place, dwindle again half scope, determine comparer 1 or comparer 2 that maximal value and minimum value are got; In like manner, if maximal value is to get big value comparer 6, minimum value is the little value comparer 8 of getting, according to the sign position Pmax.5 of large value comparer 6, the sign position Pmin.5 of little value comparer 8, in halfth district, place, dwindle again half scope, determine comparer 3 or comparer 4 that maximal value and minimum value are got;
Finally in the same way to previous stage recursion, according to the sign position Pmax.0 of the 1st grade of comparer, Pmin.0 or Pmax.1, Pmin.1, or Pmax.2, Pmin.2 or Pmax.3, Pmin.3 finally determines maximal value and the particular location of minimum value in 8 data.
At the 1st grade relatively time, when one be value greatly, another is little value, Pmax.i and Pmin.i are negate relations, that is: during Pmax.0=1, when Pmin.0=0 or Pmax.0=0, Pmin.0=1; During Pmax.1=1, when Pmin.1=0 or Pmax.1=0, Pmin.1=1; During Pmax.3=1, when Pmin.3=0 or Pmax.3=0, Pmin.3=1; During Pmax.4=1, when Pmin.4=0 or Pmax.4=0, Pmin.4=1;
When Smax>Smin, sequence signal S1=1, data output sequence: Dmin, Dmax, is propradation, when Smax<Smin, sequence signal S1=0, data output sequence: Dmax, Dmin, is decline state;
Described peak value serial detection module also comprises that S2 is compared with device, and described peak detection block also comprises switch, sequence;
Described peak value serial detection module is exported a sequence signal S2 when selecting final maximal value and final minimum value, described sequence signal S2 is that in peak value serial detection module, maximal value update times FNmax and minimum value update times FNmin relatively obtain through S2 comparer, maximal value and minimum value through the output of peak value parallel detection module are input to respectively in corresponding maximum value detector and minimum detector, contrast with maximal value and the minimum value of last time respectively, if the maximal value of new input is greater than, the maximal value of last time just remains the maximal value of newly input and update times FNmax adds 1, otherwise keep maximal value and the update times FNmax of last time constant, if the minimum value of new input is less than, the minimum value of last time just remains the minimum value of newly input and update times FNmin adds 1, otherwise keep minimum value and the update times FNmin of last time constant,
Maximal value update times FNmax and minimum value update times FNmin input S2 comparer, if it is that maximal value update times is greater than minimum value update times that FNmax is greater than FNmin, sequence signal S2=1, data output sequence: Dmin, Dmax, it is propradation, if it is that maximal value update times is less than minimum value update times that FNmax is less than FNmin, sequence signal S2=0, data output sequence: Dmax, Dmin, for being decline state, if it is that maximal value update times equals minimum value update times that FNmax equals FNmin, differentiation sequentially again, can be included in rising or decline state,
As shown in Fig. 2-1, when propradation, minimum value is sampling for the first time, maximal value is last sampling, namely the data of new sampling are becoming greatly always, and maximal value is being upgraded always, and minimum value is not upgraded, so peaked update times is greater than the update times of minimum value, S2=1 in S2 comparer, data output sequence is Dmin, Dmax, be propradation, conform to Fig. 2-1;
As shown in Fig. 2-2, when decline state, maximal value is sampling for the first time, minimum value is sampled the last time, namely the data of new sampling are diminishing always, and minimum value is being upgraded always, and maximal value is not upgraded, so peaked update times is less than the update times of minimum value, S2=0 in S2 comparer, data output sequence is Dmax, Dmin, be decline state, conform to Fig. 2-2;
As Figure 2-3, when not rising the state also not declining, maximal value update times equates with minimum value update times, differentiation sequentially again, so just can be included in the state that rises or decline, in the present invention this situation is included into decline state, conform to Fig. 2-3;
When N=1, switch disconnects, and maximal value and the minimum value of the output of peak value parallel detection module, without peak value serial detection module, be directly inputted to after sequence in reservoir, and the sequencing of maximal value and minimum value output is determined in sequence according to sequence signal S1; When N>1, switch is closed, peak value parallel detection module output maximal value and minimum value are synchronous through CLK2, be input to peak value serial detection module, when N digit counter completes counting, the final maximal value of output and final minimum value are input in reservoir after sequence, and the sequencing of final maximal value and final minimum value output is determined in sequence according to sequence signal S2.
When N digit counter completes counting, maximal value and minimum value after sequence are outputed in reservoir to the sampled point detecting as peak value; Whole peak value detects repeated sampling, to storer, is filled with and finishes sampling, completes a screen waveform acquisition.
Claims (1)
1. eliminate peak value and detect the system that by mistake produces burr, comprise PLL, ADC, CLK1, CLK2, reduction of speed processor module, peak detection block, reservoir;
Described PLL is phaselocked loop, and the ADC required clock frequency of sampling is provided;
Described ADC provides the data-signal of analog-converted numeral;
Described CLK1 is ADC sampling clock, and CLK2 is the clock of data output after reduction of speed, and reduction of speed coefficient is 2
n, meet CLK2=CLK1/2
n;
Described reduction of speed processing module is to utilize string to turn and technology, and data bit is expanded, and the data-signal of ADC output is synchronous through CLK1, is input to reduction of speed processor module;
Described peak detection block comprises peak value parallel detection module, peak value serial detection module, output switch, N digit counter; Described peak value parallel detection module becomes the data of ADC into 2 after reduction of speed processor module
nindividual parallel data, relatively exports large value and little value between two by comparer at different levels, through n level, relatively obtains maximal value and minimum value;
Described peak value serial detection module comprises maximum value detector, minimum detector, maximal value and minimum value through the output of peak value parallel detection module are input to respectively in corresponding maximum value detector and minimum detector, contrast with maximal value and the minimum value of last time respectively, the maximal value that the maximal value of new input is greater than last time just remains the maximal value of newly input, otherwise the maximal value that keeps last time, the minimum value that the minimum value of new input is less than last time just remains the minimum value of newly input, otherwise keeps the minimum value of last time constant;
Described N digit counter is the number of times of counting input maximal value and minimum value, N digit counter is counted CLK2, often carry out a clock, counter adds 1, when N digit counter does not complete counting, output switch disconnects, when N digit counter completes counting, output switch is closed, and final maximal value and final minimum value are input in reservoir;
It is characterized in that: described peak value parallel detection module also comprises S1 comparer, data are also exported and are indicated position Pmax.i or Pmin.i when comparer at different levels is relatively exported large value and little value between two, and i=2
n-2, n is positive integer; Output sequence signal S1 when relatively selecting maximal value and minimum value through n level, wherein the 1st grade has 2
n-1individual comparer, the 2nd grade has 2
n-2individual large value comparer and 2
n-2little value comparer, the like in n level, have 1 large value comparer and 1 little value comparer; Described sequence signal S1 is that Smax and Smin relatively obtain through S1 comparer, described Smax and Smin be output maximal value and minimum value 2
nposition in individual data, this position is that Pmin.i is definite by signs at different levels position Pmax.i, method is as follows:
First according to afterbody, be the sign position Pmax.i of n level comparer, Pmin.i, determines that maximal value and minimum value are upper half or the bottom halfs of getting, and described upper half and the data volume of bottom half are equal, and upper half is 2
nthe first half of individual data, bottom half is 2
nthe latter half of individual data; And then be the sign position of n-1 level comparer according to the 2nd grade of inverse, in halfth district, place, dwindle again the position that half scope is determined maximal value and minimum value; Recursion one-level forward in the same way again, at place, halfth district dwindles the position that half scope is determined maximal value and minimum value again, and recursion, finally determines that maximal value and minimum value are 2 so layer by layer
nparticular location in individual data;
At the 1st grade relatively time, when one be value greatly, another is little value, Pmax.i and Pmin.i are negate relations, that is: during Pmax.i=1, when Pmin.i=0 or Pmax.i=0, Pmin.i=1;
When Smax>Smin, sequence signal S1=1, data output sequence: Dmin, Dmax, is propradation, when Smax<Smin, sequence signal S1=0, data output sequence: Dmax, Dmin, for being decline state;
Described peak value serial detection module also comprises S2 comparer, and described peak detection block also comprises switch, sequence;
Described peak value serial detection module is exported a sequence signal S2 when selecting final maximal value and final minimum value, described sequence signal S2 is that in peak value serial detection module, maximal value update times FNmax and minimum value update times FNmin relatively obtain through S2 comparer, maximal value and minimum value through the output of peak value parallel detection module are input to respectively in corresponding maximum value detector and minimum detector, contrast with maximal value and the minimum value of last time respectively, if the maximal value of new input is greater than, the maximal value of last time just remains the maximal value of newly input and update times FNmax adds 1, otherwise keep maximal value and the update times FNmax of last time constant, if the minimum value of new input is less than, the minimum value of last time just remains the minimum value of newly input and update times FNmin adds 1, otherwise keep minimum value and the update times FNmin of last time constant,
Maximal value update times FNmax and minimum value update times FNmin input S2 comparer, if it is that maximal value update times is greater than minimum value update times that FNmax is greater than FNmin, sequence signal S2=1, data output sequence: Dmin, Dmax, it is propradation, if it is that maximal value update times is less than minimum value update times that FNmax is less than FNmin, sequence signal S2=0, data output sequence: Dmax, Dmin, for being decline state, if it is that maximal value update times equals minimum value update times that FNmax equals FNmin, differentiation sequentially again, can be included in rising or decline state,
When N=1, switch disconnects, and maximal value and the minimum value of the output of peak value parallel detection module, without peak value serial detection module, be directly inputted to after sequence in reservoir, and the sequencing of maximal value and minimum value output is determined in sequence according to sequence signal S1; When N>1, switch is closed, peak value parallel detection module output maximal value and minimum value are synchronous through CLK2, be input to peak value serial detection module, when N digit counter completes counting, the final maximal value of output and final minimum value are input in reservoir after sequence, and the sequencing of final maximal value and final minimum value output is determined in sequence according to sequence signal S2.
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Cited By (5)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN105116318A (en) * | 2015-09-02 | 2015-12-02 | 电子科技大学 | Method for realizing burr detection in logic analyzer |
| CN105680947A (en) * | 2015-12-29 | 2016-06-15 | 暨南大学 | Serial data receiving method capable of filtering burrs |
| CN107517072A (en) * | 2016-06-16 | 2017-12-26 | 上海华虹集成电路有限责任公司 | The decoding circuit received for magnetizing mediums signal in ISO7811 agreements |
| CN108288909A (en) * | 2018-01-12 | 2018-07-17 | 广东美的厨房电器制造有限公司 | Method and apparatus for bus voltage ripple control |
| CN114136209A (en) * | 2021-11-24 | 2022-03-04 | 京东方科技集团股份有限公司 | Eyeball position positioning circuit, method, substrate and virtual reality wearable device |
Citations (5)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US5115404A (en) * | 1987-12-23 | 1992-05-19 | Tektronix, Inc. | Digital storage oscilloscope with indication of aliased display |
| CN1272628A (en) * | 1999-04-29 | 2000-11-08 | 特克特朗尼克公司 | Cross digital peak value detector |
| CN101051059A (en) * | 2006-03-20 | 2007-10-10 | 特克特朗尼克公司 | Waveform compression and display |
| CN102520228A (en) * | 2011-12-21 | 2012-06-27 | 王子斌 | Peak value detection method in digital storage oscilloscope and system thereof |
| CN103176012A (en) * | 2011-12-22 | 2013-06-26 | 北京普源精电科技有限公司 | Oscilloscope capable of improving measurement accuracy and measurement method |
-
2013
- 2013-12-10 CN CN201310665549.8A patent/CN103604968B/en active Active
Patent Citations (5)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US5115404A (en) * | 1987-12-23 | 1992-05-19 | Tektronix, Inc. | Digital storage oscilloscope with indication of aliased display |
| CN1272628A (en) * | 1999-04-29 | 2000-11-08 | 特克特朗尼克公司 | Cross digital peak value detector |
| CN101051059A (en) * | 2006-03-20 | 2007-10-10 | 特克特朗尼克公司 | Waveform compression and display |
| CN102520228A (en) * | 2011-12-21 | 2012-06-27 | 王子斌 | Peak value detection method in digital storage oscilloscope and system thereof |
| CN103176012A (en) * | 2011-12-22 | 2013-06-26 | 北京普源精电科技有限公司 | Oscilloscope capable of improving measurement accuracy and measurement method |
Non-Patent Citations (1)
| Title |
|---|
| 郭宗平等: "信号采集中峰值检测电路的设计与实现", 《中国测试》 * |
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| CN105116318A (en) * | 2015-09-02 | 2015-12-02 | 电子科技大学 | Method for realizing burr detection in logic analyzer |
| CN105116318B (en) * | 2015-09-02 | 2018-02-02 | 电子科技大学 | A kind of method that burr detection is realized in logic analyser |
| CN105680947A (en) * | 2015-12-29 | 2016-06-15 | 暨南大学 | Serial data receiving method capable of filtering burrs |
| CN105680947B (en) * | 2015-12-29 | 2018-01-19 | 暨南大学 | A kind of Serial data receiving method for filtering out burr |
| CN107517072A (en) * | 2016-06-16 | 2017-12-26 | 上海华虹集成电路有限责任公司 | The decoding circuit received for magnetizing mediums signal in ISO7811 agreements |
| CN107517072B (en) * | 2016-06-16 | 2021-07-23 | 上海华虹集成电路有限责任公司 | Decoding circuit for magnetic medium signal reception in ISO7811 protocol |
| CN108288909A (en) * | 2018-01-12 | 2018-07-17 | 广东美的厨房电器制造有限公司 | Method and apparatus for bus voltage ripple control |
| CN114136209A (en) * | 2021-11-24 | 2022-03-04 | 京东方科技集团股份有限公司 | Eyeball position positioning circuit, method, substrate and virtual reality wearable device |
| CN114136209B (en) * | 2021-11-24 | 2023-11-24 | 京东方科技集团股份有限公司 | Eyeball position positioning circuit, eyeball position positioning method, substrate and virtual reality wearable device |
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