CN100351947C

CN100351947C - Biphase precharging circuit and its composite eliminating leakage current circuit

Info

Publication number: CN100351947C
Application number: CNB031006930A
Authority: CN
Inventors: 陈健中
Original assignee: Winbond Electronics Corp
Current assignee: Winbond Electronics Corp
Priority date: 2003-01-17
Filing date: 2003-01-17
Publication date: 2007-11-28
Anticipated expiration: 2023-01-17
Also published as: CN1517999A

Abstract

The present invention discloses a two-phase precharging circuit used for eliminating leakage current produced by short circuiting of a bit line and a word line of a dynamic random access memory. The present invention comprises a complementary bit line, a precharging voltage source and a precharging equalization circuit, wherein one end of the precharging equalization circuit is connected to the precharging voltage source, and the other end is connected to the complementary bit line; at least one control signal from the outside is used for respectively activating a pulse at the front end and the tail end of an operating mode of the dynamic random access memory, and the bit line of the precharging voltage source is conducted; the control signal is in a closed state in a quiet mode. Thus, the present invention has the advantage that electric current leakage caused by the short circuit between the bit line and the word line can be eliminated.

Description

The elimination leakage current circuit of two-phase pre-charge circuit and combination thereof

Technical field

The present invention relates to a kind of circuit that dynamic random is handled the leakage current of internal memory of eliminating, particularly a kind ofly eliminate the circuit that dynamic random is handled short circuit standby current (shortDC standby current) between the bit line of internal memory and word line.

Background technology

Handle in the manufacture process of internal memory at dynamic random, occur the situation of word line and bitline short circuits sometimes, thereby cause leakage current and influence the acceptance rate of product.

A kind of mode that addresses the above problem is at U.S. Patent number 5,499,211, title is disclosed for the patent specification of " BIT-LINE PRECHARAGE CURRENT LIMITER FOR CMOS DYNAMICMEMORIES (the bit-line pre-charge demand limiter that is used for the CMOS dynamic storage) ".As shown in Figure 1, the circuit 10 of the prior art comprises a word line 12, a complementary bit lines 13, a precharge equalizing circuit 14 (equalization circuit) and a current-limiting apparatus 11.This equalizing circuit effect is to paratope line provides identical current potential when the original state, and precharge purpose is to make paratope line to have a predetermined current potential when original state.The prior art causes excessive leakage current for avoiding word line (WL) and bit line (BL) short circuit, between pre-charge voltage source (VBLEQ) 15 and bit line 13, add this current-limiting apparatus 11 especially, the N transistor npn npn (NMOS) of a depletion type for example is in order to the maximum leakage current of restriction when bit line and word line are short-circuited.

So generally speaking, word line driving voltage (V _WL) be 0 volt when still-mode.And this moment, the EQL control signal was activated, and made bit-line voltage V _BLGreater than 0 volt, therefore when still-mode, will form a leakage current path, this leakage current flow to earth terminal by BLEQ, BL, WL.In other words, the leakage current when existing mode only can reduce word line 12 and bit line 13 short circuits but can not be eliminated effectively.Handle the product of internal memory for present low-power dynamic random and use, this leakage current is still because of the too big demand that can't satisfy market.

In view of the problem that prior art exists, the present invention proposes the two-phase pre-charge circuit of a novelty, to overcome above-mentioned shortcoming.

Summary of the invention

Fundamental purpose of the present invention provides a kind of two-phase pre-charge circuit, and it only activates in mode of operation, in order to conducting pre-charge voltage source to bit line.And when still-mode, this two-phase pre-charge circuit is in the state that opens circuit, thereby can eliminate the leakage current because of short circuit caused between position and word line.

Another object of the present invention provides the leakage current circuit with the combined elimination DRAM (Dynamic Random Access Memory) of above-mentioned two-phase pre-charge circuit, handles the application demand of internal memory applicable to the low-power dynamic random.

In order to achieve the above object, according to an aspect of the present invention, provide a kind of two-phase pre-charge circuit, be used to eliminate DRAM (Dynamic Random Access Memory), included complementary bit lines because of the leakage current that bit line and word line short circuit produce; One pre-charge voltage source; One precharge equalizing circuit, one end are connected to this pre-charge voltage source, and the other end is connected to this complementary bit lines; Wherein only activate a pulse respectively at the front end and the end of the mode of operation of this DRAM (Dynamic Random Access Memory) from least one control signal of outside, to this bit line, and this control signal system is in closing state when still-mode in order to this pre-charge voltage source of conducting.

According to a further aspect in the invention, a kind of circuit of eliminating the short circuit leakage current of DRAM (Dynamic Random Access Memory) is provided, comprise a pre-charge voltage source, a plurality of word line, a plurality of complementary bit lines and a plurality of precharge equalizing circuit, it is characterized in that one of this precharge equalizing circuit end is connected to this pre-charge voltage source, the other end is connected to those complementary bit lines; And from least one control signal of outside only before the mode of operation of this DRAM (Dynamic Random Access Memory) end and end activate a pulse respectively, to this bit line, and this control signal is in closing state when still-mode in order to this pre-charge voltage source of conducting.

Description of drawings

The present invention will describe in detail according to accompanying drawing, wherein:

Fig. 1 (a) is the structural representation of the circuit of an existing elimination leakage current;

Fig. 1 (b) is the working timing figure of Fig. 1 (a);

Fig. 2 (a) is the physical circuit figure of first embodiment of elimination leakage current circuit of the present invention;

Fig. 2 (b) is the working timing figure of Fig. 2 (a);

Fig. 3 (a) is the physical circuit figure of second embodiment of elimination leakage current circuit of the present invention; And

The working timing figure of Fig. 3 (a) of Fig. 3 (b).

Fig. 4 is the embodiment that elimination leakage current circuit of the present invention is used for storage matrix.

Embodiment

Please refer to Fig. 2 (a), the circuit 20 of the short circuit leakage current of elimination DRAM (Dynamic Random Access Memory) of the present invention comprises a pre-charge voltage source 24, a plurality of word line 22, a plurality of complementary bit lines 23 and a plurality of precharge equalizing circuit 21.Provide θ 1 control signal 25 to precharge equalizing circuit 21 among this embodiment with two-phase.This θ 1 control signal 25 will activate two pulses during mode of operation, wherein first pulse is positioned at before the word line work, and another pulse is positioned at after the word line work, its objective is a pre-charge voltage source VBLEQ24 is precharged to complementary bit lines 23.More prior be this θ 1 control signal 25 during still-mode for closed condition, even if therefore bit line 23 and word line 22 are short-circuited, also do not have leakage current and produce.By circuit of the present invention, the flaw that can eliminate because of manufacture process produces the problem of leakage current in stationary state, and can satisfy the product requirement that the low-power dynamic random is handled internal memory.

In addition, because the present invention cuts off the guiding path of bit line 23 at still-mode, the leakage current in the time of therefore can eliminating bit line 23 and word line 22 short circuits fully.In other words, the present invention can omit the employed current-limiting apparatus 11 of prior art and still can reach better effect.

Please refer to Fig. 3 (a), this embodiment adopts two control signal θ 1 and θ 2 at this precharge equalizing circuit 21.This θ 1 control signal is used for starting impulse during the mode of operation before the word line work, and these θ 2 control signals are used for starting impulse during the mode of operation after word line work.No matter right identical with first embodiment be, be control signal θ 1 or θ 2, and it is closed condition during still-mode, so can guarantee that reason bit line 23 and word line 22 are not short-circuited and produce leakage current.

Pre-charge circuit 21 of the present invention is not limited to above-mentioned ad hoc structure.In the structure of Fig. 2 (a), comprise the first transistor 26, transistor seconds 27 and the 3rd transistor 28, this the first transistor 26 is crossed over and is connected to this a plurality of complementary bit lines 23, this the second and the 3rd transistor 27,28 is connected in series respectively to this a plurality of complementary bit lines 23, and this first, second be connected to this control signal 25 with the gate pole of the 3rd transistor 26,27,28.So, the structure of Fig. 2 (a) only is an illustration, allly can be implemented in the structure that this pre-charge voltage source VBLEQ24 is precharged to during the mode of operation complementary bit lines 23, is within the scope that technological thought of the present invention contains.

Fig. 4 is the embodiment that elimination leakage current circuit of the present invention is used for storage matrix.Identical with most of storage matrix lines, the storage unit that will be positioned at same row is connected to same bit line, and will be connected to same word line with the storage unit of delegation.Characteristics of the present invention are to make the storage unit with delegation to be connected to same control signal θ 1.Because the present invention can utilize control signal θ 1 to cut off the guiding path of bit line at still-mode, the leakage current in the time of therefore can eliminating bit line and word line short circuit fully.

Technology contents of the present invention and technical characterstic the sixth of the twelve Earthly Branches describe as above, yet those skilled in the art still can make multiple replacement and the modification that does not deviate from spirit of the present invention based on teaching of the present invention and disclosed content.Therefore, protection scope of the present invention should be not limited to the described content of embodiment, and should comprise various replacement and the modifications that do not deviate from spirit of the present invention, and is contained by the defined scope of accompanying Claim.

Claims

1, a kind of two-phase pre-charge circuit is used to eliminate DRAM (Dynamic Random Access Memory) because of the leakage current that bit line and word line short circuit produce, and comprises:

A plurality of complementary bit lines;

One pre-charge voltage source;

One precharge equalizing circuit, one end are connected to this pre-charge voltage source, and the other end is connected to those complementary bit lines;

Wherein from least one control signal of outside only before the mode of operation of this DRAM (Dynamic Random Access Memory) end and end activate a pulse respectively, to this bit line, and this control signal system is in closing state when still-mode in order to this pre-charge voltage source of conducting.

2, according to the two-phase pre-charge circuit of claim 1, wherein this precharge equalizing circuit comprises first, second and the 3rd transistor, this the first transistor is crossed over and is connected to this complementary bit lines, this the second and the 3rd transistor is connected in series respectively to this complementary bit lines, and this first, second and the 3rd transistorized gate pole be provided to this control signal.

3, according to the two-phase pre-charge circuit of claim 1, the control signal that wherein offers this precharge equalizing circuit is two groups of control signals, and each is organized control signal and is respectively applied for front end and the terminal pulse that produces mode of operation.

4, a kind of circuit of eliminating the short circuit leakage current of DRAM (Dynamic Random Access Memory), comprise a pre-charge voltage source, a plurality of word lines, a plurality of complementary bit lines and a plurality of precharge equalizing circuit, it is characterized in that described several precharge equalizing circuits have a control signal, and described control signal only starts a pulse respectively at the front end and the end of described dynamic RAM mode of operation, be used for the source conducting of described pre-charge voltage to described several complementary bit lines, and described control signal is closed when still-mode, can eliminate the leakage current because of short circuit caused between described bit line and described word line thus.

5, according to the circuit of the short circuit leakage current of the elimination DRAM (Dynamic Random Access Memory) of claim 4, the control signal that wherein offers these a plurality of precharge equalizing circuits is two groups, and each is organized control signal and is respectively applied for front end and the terminal pulse that produces mode of operation.

6, according to the circuit of the short circuit leakage current of the elimination DRAM (Dynamic Random Access Memory) of claim 4, wherein these a plurality of precharge equalizing circuits comprise first, second and the 3rd transistor, this the first transistor is crossed over and is connected to this a plurality of complementary bit lines, this the second and the 3rd transistor is connected in series respectively to these a plurality of complementary bit lines, and this first, second and the 3rd transistorized gate pole be provided to this control signal.