CN100349464C - Random access storage frame buffer device and its control method - Google Patents
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Abstract
The present invention discloses an RAM frame buffer device which comprises an RAM used for storing frame data, and a frame buffer controller used for controlling the RAM frame buffer device, wherein the frame buffer controller at least comprises an image processing module interface used for connecting an image processing module, an RAM interface unit used for the RAM, and a control logic unit used for control realization, the frame buffer controller further comprises a power consumption control module, and according to preset image processing algorithms, the power consumption control module is used for setting the RAM in a normal working state in a time period when the image processing module needs to access the frame buffer device and setting the RAM in a low power consumption state in a time period when the image processing module doesn't need to access the frame buffer device. The present invention also provides a control method of the RAM frame buffer device. The present invention effectively lowers the energy consumption of the RAM frame buffer device.
Description
Technical field
The present invention relates to the memory technology field, particularly a kind of random-access memory (ram) frame buffer device and control method thereof.
Background technology
In Digital Image Processing, the image data storage that generally will need to handle is in static random access memory (SRAM) frame buffer device, and image processing module is visited this SRAM frame buffer device, reads image data as required then.
SRAM frame buffer device of the prior art as shown in Figure 1 comprises the SRAM that is used for storing image data and is used to control the frame buffer controller of this SRAM.The control logic module that frame buffer controller comprises the image processing module interface that is connected with the external image processing module, the SRAM interface unit that is connected with SRAM and is used to realize control.This SRAM frame buffer controller is connected by the image processing module of image processing module interface with the outside, and transmits address information, view data and the control information of view data; Frame buffer controller transmits address information, view data and the control information of view data by described SRAM interface unit and SRAM; Control logic module is used for producing various control informations according to the visit of image processing module, thereby finish read operation to SRAM, for example when image processing module is visited this SRAM frame buffer device reading of data, control logic module produces the control information to SRAM interface unit and image processing module interface, SRAM interface unit and image processing module interface are determined operating state mutually according to the control information of control logic module then, when the SRAM interface unit is transmission (Transfer) state, the image processing module interface is that image processing module is from SRAM frame buffer device reading of data when receiving (Receive) state.
Adopt SRAM frame buffer device as shown in Figure 1, during image processing module was visited this SRAM frame buffer device reading of data, SRAM can be in normal operating conditions always.But, image processing module is after reading a secondary data, arranged in deal with data and non-reading of data a very long time, so during this period of time SRAM still is in normal operating conditions, and the normal operating conditions of SRAM frame buffer device expends a lot of energy than low power consumpting state more, it is too fast to make that like this mobile phone, digital camera etc. contain the battery consumption of equipment of SRAM frame buffer device, has shortened the useful life of battery.
Summary of the invention
In view of this, the present invention proposes a kind of RAM frame buffer device and control method thereof, its purpose is to reduce the spent energy of RAM frame buffer device.
According to above-mentioned purpose, the invention provides a kind of RAM frame buffer device, at least comprise the RAM that is used to preserve frame data, and the frame buffer controller that is used to control described RAM frame buffer device, wherein said frame buffer controller comprises the image processing module interface that is used to connect image processing module at least, be used to connect the RAM interface unit of described RAM, and be connected in control logic module between image processing module interface and the RAM interface unit, described frame buffer controller further comprises power consumption control module, be connected between image processing module interface and the RAM interface unit, be used for described RAM being set and be in normal operating conditions, in the time period that described image processing module does not need to visit frame buffer device described RAM is set and is in low power consumpting state in the time period that described image processing module need be visited frame buffer device.
In such scheme, described RAM is SRAM.
Described RAM comprises sleep pattern enable signal ZZ pin; Described power consumption control module is provided with described RAM and is in normal operating conditions by the ZZ pin being changed to inactive level, perhaps described RAM is set is in low power consumpting state by the ZZ pin being changed to significant level.
In such scheme, described RAM is SDRAM.
Described SDRAM comprises clock enable signal CKE pin; Described power consumption control module is provided with described SDRAM and is in normal operating conditions by the CKE pin being changed to significant level, perhaps described SDRAM is set is in low power consumpting state by the CKE pin being changed to inactive level.
Described power consumption control module further is connected with control logic module; Described control logic module is further used for controlling the in running order or non operating state of power consumption control module; When described power consumption control module is in running order, enable of the power consumption state control of described power consumption control module to described RAM; When described power consumption control module is in non operating state, forbid enabling of the power consumption state control of described power consumption control module to described RAM.
The present invention also provides the control method of a kind of RAM frame buffer device of volume, and this method relates to image processing module and RAM frame buffer device, and described RAM frame buffer device comprises RAM and frame buffer controller at least, and this method may further comprise the steps:
A. image processing module notification frame buffer control unit image processing begins;
B. frame buffer controller is provided with described RAM in the time period that described image processing module need be visited frame buffer device and is in normal operating conditions, in the time period that described image processing module does not need to visit frame buffer device described RAM is set and is in low power consumpting state.
In such scheme, described RAM is SRAM.
Described RAM comprises the ZZ pin; In step B, described frame buffer controller is provided with described RAM and is in normal operating conditions by the ZZ pin being changed to inactive level, perhaps described RAM is set is in low power consumpting state by the ZZ pin being changed to significant level.
In such scheme, described RAM is SDRAM.
Described SDRAM comprises the CKE pin; In step B, described frame buffer controller is provided with described SDRAM and is in normal operating conditions by the CKE pin being changed to significant level, perhaps described SDRAM is set is in low power consumpting state by the CKE pin being changed to inactive level.
Further comprising before the described steps A: after frame buffer controller is set according to the image processing algorithm that image processing module adopted in advance obtains notice that the image processing module image processing begins, in the time period that described image processing module need be visited frame buffer device described RAM is set and is in normal operating conditions, in the time period that described image processing module does not need to visit frame buffer device described RAM is set and is in low power consumpting state.
Preferably, described image processing algorithm is three step search methods; Described step B comprises: frame buffer controller is provided with described RAM in the time period that image processing module is visited frame buffer device for the first time and is in normal operating conditions; Time period in that image processing module is handled according to the data of for the first time visiting frame buffer device and being read, described RAM is set is in low power consumpting state; In the time period of image processing module back-call frame buffer device, described RAM is set is in normal operating conditions; The time period that the data that read according to the back-call frame buffer device at image processing module are handled, described RAM is set is in low power consumpting state; Visit time period of frame buffer device for the third time at described image processing module, described RAM is set is in normal operating conditions; Time period in that described image processing module is handled according to the data of visiting frame buffer device for the third time and being read, described RAM is set is in low power consumpting state.
From such scheme as can be seen, because the present invention is according to the rule of image processing module visit RAM frame buffer device in the image processing algorithm that sets in advance, when image processing module is not visited the RAM frame buffer device, RAM is not placed low power consumpting state, when image processing module visit RAM frame buffer device, RAM is placed normal operating conditions, thereby reduced the spent energy of RAM frame buffer device.
Description of drawings
Fig. 1 is the structural representation of SRAM frame buffer device in the prior art;
Fig. 2 is the structural representation of SRAM frame buffer device among the present invention;
Fig. 3 is the schematic diagram of three step search methods;
Fig. 4 is the flow chart of first embodiment of the invention;
Fig. 5 is the pin schematic diagram of the k7m803625B of Samsung model SRAM;
Fig. 6 is the structural representation of SDRAM frame buffer device among the present invention.
Embodiment
For making the purpose, technical solutions and advantages of the present invention clearer, the present invention is described in more detail by the following examples.
Unlike the prior art be, the present invention has increased power consumption control module in frame buffer controller, this power consumption control module is according to the rule of image processing module visit RAM frame buffer device in the image processing algorithm, when image processing module does not need to visit the RAM frame buffer device, RAM is not placed low power consumpting state, when image processing module need be visited the RAM frame buffer device, RAM is placed normal operating conditions, to realize reducing the spent energy of RAM frame buffer device.
Fig. 2 is the structural representation of SRAM frame buffer device in the first embodiment of the invention.Comprise SRAM frame buffer device and image processing module among the figure, this SRAM frame buffer device comprises SRAM and frame buffer controller, and SRAM is used to preserve view data, and frame buffer controller is used for the SRAM frame buffer device is controlled.Described frame buffer controller comprises image processing module interface, SRAM interface unit, control logic module and power consumption control module, wherein identical in the effect of image processing module interface, SRAM interface unit and the prior art, the image processing module interface is used to connect image processing module, transmit view data, address information and control information, the SRAM interface unit is used to connect SRAM and frame buffer controller, and transmits view data, address information and control information.Be connected in the control logic module between SRAM interface unit and the image processing module interface, be used for producing control information, thereby finish read operation SRAM according to the visit of image processing module.Power consumption control module, be connected between SRAM interface unit and the image processing module interface, and be connected with control logic module, power consumption control module is visited the temporal regularity of described SRAM frame buffer device according to predefined image processing module needs, in the time period that described image processing module need be visited frame buffer device described SRAM is set and is in normal operating conditions, in the time period that described image processing module does not need to visit frame buffer device described SRAM is set and is in low power consumpting state.
Control logic module can also further be controlled the in running order or non operating state of power consumption control module by control information, when power consumption control module is in non operating state, forbid enabling of the power consumption state control of described power consumption control module, transmit normal control information in the prior art between SRAM interface unit and the image processing module interface described RAM; When power consumption control module is in running order, enable the power consumption state control of described power consumption control module to described RAM, power consumption control module further can send to SRAM by the SRAM interface unit and put the control information of SRAM in normal operating conditions and low power consumpting state.
The algorithm of supposing the image processing module employing is three step searching algorithms as shown in Figure 3, and the search procedures of three step searching algorithms divide three steps to finish, and the macro block with 16 * 16 bytes is that unit explanation three goes on foot search methods below:
The first step, in the searching for reference frame size be 9 * 9 macro blocks window the center macro block and be positioned at the macro block on 8 summits on every side, promptly among Fig. 3 with the round dot of " 1 " mark, draw the macro block that mates the most with current macro;
In second step, the macro block of coupling the most that obtains with first step search is that center, size are the new window of 5 * 5 macro blocks, searches for this window macro block on 8 summits on every side, promptly uses the round dot of " 2 " mark among Fig. 3, draws the macro block that mates the most with current macro;
The 3rd goes on foot, and the macro block of coupling the most that obtains with the search of second step is that center, size are the new window of 3 * 3 macro blocks, searches for this window macro block on 8 summits on every side, promptly uses the round dot of " 3 " mark among Fig. 3, draws the macro block that mates the most with current macro.
Suppose that first step search needs time T 1 in the three step search methods, the search of second step needs time T 2, the search of the 3rd step needs time T 3, read the used data of first step search from the SRAM frame buffer device and need time T 01, reading the used data of second step search needs time T 02, and reading the used data of the 3rd step search needs time T 03.In power consumption control module, carry out following setting in advance: receive after image processing module notice power consumption control module begins to carry out the image processing of special algorithm, when image processing module need be visited the SRAM frame buffer device, control SRAM is in normal operating conditions, when image processing module did not need to visit the SRAM frame buffer device, control SRAM was in low power consumpting state.Specifically, power consumption control module is after obtaining notice, and the T01 that reads the data that the three step search method first steps need at image processing module visit SRAM frame buffer is in the time period, and control SRAM is in normal operating conditions; Then after the data that read 9 * 9 macro blocks, power consumption control module control SRAM is not in low power consumpting state in image processing module does not need to visit the time T 1 of SRAM frame buffer device; The T02 that image processing module need be visited the SRAM frame buffer device behind the T1 is in the time period, and control SRAM is in normal operating conditions; After second time reading of data, power consumption control module control SRAM is not in low power consumpting state in image processing module does not need to visit the time T 2 of SRAM frame buffer device; The T03 that image processing module need be visited the SRAM frame buffer device behind the T2 controlled SRAM again and is in normal operating conditions in the time period; After reading of data for the third time, power consumption control module control SRAM is not in low power consumpting state in image processing module does not need to visit the time T 3 of SRAM frame buffer device; Control SRAM again when image processing module need be visited the SRAM frame buffer device behind the T3 and be in normal operating conditions.Time T 1, T2, T3 and the image processing module of image processing module search are visited time T 01, T02, the T03 of SRAM frame buffer device at every turn, it can be the time that directly defines, also can be to define according to the clock cycle, for example T1 equals N1 clock cycle, T2 and equals N2 clock cycle, T3 and equal N3 clock cycle, T01 and equal N01 clock cycle, T02 and equal N02 clock cycle, T03 and equal N03 clock cycle.
After carrying out above-mentioned the setting,, adopt the workflow of SRAM frame buffer controller among Fig. 2 as follows with reference to figure 4:
Step 401, the power consumption control module in the image processing module notice SRAM frame buffer controller, image processor begins to carry out the image processing of special algorithm.In first embodiment, the image processing of special algorithm refers to adopt three step searching algorithms to carry out estimation.Image processing module can be by the beginning of the request notice power consumption control module image processing process of reading of data for the first time of three step search methods, also can notify the beginning of power consumption control module image processing process by alternate manner, for example image processing module sends a mode such as signal to power consumption control module.
Step 406, SRAM frame buffer controller comprise the address of view data according to the access request of image processing module in this request, read the view data of 3 * 3 macro blocks of reference frame and the current macro of present frame from SRAM, and send to image processing module.In the section T03, power consumption control module places normal operating conditions with SRAM at this moment.
SRAM is an example with Samsung (Samsung) k7m803625B of company model, illustrates that SRAM frame buffering is controlled the process that SRAM is changed to low power consumpting state and normal operating conditions in the above-mentioned flow process.As shown in Figure 5, this SRAM has 100 pins, and wherein label is that 64 pin is sleep pattern enable signal (ZZ) pin, and this ZZ pin is effective when high level, and promptly high level is that significant level, low level are inactive level.When the ZZ of SRAM pin was high level, this SRAM was changed to the sleep pattern (Sleep Mode) of low-power consumption, and the power consumption of SRAM only is 20% of a normal operating conditions under this pattern; When the ZZ of SRAM pin was low level, this SRAM was changed to normal operating conditions.SRAM power consumption control module of the present invention is exactly to be changed to low level by the ZZ pin with SRAM SRAM is changed to low power consumpting state, is changed to high level by the CKE pin with SRAM SRAM is changed to normal operating conditions.
The process that other SRAM is changed to low power consumpting state or normal operating conditions is similar to top example, may be different be the title of pin or the height of level.
In first embodiment, described frame buffer device is the SRAM frame buffer device, is synchronous DRAM (SDRAM) frame buffer device at frame buffer device described in the second embodiment of the present invention.As shown in Figure 6, the SDRAM frame buffer device comprises SDRAM and frame buffer controller, and SDRAM is used to preserve view data, and frame buffer controller is used for the SDRAM frame buffer device is controlled.Described frame buffer controller comprises the image processing module interface, the sdram interface parts, control logic module and power consumption control module, image processing module interface wherein, the image processing module interface of SRAM frame buffer device among the effect of sdram interface parts and prior art and first embodiment, the SRAM interface unit is identical, the image processing module interface is used to connect image processing module, transmit view data, address information and control information, the sdram interface parts are used to connect SDRAM and frame buffer controller, and transmit view data, address information and control information.Be connected in the control logic module between sdram interface parts and the image processing module, be used for visit, produce control information, thereby finish read operation SDRAM according to image processing module.Power consumption control module, be connected between sdram interface parts and the image processing module interface, and be connected with control logic module, power consumption control module is visited the temporal regularity of described SDRAM frame buffer device according to predefined image processing module needs, in the time period that described image processing module need be visited frame buffer device described SDRAM is set and is in normal operating conditions, in the time period that described image processing module does not need to visit frame buffer device described SDRAM is set and is in low power consumpting state.
Control logic module can also further be controlled the in running order or non operating state of power consumption control module by control information, when power consumption control module is in non operating state, transmit normal control information between sdram interface parts and the image processing module interface; When power consumption control module was in running order, power consumption control module further can send to SDRAM by the sdram interface parts and put the control information of SRAM in normal operating conditions and low power consumpting state.
What the SDRAM frame buffer device was structurally different with the SRAM frame buffer device is memory portion, and one is SDRAM, and one is SRAM; The interface of other parts is identical with function.
Adopt the workflow of SDRAM frame buffer device identical, repeat no more here with the workflow of SRAM frame buffer device.Power consumption control module is changed to low power consumpting state and normal operating conditions by clock enable signal (CKE) pin output high level, low level to SDRAM with SDRAM among second embodiment.When the CKE of SDRAM pin is an inactive level when being low level, SDRAM is in low-power consumption mode, and the power consumption of SDRAM only is 3% of a normal operating conditions under this pattern; When the CKE of SDRAM pin is a significant level when being high level, SDRAM is in normal operating conditions.
The above only is preferred embodiment of the present invention, and is in order to restriction the present invention, within the spirit and principles in the present invention not all, any modification of being done, is equal to replacement, improvement etc., all should be included within protection scope of the present invention.
Claims (13)
1, a kind of random access memory ram frame buffer device, at least comprise and be used to the frame buffer controller preserving the RAM of frame data and be used to control described RAM frame buffer device, wherein said frame buffer controller comprise the image processing module interface that is used to connect image processing module at least, be used to connect the RAM interface unit of described RAM and be connected in the image processing module interface and the RAM interface unit between control logic module
It is characterized in that, described frame buffer controller further comprises power consumption control module, be connected between image processing module interface and the RAM interface unit, be used for described RAM being set and be in normal operating conditions, in the time period that described image processing module does not need to visit frame buffer device described RAM is set and is in low power consumpting state in the time period that described image processing module need be visited frame buffer device.
2, frame buffer device according to claim 1 is characterized in that, described RAM is static random access memory SRAM.
3, frame buffer device according to claim 2 is characterized in that, described RAM comprises sleep pattern enable signal ZZ pin;
Described power consumption control module is provided with described RAM and is in normal operating conditions by the ZZ pin being changed to inactive level, perhaps described RAM is set is in low power consumpting state by the ZZ pin being changed to significant level.
4, frame buffer device according to claim 1 is characterized in that, described RAM is synchronous DRAM SDRAM.
5, frame buffer device according to claim 4 is characterized in that, described SDRAM comprises clock enable signal CKE pin;
Described power consumption control module is provided with described SDRAM and is in normal operating conditions by the CKE pin being changed to significant level, perhaps described SDRAM is set is in low power consumpting state by the CKE pin being changed to inactive level.
6, frame buffer device according to claim 1 is characterized in that, described power consumption control module further is connected with control logic module;
Described control logic module is further used for controlling the in running order or non operating state of power consumption control module;
When described power consumption control module is in running order, enable of the power consumption state control of described power consumption control module to described RAM; When described power consumption control module is in non operating state, forbid enabling of the power consumption state control of described power consumption control module to described RAM.
7, a kind of control method of RAM frame buffer device, this method relate to image processing module and RAM frame buffer device, and described RAM frame buffer device comprises RAM and frame buffer controller at least, it is characterized in that, this method may further comprise the steps:
A. image processing module notification frame buffer control unit image processing begins;
B. frame buffer controller is provided with described RAM in the time period that described image processing module need be visited frame buffer device and is in normal operating conditions, in the time period that described image processing module does not need to visit frame buffer device described RAM is set and is in low power consumpting state.
8, method according to claim 7 is characterized in that, described RAM is SRAM.
9, method according to claim 8 is characterized in that, described RAM comprises the ZZ pin;
In step B, described frame buffer controller is provided with described RAM and is in normal operating conditions by the ZZ pin being changed to inactive level, perhaps described RAM is set is in low power consumpting state by the ZZ pin being changed to significant level.
10, method according to claim 7 is characterized in that, described RAM is SDRAM.
11, method according to claim 10 is characterized in that, described SDRAM comprises the CKE pin;
In step B, described frame buffer controller is provided with described SDRAM and is in normal operating conditions by the CKE pin being changed to significant level, perhaps described SDRAM is set is in low power consumpting state by the CKE pin being changed to inactive level.
12, method according to claim 7 is characterized in that, further comprises before described steps A:
After frame buffer controller be set obtain notice that the image processing module image processing begins according to the image processing algorithm that image processing module adopted in advance, in the time period that described image processing module need be visited frame buffer device described RAM is set and is in normal operating conditions, in the time period that described image processing module does not need to visit frame buffer device described RAM is set and is in low power consumpting state.
13, method according to claim 12 is characterized in that, described image processing algorithm is three step search methods;
Described step B comprises: frame buffer controller is provided with described RAM in the time period that image processing module is visited frame buffer device for the first time and is in normal operating conditions; Time period in that image processing module is handled according to the data of for the first time visiting frame buffer device and being read, described RAM is set is in low power consumpting state; In the time period of image processing module back-call frame buffer device, described RAM is set is in normal operating conditions; The time period that the data that read according to the back-call frame buffer device at image processing module are handled, described RAM is set is in low power consumpting state; Visit time period of frame buffer device for the third time at described image processing module, described RAM is set is in normal operating conditions; Time period in that described image processing module is handled according to the data of visiting frame buffer device for the third time and being read, described RAM is set is in low power consumpting state.
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| JP2003186444A (en) * | 2001-12-13 | 2003-07-04 | Sharp Corp | Information processing system |
| CN1431829A (en) * | 2002-01-11 | 2003-07-23 | 三菱电机株式会社 | Image coding integrated circuit to lower power consumption according to target data |
| US20040233772A1 (en) * | 2003-03-20 | 2004-11-25 | Seiko Epson Corporation | Semiconductor device, semiconductor circuit, electronic equipment, and method of controlling clock-supply |
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Patent Citations (6)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPH08275142A (en) * | 1995-03-31 | 1996-10-18 | Kokusai Electric Co Ltd | Still image transmission method and its device |
| JPH10173832A (en) * | 1996-12-13 | 1998-06-26 | Ricoh Co Ltd | Facsimile equipment |
| JP2003186444A (en) * | 2001-12-13 | 2003-07-04 | Sharp Corp | Information processing system |
| CN1431829A (en) * | 2002-01-11 | 2003-07-23 | 三菱电机株式会社 | Image coding integrated circuit to lower power consumption according to target data |
| CN1376960A (en) * | 2002-04-27 | 2002-10-30 | 西安交通大学 | Interface controller for high-speed video processing and its design method |
| US20040233772A1 (en) * | 2003-03-20 | 2004-11-25 | Seiko Epson Corporation | Semiconductor device, semiconductor circuit, electronic equipment, and method of controlling clock-supply |
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