CN100337484C - Synchronous error measuring method and apparatus with envelope elimination and digital power amplifier restoration - Google Patents
Synchronous error measuring method and apparatus with envelope elimination and digital power amplifier restoration Download PDFInfo
- Publication number
- CN100337484C CN100337484C CNB031374476A CN03137447A CN100337484C CN 100337484 C CN100337484 C CN 100337484C CN B031374476 A CNB031374476 A CN B031374476A CN 03137447 A CN03137447 A CN 03137447A CN 100337484 C CN100337484 C CN 100337484C
- Authority
- CN
- China
- Prior art keywords
- power amplifier
- signal
- delay
- amplitude
- test signal
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Expired - Fee Related
Links
Images
Abstract
The present invention relates to a synchronous error measuring method and a synchronous error measuring apparatus with envelope elimination and digital power amplifier restoration. The method comprises the steps that a. a test signal A+cos (omega t) and sin (omega t) +jcos (omega t) are input; b. delay times T_delay 1, T_delay 2 of an amplitude branch circuit and a phase branch circuit are regulated, and thus, an output signal is minimal; c. the delay times T_delay 1, T_delay 2 at the minimal time of the output signal are taken for making a difference, and the difference value is used as a synchronization error. The apparatus comprises an envelop detector, a modulator, an amplitude limiter, a mixer, a local oscillator, a nonlinear power amplifier, a first delaying module which is a circuit module for regulating the delay time of the amplitude branch circuit, a second delaying module which is a circuit module for regulating the delay time of the phase branch circuit, and a feedback testing circuit. The synchronization error obtained by using the measuring apparatus and the measuring method of the present invention has high precision. Meanwhile, large influence can not be brought to the cost of the power amplifier, and disturbance caused by a great deal of artificial factors in the measuring processes can be effectively avoided.
Description
Technical field
The present invention relates to fields of measurement, relate in particular to a kind of envelope and eliminate and the synchronous error method of measurement of recovering digital power amplifier.
Technical background
Radio honeycomb communication system as WCDMA and CDMA2000 system, must adopt high performance Linear Power Amplifier.High efficiency Linear Power Amplifier can reduce the requirement of power amplifier thermal design on the one hand, has also reached purpose of power saving on the other hand.At present, the Linear Power Amplifier technology has become one of key technology in the mobile communcations system.
Envelope is eliminated and (the Envelope Elimination and Restoration) technology of recovery, it is the EER technology, be a kind of typical high efficiency, Linear Power Amplifier technology cheaply, the theory diagram of EER technology as shown in Figure 1, this technology is with the amplitude of signal and PHASE SEPARATION, respectively amplitude and phase place are amplified again, then merge the process that reverts to original signal.Realize EER specification requirement amplitude branch road and phase branches have good synchronously, synchronous error (being synchro measure) how accurately to measure two branch roads is a great problem of pendulum in face of ours.Existing technical scheme generally is before power amplifier dispatches from the factory, and manually adjusts.Promptly import certain fixing test signal, Yi Bian adjust synchronization delayed time, Yi Bian observe the frequency spectrum of output signal, when signal spectrum was in optimum state, the synchronization delayed time of this moment just was determined.But there is following major defect in this technology:
1, artificial observation causes synchronization accuracy not guarantee, will directly have influence on the output-index of EER power amplifier;
2, can not be in full accord because of device, the circuit of every circuit board, make batch process to carry out, can only all carry out the first-order error test at each piece circuit version, this will cause production cost to rise;
3,, make that the channel characteristic of EER system may time to time change owing to reasons such as device agings.Like this, accumulate over a long period, the output performance index (as Adjacent Channel Leakage Ratio) of power amplifier will run down, and has to the most at last recalibrate, and this has increased the maintenance cost of system to a certain extent.
Summary of the invention
The purpose of this invention is to provide a cover unique and effective method for synchronously measuring and a measurement mechanism, be used to solve this synchro measure problem.
For this reason, the present invention adopts following technical scheme:
A kind of envelope is eliminated and the synchronous error method of measurement of recovering the EER digital power amplifier, may further comprise the steps:
A, at the input of amplitude and phase branches input test signal A+cos (ω t) and sin (ω t)+jcos (ω t) respectively, wherein A is a positive constant, ω is the frequency of test signal;
The T_delay1 and T_delay2 time of delay of b, adjusting range branch road and phase branches makes the output signal TestOutput minimum of feedback test circuit, and described feedback test circuit receives the signal of non-linear power amplifier output;
C, getting output signal TestOutput output minimum time of delay constantly T_delay1 and T_delay2, and do poorly, is synchronous error with this difference.
Described step b is that the output signal value is zero.
Described step a-c finishes in the process of power amplifier output by beginning after amplitude and the PHASE SEPARATION.
A kind of envelope is eliminated and the synchronous error measurement mechanism that recovers the EER digital power amplifier, comprises the envelope detector of reception amplitude test signal and the amplitude limiter of receiving phase test signal, also comprises:
First time delay module receives the amplitude test signal that envelope detector is imported, and carries out delay process;
Modulator receives the amplitude test signal after first time delay module is handled, and is sent to non-linear power amplifier after the modulation treatment;
Second time delay module receives the phase test signal that amplitude limiter is imported, and carries out delay process;
Local oscillator is used to provide local oscillation signal;
Frequency converter receives the phase test signal after second time delay module is handled, and utilizes local oscillation signal to carry out being sent to non-linear power amplifier after the frequency-conversion processing;
Non-linear power amplifier, to the amplitude test signal that receives and the phase test signal merges and power amplification after export;
The feedback test circuit receives the test signal of non-linear power amplifier output, with after itself and the local oscillation signal Frequency mixing processing, obtains output signal TestOutput.
Described feedback test circuit, comprise frequency mixer and the low pass filter that links to each other with frequency mixer, the test signal of described non-linear power amplifier output and local oscillation signal carry out low-pass filtering by low pass filter after the frequency mixer Frequency mixing processing, obtain output signal TestOutput.
With measurement mechanism of the present invention and method of measurement, the synchronous error precision that obtains is very high, method of testing more of the prior art in realization is much simple, can not bring too much influence to the power amplifier cost, the interference of effectively having avoided a lot of human factors to cause simultaneously in measuring process.
Description of drawings
Fig. 1 is an EER know-why schematic diagram;
Fig. 2 is the measurement mechanism schematic diagram that the present invention adopts;
Fig. 3 is a test flow chart of the present invention;
Embodiment
Below in conjunction with Figure of description the specific embodiment of the present invention is described.
As shown in Figure 2, it is the synchronous error measurement mechanism structural representation of EER digital power amplifier of the present invention, as we can see from the figure, its testing apparatus with prior art is identical substantially, comprise the envelope detector (envelop detector) and the amplitude limiter (limiter) that are positioned at signal receiving end, respectively the range signal and the phase signal of acceptance test signal; The present invention has increased testing time deferred mount 2 on the basis of existing technology, comprising:
First time delay module (delay1) that handle the time of delay of amplitude branch road links to each other with envelop detector, is used for the time delay T_delay1 of adjusting range branch road; Modulator receives the amplitude test signal after the first time delay module time delay T_delay1 handles, and carries out modulation treatment, as carries out pulse width modulation or deltasigma modulation etc., and the amplitude test signal after the modulation treatment is sent to non-linear power amplifier;
Handle time of delay of phase branches second time delay module (delay2), link to each other with amplitude limiter, receive the phase test signal that amplitude limiter is imported, be used to adjust the time delay T_delay2 of phase branches; Frequency converter receives the phase test signal after the second time delay module time delay T_delay2 handles, and the local oscillation signal that utilizes local oscillator to transmit carries out frequency-conversion processing, such as be sent to non-linear power amplifier after the frequency-conversion processing of if-to-rf.
First, second time delay module wherein is made of a part of circuit, realizes time delay such as adopting clock to trigger.
The present invention also comprises a feedback test circuit 1 of being made up of frequency mixer and low pass filter, links to each other with local oscillator, is used to receive the test signal of the output of non-linear power amplifier.The test signal of the output of described non-linear power amplifier and local oscillation signal carry out low-pass filtering by low pass filter after the frequency mixer Frequency mixing processing, obtain output signal TestOutput.
As shown in Figure 3, be test flow chart of the present invention, because error is to be separated with phase signal after by different amplification paths by amplitude, and the delay difference on every road causes, so measuring object is defined as exporting to power amplifier by beginning after amplitude and the PHASE SEPARATION.
Corresponding with measurement mechanism of the present invention, method of testing of the present invention may further comprise the steps:
A, at the input of amplitude and phase branches input test signal 4+cos (ω t) and sin (ω t)+jcos (ω t) respectively, wherein A is a positive constant, ω is the frequency of test signal;
Input difference input test signal A+cos (ω t) and sin (ω t)+jcos (ω t) in amplitude and phase branches.Wherein A is a positive constant, and the input signal perseverance that is used to guarantee the amplitude branch road is greater than zero and meet certain peak-to-average ratio requirement; ω is the frequency of test signal; Phase branches guarantees that signal is permanent envelope.
The T_delay1 and T_delay2 time of delay of b, adjusting range branch road and phase branches makes output signal TestOutput minimum;
The signal of amplitude branch road is A+cos (ω t+Delay_Am) through the signal indication that amplifies after postponing, and does not consider amplification coefficient, and is as follows.
The signal of the signal of phase branches after ovennodulation is amplified is:
Re{[sin(ωt+Delay_Ph)+jcos(ωt+Delay_Ph)]*[cos(ω
ct)-jsin(ω
ct)]}
＝sin(ωt+Delay_Ph)*cos(ω
ct)+cos(ωt+Delay_Ph)*sin(ω
ct)
＝sin(ωt+ω
ct+Delay_Ph)
ω wherein
cBe the carrier frequency of phase branches,
Signal after amplitude-phase merges is:
[A+cos(ωt+Delay_Am)]*sin(ωt+ω
ct+Delay_Ph)
＝Asin(ωt+ω
ct+Delay_Ph)
+sin(ωt+ω
ct+Delay_Ph)*cos(ωt+Delay_Am)
＝Asin(ωt+ω
ct+Dely_Ph)
+0.5*sin(2ωt+ω
ct+Delay_Ph+Delay_Am)
+0.5*sin(ω
ct+Delay_Ph-Dely_Am)
As seen the phase information of the carrier signal of input mixer is exactly the delay error of amplitude branch road and phase branches.Be the method for extracting phase place below.
This signal and local oscillation signal multiplied each other:
cos(ω
ct+Delay_c)*[Asin(ωt+ω
ct+Delay_Ph)
+0.5*sin(2ωt+ω
ct+Delay_Ph+Delay_Am)
+0.5*sin(ω
ct+Delay_Ph-Delay_Am)]
Wherein delay_c is the phase place of reception carrier.Filtering ω and the signal that obtains with the signal component of upper frequency are as follows, do not consider coefficient:
sin(Delay_Ph-Delay_Am-Delay_c)。
C, adjustment T_delay1 time of delay and T_delay2, and get TestOutput minimum time of delay constantly T_delay1 and T_delay2, be T=T_delay1-T_delay2, with T synchronous error.
When transmitting and receiving carrier synchronization, Delay_c=0, end product are sin (Delay_Ph-Delay_Am), when error hour, can be reduced to Delay_Ph-Delay_Am and error signal is directly proportional.
In an embodiment of the present invention, get wc=2*pi*100MHz, w=100KHz and 300KHz, the measure error that draws is respectively 334.6ns and 326.4ns.
This shows, to same object, use different frequency test signals, the result who obtains can be different.Its reason is that the amplitude branch road exists a low pass filter, and the frequency plot characteristic of this filter is non-linear.Experimental result illustrates that on the one hand this method of testing is correct, illustrates that on the other hand the present invention can accurately obtain synchronous error, is helpful to the performance that improves power amplifier.
With measurement mechanism of the present invention and method of measurement, the synchronous error precision that obtains is very high, method of testing more of the prior art in realization is much simple, can not bring too much influence to the power amplifier cost, the interference of effectively having avoided a lot of human factors to cause simultaneously in measuring process.
The above; only for the preferable embodiment of the present invention, but protection scope of the present invention is not limited thereto, and anyly is familiar with those skilled in the art in the technical scope that the present invention discloses; the variation that can expect easily or replacement all should be encompassed within protection scope of the present invention.Therefore, protection scope of the present invention should be as the criterion with the protection range of claims.
Claims (5)
1, a kind of envelope is eliminated and the synchronous error method of measurement of recovering the EER digital power amplifier, it is characterized in that may further comprise the steps:
A, at the input of amplitude and phase branches input test signal A+cos (ω t) and sin (ω t)+jcos (ω t) respectively, wherein A is a positive constant, ω is the frequency of test signal;
The T_delay1 and T_delay2 time of delay of b, adjusting range branch road and phase branches makes the output signal TestOutput minimum of feedback test circuit, and described feedback test circuit receives the signal of non-linear power amplifier output;
C, getting output signal TestOutput output minimum time of delay constantly T_delay1 and T_delay2, and do poorly, is synchronous error with this difference.
2, the synchronous error method of measurement of EER digital power amplifier as claimed in claim 1 is characterized in that described step b, and the output signal value is zero.
3, the synchronous error method of measurement of EER digital power amplifier as claimed in claim 1 is characterized in that described step a-c finishes by beginning after amplitude and the PHASE SEPARATION in the process of power amplifier output.
4, a kind of envelope is eliminated and the synchronous error measurement mechanism that recovers the EER digital power amplifier, comprises the envelope detector of reception amplitude test signal and the amplitude limiter of receiving phase test signal, it is characterized in that also comprising:
First time delay module receives the amplitude test signal that envelope detector is imported, and carries out delay process;
Modulator receives the amplitude test signal after first time delay module is handled, and is sent to non-linear power amplifier after the modulation treatment;
Second time delay module receives the phase test signal that amplitude limiter is imported, and carries out delay process;
Local oscillator is used to provide local oscillation signal;
Frequency converter receives the phase test signal after second time delay module is handled, and utilizes local oscillation signal to carry out being sent to non-linear power amplifier after the frequency-conversion processing;
Non-linear power amplifier, to the amplitude test signal that receives and the phase test signal merges and power amplification after export;
The feedback test circuit receives the test signal of non-linear power amplifier output, with after itself and the local oscillation signal Frequency mixing processing, obtains output signal TestOutput.
5, the synchronous error measurement mechanism of EER digital power amplifier as claimed in claim 4, it is characterized in that described feedback test circuit, comprise frequency mixer and the low pass filter that links to each other with frequency mixer, the test signal of described non-linear power amplifier output and local oscillation signal are after the frequency mixer Frequency mixing processing, carry out low-pass filtering by low pass filter, obtain output signal TestOutput.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CNB031374476A CN100337484C (en) | 2003-06-20 | 2003-06-20 | Synchronous error measuring method and apparatus with envelope elimination and digital power amplifier restoration |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CNB031374476A CN100337484C (en) | 2003-06-20 | 2003-06-20 | Synchronous error measuring method and apparatus with envelope elimination and digital power amplifier restoration |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| CN1568029A CN1568029A (en) | 2005-01-19 |
| CN100337484C true CN100337484C (en) | 2007-09-12 |
Family
ID=34470412
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| CNB031374476A Expired - Fee Related CN100337484C (en) | 2003-06-20 | 2003-06-20 | Synchronous error measuring method and apparatus with envelope elimination and digital power amplifier restoration |
Country Status (1)
| Country | Link |
|---|---|
| CN (1) | CN100337484C (en) |
Families Citing this family (6)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JP2006333450A (en) * | 2005-04-28 | 2006-12-07 | Matsushita Electric Ind Co Ltd | Polar coordinate modulation circuit, polar coordinate modulation method, integrated circuit, and radio transmission apparatus |
| CN101090382B (en) * | 2006-06-04 | 2012-04-25 | 三星电机株式会社 | Systems, methods, and apparatuses for linear polar transmitters |
| CN101677228B (en) * | 2008-09-16 | 2011-11-09 | 财团法人工业技术研究院 | Power amplifier system, control method and control device thereof |
| US9577771B1 (en) * | 2016-07-25 | 2017-02-21 | Apple Inc. | Radio frequency time skew calibration systems and methods |
| CN112203303B (en) * | 2020-09-30 | 2023-11-14 | 锐迪科创微电子（北京）有限公司 | Delay mismatch calibration method and device and computer readable storage medium |
| CN112203304B (en) * | 2020-09-30 | 2023-11-14 | 锐迪科创微电子（北京）有限公司 | Delay mismatch calibration method and device and computer readable storage medium |
Citations (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN1222787A (en) * | 1997-05-08 | 1999-07-14 | 摩托罗拉公司 | High efficiency power amplifier |
| CN1280423A (en) * | 1999-07-08 | 2001-01-17 | 深圳市华为技术有限公司 | Method and device for controlling power envelope |
| WO2002013397A2 (en) * | 2000-08-09 | 2002-02-14 | Sicom, Inc. | Constrained-envelope transmitter and method therefor |
-
2003
- 2003-06-20 CN CNB031374476A patent/CN100337484C/en not_active Expired - Fee Related
Patent Citations (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN1222787A (en) * | 1997-05-08 | 1999-07-14 | 摩托罗拉公司 | High efficiency power amplifier |
| CN1280423A (en) * | 1999-07-08 | 2001-01-17 | 深圳市华为技术有限公司 | Method and device for controlling power envelope |
| WO2002013397A2 (en) * | 2000-08-09 | 2002-02-14 | Sicom, Inc. | Constrained-envelope transmitter and method therefor |
Also Published As
| Publication number | Publication date |
|---|---|
| CN1568029A (en) | 2005-01-19 |
Similar Documents
| Publication | Publication Date | Title |
|---|---|---|
| CN1218474C (en) | Power modulation systems and methods that separately amplify low and high frequency portions of an amplitude waveform | |
| CN1642025A (en) | Timing adjustment method for wireless communication apparatus | |
| CN1411147A (en) | Precorrective linearized power amplifying system using digital IF technique | |
| CN101055299A (en) | Impact load electric energy metering method | |
| CN1714502A (en) | Pulse width-modulated noise shaper | |
| CN100337484C (en) | Synchronous error measuring method and apparatus with envelope elimination and digital power amplifier restoration | |
| CN1701521A (en) | Transmission device and adjustment method thereof | |
| CN1929296A (en) | Chopper amplifier circuit and semiconductor device | |
| CN1208922C (en) | Timed inner-inserting device for digital demodulator | |
| CN104796144B (en) | The single channel synchronous acquisition device and method of multiple signals bipolarity quadrature square wave modulation | |
| CN1430390A (en) | Device and method for compensating error of analog integral modulator | |
| CN1722720A (en) | Detect the equipment and the method for the time synchronized of frame and code element | |
| CN1154244C (en) | Quadrature-free RF receiver for directly receiving angle modulated signal | |
| CN1152494C (en) | Analog orthogonal modulation unbalance compensating method | |
| CN1146112A (en) | Phase detecting method and phase tracking loop circuit of digital vestigial sideband modulation communication device | |
| CN1822581A (en) | Interpose module,interposer and its method | |
| CN1627087A (en) | Electric power meter | |
| CN1917380A (en) | Method for eliminating dc bias for receiver and signal process module | |
| CN1516946A (en) | Frequency correction with symmetrical phase adjustment in each OFDM symbol | |
| CN1521976A (en) | Data receiving method based on clock signal and apparatus thereof | |
| ATE441968T1 (en) | DEVICE FOR REDUCING IF SIGNALS TO THE BASEBAND, AND METHOD THEREOF | |
| CN1105920C (en) | Passive-element testing circuit for printed circuit | |
| CN114063323A (en) | Method for automatically controlling optimal bias point of electro-optical modulator | |
| CN106452578A (en) | Method of restoring distorted signal in visible light communication system | |
| CN1531195A (en) | Enlarger controlling system for counting improvement of digital controlling signal resolution ratio |
Legal Events
| Date | Code | Title | Description |
|---|---|---|---|
| C06 | Publication | ||
| PB01 | Publication | ||
| C10 | Entry into substantive examination | ||
| SE01 | Entry into force of request for substantive examination | ||
| C14 | Grant of patent or utility model | ||
| GR01 | Patent grant | ||
| CF01 | Termination of patent right due to non-payment of annual fee | ||
| CF01 | Termination of patent right due to non-payment of annual fee |
Granted publication date: 20070912 Termination date: 20200620 |