CH707285A2 - Electronic timepiece movement, has time base including inhibition circuit that provides inhibit signal to input of frequency divider circuit, to remove number of clock pulses by inhibition period divided into sub-periods - Google Patents

Abstract

The movement (2) has a time base (4) including a timer circuit (8) for supplying clock pulses, and a frequency divider circuit (10) for receiving the pulses at an input. An inhibition circuit (12) provides an inhibit signal (S3) to another input of the divider circuit, to remove a first number of clock pulses by an inhibition period (P) divided into sub-periods. The inhibiting circuit suppresses a second number of clock pulses corresponding to the result of division of an integer by the number of sub-periods, and a third number of clock pulses corresponding to the remainder of the division. An independent claim is also included for a method for adjusting a time base.

Description

Technical area

The present invention relates to the field of electronic watch movements, in particular high precision electronic movements undergoing precision tests for obtaining a chronometer certificate issued by an official body (in Switzerland: The COSC). More generally, the invention relates to time bases comprising a crystal oscillator and set by inhibition of clock pulses and in particular a method of setting such a time base.

Technological background

[0002] Electronic clock movements generally comprise a time base providing a time signal and a display module receiving this time signal, which is formed of timing pulses. The time base comprises a clock circuit and a frequency divider circuit. The clock circuit is formed by a crystal oscillator and provides a clock signal to the frequency divider circuit, which clock signal has a determined clock frequency. The frequency divider circuit is formed by a divider chain (usually two) and outputs a time signal formed of clock pulses generated at a unit frequency.

As it is not possible in an industrial production to produce oscillators all having a reference frequency F0 which would make it possible to obtain timing pulses with a reference unit frequency (in particular 1 Hz), it is intended to producing quartz oscillators with frequencies F distributed in a certain frequency range greater than the reference frequency F0. If we consider a basic period P0 (especially one minute), the number of clock pulses at the reference frequency is equal to M0 = P0⋅F0 (F0 is an integer and it is assumed that P0 is also a number whole of seconds). The quartz oscillators are selected so that the number of pulses X0 (real number) that they generate in the period P0 are between M0 and M0 + N0max (that is, M0 <X0 <M0 + N0max ). In order to better adjust the time signal generated by the time base, it is known to associate with this timebase an inhibition circuit, which provides at the input of the frequency divider circuit an inhibition signal which acts in such a way as to deleting a number N0 of clock pulses per inhibition period P0 to adjust on each inhibition period P0 the number of clock pulses activating the frequency divider circuit. The number N0 is a positive integer. It is determined for each clock circuit that the frequency divider circuit is activated over the period P0 by a number of times X0-N0 which rounds to the integer M0 (i.e. M0-1 / 2 <X0-N0 <= M0 + 1/2). Thus, the precision obtained for the clock movement is equal to (1/2) / M0 = 1 / 2M0.

To increase the accuracy of the watch movement, it is possible to increase the inhibition period P by a factor Y relative to P0, ie P = Y⋅P0 with Y> 1. Over this period P, the number of clock pulses M at the reference frequency is equal to Y⋅M0 (that is to say M = Y⋅M0) while the number X of clock pulses at the frequency F generated by a given crystal oscillator is equal to Y⋅X0 (that is, X = Y⋅X0). It will be noted that, for the quartz oscillators selected according to the criterion mentioned above, the maximum number of clock pulses Nmax to be inhibited over the period P is equal to Y-N0max (that is to say Nmax = Y⋅ N0max). Again the number N of clock pulses to be inhibited is determined for each oscillator by the mathematical relationship: M-1/2 <X-N <= M + 1/2. Thus the precision obtained by the inhibition is therefore equal to (1/2) / M = (1/2) / (Y⋅M0) = (1 / Y) ⋅ (1 / 2M0). It is therefore found that the precision over a muting period increases by a factor Y when the inhibition period is increased by this factor Y. Note that this accuracy corresponds to the average accuracy of the time base which gives the drift of this time base over time.

However, the increase of the inhibition period from P0 to P raises a problem explained below since the maximum absolute error EAmax <AA> between two measurements of time provided by the time base increases proportionally. to Y since the inhibition of the N clock pulses per inhibition period is carried out in block at time intervals corresponding to the inhibition period. The classic definition of inhibition period follows from this way of proceeding. So we have:

EAmax <AA> (P) = Nmax / F = Y⋅N0max / F = Y⋅EAmax (P0)

This is shown in Figure 2 for a period of inhibition P of eight minutes (8 min). Let P0 equal to one minute (1 min), the maximum absolute error EAmax <AA> is proportional to the inhibition period and this maximum absolute error is eight times greater than the corresponding error for a basic inhibition period P0. The instantaneous absolute error does not pose a problem for the movement of the watch movement and it becomes negligible for long periods, but it poses a significant problem during precision tests of the time base or the watch movement comprising such a base of time. Thus, when increasing the accuracy by increasing the inhibition period, it can not be verified over a short period of time so that it is not possible to obtain a very accurate chronometer certificate by a certification body , including the COSC in Switzerland. The tests are for example carried out over periods of approximately 24 hours and this asynchronously with respect to the inhibition periods P. In other words, the test period is not determined so as to be equal to a multiple of the inhibition period so that it is possible to measure almost the maximum absolute error over this test period. The resulting relative error is relatively large since the test period is relatively short. The measurement of the real accuracy of the watch movement can not therefore be correctly established by a certification body.

Summary of the invention

The present invention aims to solve the problem of the aforementioned prior art, namely to allow an increase in the accuracy of an electronic watch movement while ensuring that it successfully undergo certification tests establishing the great precision of this watch movement.

The present invention relates to an electronic watch movement comprising a time base arranged to provide a time signal formed of timing pulses generated at a unit frequency, this time base comprising: A clock circuit providing clock pulses with a determined clock frequency; - a frequency divider circuit receiving at a first input the clock pulses and outputting the time signal; An inhibition circuit supplying an inhibition signal to a second input of the frequency divider circuit, this inhibition signal acting to suppress a first number N of clock pulses per inhibition period P to regulate on each inhibition period the number of clock pulses activating the frequency divider circuit so that said unit frequency approaches closer to a reference unit frequency.

According to industrial practice, the clock frequency of this electronic clock movement is provided in a certain frequency range greater than a reference frequency which would make it possible to obtain a reference unit frequency at the output of the frequency divider circuit. the absence of inhibition.

According to the invention, each inhibition period is divided into a plurality K of sub-periods and the inhibition circuit is arranged to delete in each sub-period a second number of clock pulses corresponding to the result. of the entire division of the first number by the number of sub-periods INT [N / K] and, in addition, in each inhibition period a third number of clock pulses corresponding to the remainder of said whole division (N modulo K).

The invention also relates to a method of setting a time base corresponding to the algorithm implemented in the watch movement according to the invention.

With the characteristics of the invention, it is possible to increase the precision of the watch movement by increasing the inhibition period P and to reduce the absolute error so that it corresponds substantially to that of a period of time. shorter inhibition of a K factor.

Brief description of the drawings

The invention will be described hereinafter in detail with the aid of the accompanying drawings, given by way of non-limiting examples, in which: <tb> Fig. 1 <SEP> schematically represents functional blocks of the electronic watch movement according to the invention; <tb> Fig. 2 <SEP> already described, is a graph giving the absolute temporal error over time for a movement of the prior art with an inhibition period of eight minutes (8 min); <tb> Fig. 3 <SEP> is a graph similar to that of FIG. 2 and giving the absolute temporal error over time for an electronic watch movement according to the invention, also with an inhibition period of eight minutes (8 min); and <tb> Fig. 4 <SEP> shows a variant of the inhibition method according to FIG.

Detailed description of the invention

In Figure 1 is schematically shown an electronic clock movement 2 comprising a time base 4 arranged to provide a time signal S1 formed of timing pulses generated at a unit frequency F1. The time base includes: A clock circuit 8 which supplies a clock signal S2 formed of clock pulses generated at a determined clock frequency F; A frequency divider circuit 10 which receives at a first input the clock pulses of the clock signal S2 and which outputs the time signal S1; An inhibition circuit 12 which supplies an inhibition signal S3 to a second input of the frequency divider circuit 10.

To synchronize the inhibition circuit 12 with the clock circuit and also for managing the periodic sending of the inhibition signal, this inhibition circuit is connected to the frequency divider circuit 10 which provides it with a control signal S4.

As already explained above, the clock frequency F is provided in a certain frequency range greater than a reference frequency F0 which would make it possible, in the absence of inhibition, to obtain an output reference unit frequency. of the frequency divider circuit. The reference unit frequency is usually 1 Hz (period of 1 s).

According to the invention, the adjustment method implemented in the watch movement according to the invention comprises the following steps: - select an inhibition period P greater than one minute; A first number N of clock pulses to be suppressed by inhibition period P to set on each inhibition period P the number of clock pulses activating the frequency divider circuit so that the unit frequency F1 approaches closer to the aforementioned reference unit frequency; Selecting a plurality K of sub-periods P1 for each inhibition period P; In each sub-period P1, deleting a second number N1 of clock pulses corresponding to the result of the entire division of the first number N of clock pulses by the number K of sub-periods (N1 = INT [N / K]), and In addition to the suppression of the preceding step, in each inhibition period P, a third number N2 of clock pulses corresponding to the remainder of the entire division of the first number N of clock pulses is suppressed by the number K of sub-periods (N2 = N modulo K).

Thus, on each inhibition period P, it removes the first number N to obtain the maximum accuracy for this period of inhibition. Indeed, N = N1 + N2.

Figure 3 shows the benefit of the timing control method 4 according to the present invention. In the prior art, it is usual to provide an inhibition period P0 equal to one minute (P0 = 1 min). To increase the accuracy, it is possible to take a longer inhibition period P, for example eight minutes (P = 8 min), as in the variant of the prior art shown in FIG. 2. Taking the specific case where the setting of the time base by inhibition of clock pulses over the period P makes it possible to obtain exactly the reference unit frequency, the instantaneous absolute error EA <AA> varies with a given slope. by (N / P) / F, where N is the number of clock pulses to be removed per period P and F is the clock frequency. Thus, in the case of the prior art, the maximum absolute error EAmax <AA> over a period P (between the beginning and the end of the period) is equal to N / F. In the case where N = Nmax, one arrives at a maximum absolute error equal to Nmax / F over the period P. In the specific case mentioned above, it will be noted that N = Y⋅N0 where N0 is the number of pulses to be suppressed on a base period P0 = P / Y. In general, Nmax = Y⋅N0max.

Figure 3 gives the absolute error EA with the adjustment method according to the invention for a period of inhibition P corresponding to that of the case of the prior art of Figure 2. Taking K = 8 and therefore a sub-period P1 = 1 min, the maximum absolute error EAmax between any two instants of a period P is greatly reduced. It is substantially given by the following equality and inequality: EAmax = (INT [N / K] + N modulo K) / F EAmax <(INT [N / K] + K) / F

Note that in Figure 3, N modulo K is noted N% K. P1 is chosen as an example equal to the basic period P0, but it is a particular case that is in no way limiting. We can take K = 4 and P1 = 2 min for a period P = 8 minutes, or K = 16 and P1 = 30 seconds (30 s).

In the specific case mentioned above, EAmax = INT [N / K] = N0 and EAmax corresponds to the maximum absolute error between any two instants in the course of time. To illustrate the general case, take a numerical example, P = 8 min, K = 8 and N = 245. Thus, in the case of the prior art (FIG. 2), the maximum absolute error EAmax <AA> = 245 / F. In the case of the present invention, the sub-period P1 = 1 min, INT [N / K] = 30 and N modulo K = 5. Thus the maximum absolute error EAmax = (30 + 5) / F = 35 / F. According to the inequality given above EAmax <(INT [N / K] + K) / F = 38 / F. It can thus be seen that in the worst case, the maximum absolute error is reduced by at least a factor of six.

In FIG. 3, the correction of the remainder of the entire division over the period P (N modulo K, denoted N% K) is carried out inside a single sub-period P1 (sub-periods No 5 , 13, ... 5 + nK, ...) in each inhibition period P, while the correction of INT [N / K] clock pulses is performed at the end or at the beginning of each subperiod P1. In FIG. 4 is shown in more detail an implementation variant of the adjustment method according to the invention where the correction of the remainder of the entire division N modulo K over the period P is performed together with a correction of INT [N / K] clock pulses at the end or at the beginning of a sub-period P1. In the variant of Figure 4, Δt1 = (INT [N / K]) / F and Δt2 = (N modulo K) / F. We have taken an example where Δt2 is non-zero and approximately equal to one sixth of Δt1 as in the numerical example given above. As the correction Δt1 in each sub-period P1 is relatively inaccurate since N modulo K is non-zero, it is found that there is a drift during each inhibition period P defined by the dashed lines. This drift is compensated at the end of the inhibition period P so that the average frequency of the time base is identical to that obtained in an embodiment of the prior art with the same inhibition period P. As mentioned above, the maximum absolute error EAmax = Δt1 + Δt2.

Preferably, since one generally works with binary registers in a digital circuit, one selects K = 2 <n>, n being an integer greater than one (n> 1). The number N has a maximum Nmax given by the manufacturing tolerance of quartz oscillators. N is an integer registered in binary form in a memory register. For example Nmax = 1023. As 2 <10> = 1024, the memory register then comprises 10 bits. In general, take 2 <n> <Nmax <2 <m>, m being by definition greater than n in the context of the invention (m> n). Thus, the two numbers of pulses to be eliminated which must be determined for the implementation of the method of setting the time base, INT [N / K] and N modulo K, are easily obtained. Indeed, on the one hand, INT [N / K] corresponds to the binary number obtained by taking the first m-n bits of the memory register, which amounts to shifting the binary number in the memory register from m-n bits to the right. On the other hand, N modulo K is given by the last n bits of the memory register.

Claims (8)

An electronic watch movement (2) comprising a time base (4) arranged to provide a time signal (51) formed of timing pulses generated at a unit frequency (F1), said time base comprising: - a clock circuit (8) providing clock pulses with a determined clock frequency (F); - a frequency divider circuit (10) receiving at a first input said clock pulses and outputting said time signal; An inhibition circuit (12) providing an inhibition signal (S3) to a second input of said frequency divider circuit, said inhibition signal acting to suppress a first number N of clock pulses per period; inhibiting circuit (P) for setting on each inhibition period the number of clock pulses activating said frequency dividing circuit such that said unit frequency approaches closest to a reference unit frequency; said clock frequency being provided in a certain frequency range greater than a reference frequency which would make it possible, in the absence of inhibition, to obtain said reference unit frequency at the output of the frequency divider circuit; characterized in that each inhibition period is divided into a plurality K of sub-periods (P1), and in that the inhibition circuit is arranged to suppress in each sub-period a second number N1 of pulses of clock corresponding to the result of the integer division of the first number by the number of sub-periods (N1 = INT [N / K]) and, in addition, in each inhibition period a third number N2 of equal clock pulses to the rest of said whole division (N2 = N modulo K). 2. Electronic watch movement according to claim 1, characterized in that the number K of sub-periods is equal to an integer power of two, ie K = 2n, n being an integer greater than zero (n> 0) and the number K being less than a maximum number of clock pulses to be suppressed by inhibition period (P). 3. Electronic watch movement according to claim 1 or 2, characterized in that the integer n is greater than two (n> 2). 4. Electronic watch movement according to any one of claims 1 to 3, characterized in that the inhibition period (P) is greater than or equal to eight minutes (P> = 8 min). A method of setting a time base (4) arranged to provide a time signal (S1) formed of timing pulses generated at a unit frequency (F1), said time base comprising: - a clock circuit (8) providing clock pulses with a determined clock frequency (F); - a frequency divider circuit (10) receiving at a first input said clock pulses and outputting said time signal; An inhibition circuit (12) supplying an inhibition signal (S3) to a second input of said frequency divider circuit; said clock frequency being provided in a certain frequency range higher than a reference frequency which would make it possible, in the absence of inhibition, to obtain a reference unit frequency at the output of the frequency divider circuit; this adjustment method comprising the following steps: - select an inhibition period (P) greater than one minute; determining a first number N of clock pulses to be suppressed per inhibition period (P) in order to set on each inhibition period the number of clock pulses activating said frequency divider circuit so that said unit frequency approaches at best the said reference unit frequency; Selecting a plurality K of sub-periods (P1) for each inhibition period (P); In each sub-period (P1), deleting a second number N1 of clock pulses corresponding to the result of the integer division of the first number by the number of sub-periods (N1 = INT [N / K]), and In addition to the suppression of the preceding step, in each inhibition period (P), a third number N2 of clock pulses corresponding to the remainder of said entire division (N2 = N modulo K) is suppressed. 6. An adjustment method according to claim 5, characterized in that the number K of sub-periods is equal to an integer power of two, ie K = 2 <n>, where n is an integer greater than zero (n> 0 ) and the number K being less than a maximum number of clock pulses to be suppressed by inhibition period (P). 7. Adjustment method according to claim 5 or 6, characterized in that the integer n is greater than two (n> 2). 8. Adjustment method according to any one of claims 5 to 7, characterized in that the inhibition period (P) is greater than or equal to eight minutes (P> = 8 min).