CH686328A5 - Reversible non-decimating / decimating adaptive equalization filter. - Google Patents

Description

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A digital decimation filter is known from European patent application EP-A 0 305 708, the multiplexer contained therein is operated at the sampling rate of the signals fed to it, while half of the signal paths connected to its outputs and the partial circuits of the filter connected to them Sampling rate of the input signal are operated.

Furthermore, from the dissertation of Tobias Gebhard Noll at the Ruhr University Bochum, 1989, entitled "Architecture and circuit design of a digital adaptive equalizer for digital radio relay with locally systolic carry-save arrays in CMOS technology", page 50, a block diagram of a digital zero-forcing equalizer is known, in which filter coefficients from coefficient multipliers of a filter circuit can be adjusted by partial correlators of a coefficient adjustment circuit as a function of an error signal and a decision output signal as a reference signal, in order to approximate an inverse filter at a time to form changing channel.

The invention has for its object to provide a switchable non-decimating / decimating adaptive equalizer filter, in which the wiring between a coefficient adjustment circuit and a filter circuit with variable coefficients with regard to switching between non-decimating and decimating operating modes is possible for both operating modes and only the smallest possible number of switches or change-over switches is required and in which the smallest possible chip area is required and the lowest possible power loss occurs.

The object is achieved by the features specified in claim 1.

Claim 2 is directed to a preferred embodiment of the invention.

The invention is explained below with reference to the drawing. It shows

1 is a circuit diagram of an equalizer filter according to the invention with a serial-in / parallel-out structure and

2 shows an equalizer filter according to the invention with a parallel in / serial out structure.

1 shows a switchable non-decimating / decimating adaptive equalizer filter with N = 11 coefficients, which consists of a switchable non-decimating / decimating filter with variable coefficients NDF / DF and a coefficient adjustment circuit CORR, the filter NDF / DF consists of a partial filter TFI and a further partial filter TF2, both of which have a serial-in / parallel-out structure. The first sub-filter TFI has a series connection of delay elements 1 ... 5 with the respective delay time T, where l / T corresponds to the symbol rate fs, six coefficient multipliers 31 ... 36 for variable coefficients and five adders 53 ... 57 Partial filter TF2 has a series connection of four delay elements 6 ... 9,

five coefficient multipliers 37 ... 41 and four adders 58 ... 61. The input signal of the filter TF1 is multiplied in the coefficient multiplier 31 by the respective coefficient and fed to the series circuit comprising the five delay elements 1 ... 5. The signals of the outputs of the delay elements 1 ... 5 are multiplied by the respective coefficients in the coefficient multipliers 32 ... 36 and the result is fed to a first input of a respective adder of the adders 53 ... 57. The second input of the adder 53 is connected to the output of the coefficient multiplier 31 and the further second inputs of the adders 55 ... 57 are each connected in series to an output of a respective adder and the output of the adder 57 is connected to an input of a Adders 62 connected. In the case of the partial filter TF2, the input signal to the coefficient multiplier 37 and the output signals of the delay elements 6 ... 9 to the coefficient multipliers 38 ... 41 can be fed individually one after the other. A first input of the adder 58 is connected to the output of the coefficient multiplier 37 and the first inputs of the further adders 59 ... 61 are each connected to an output of a preceding adder and the output of the adder 61 is to the second input of the adder 62 connected, the output of which represents the filter output y. The second inputs of the adders 58 ... 61 are each connected in sequence to an output of the coefficient multipliers 38 ... 41. The filter NDF / DF has a demultiplexer DMUX1, the input of which carries the filter input signal x, the first output of which is connected to the input of the filter TF1 and the second output of which is connected to the input of a changeover switch 52. The demultiplexer DMUX1 can be switched at the symbol rate fs, that is, each of the two switching states of the demultiplexer is assumed for the time 1/2 * fs, and its two outputs can be bridged by a switch S1.

In non-decimating operation, the filter or sampling frequency used corresponds to the symbol rate fs (baud rate). This scanning violates the scanning theorem in all practical applications, which in turn results in high demands on the scanning phase used. In decimating operation, the sampling frequency is usually chosen to be twice the symbol rate 2fs for reasons of simplified synchronization and thus corresponds to the sampling theorem. After the equalization filtering, the sampling rate can usually be reduced to the symbol rate and the filter arrangement can thus be interpreted as a decimation filter. The disadvantage here lies in certain undesirable degrees of freedom when setting the filter coefficients. The outputs of the demultiplexer DMUX1 are bridged in the non-decimating mode by the switch SI, that is to say that the demultiplexer DMUX1 can also be switched over as in decimating mode and does not have to be switched off, and the input of the switch 52 is connected via a pre-delay circuit VI the input of the sub-filter

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TF2 connected and the coefficient multipliers 31 ... 36 are supplied in parallel with the coefficients C-5 ... Co and the coefficient multipliers 37 ... 41 of the sub-filter TF2 are supplied with the coefficients C1 ... C5 in sequence. In decimating mode, the switch S1 is open, the demultiplexer DMUX1 is thus effective, and the input of the switch 52 is connected to the input of the sub-filter TF2 via a pre-delay circuit V2, and the coefficient multipliers 31 ... 36 of the sub-filter TFI are sequentially connected in parallel with the Coefficients C-5/2, C-3/2, .... C5 / 2 and the coefficient multipliers 37 ... 41 of the sub-filter TF2 with the coefficients C4 / 2, C-2/2. ... C4 / 2 supplied.

The coefficient adjustment circuit CORR consists of N = 11 partial correlators 80 ... 90, a chain of delay elements 10 ... 14, a further chain of delay elements 15 ... 18, a demultiplexer DMUX2, changeover switches S3 and S4, a switch S5 and Pre-delay elements V3 ... V6. An error signal e can be fed via the changeover switch 53 either via the pre-delay element V3 or via the pre-delay element V4 to all of the first inputs of the partial correlators 80 ... 90. A reference signal W can be fed to the input of the demultiplexer DMUX2, which can be switched over at the symbol rate fs. The output signal of a decision circuit, which is supplied with the filter output signal 7, is used as the reference signal W in the so-called zero-forcing method, and the filter input signal x is used for this in the so-called minimum-mean-squares error method. A first output of the Démultiplexera DMUX2 is connected to the input of the chain of delay elements 10 ... 14, the second output of the Démultiplexera DMUX2 is via the switch S4 either via the pre-delay circuit V5 or via the pre-delay circuit V6 with the input of the chain of delay elements 15 ... 18 connectable and the two outputs of the Démultiplexera DMUX2 are bridged by switch S5 in non-decimating mode and not bridged in decimating mode. The second input of the partial correlator 80 is connected to the input of the chain of delay elements 10 ... 14 and the outputs of the delay elements 10 ... 14 are connected in series to a second input of the partial correlators 82, 84 ... 90. The input of the chain of delay elements 15 ... 18 is connected to the second input of the partial correlator 81 and the outputs of the delay elements 15 ...

18 are each connected in series to one of the partial correlators 83, 85 ... 89. The partial correlator 80 is carried out in detail by way of example, the two inputs of the partial correlator 80 representing the inputs of a multiplier M which is followed by an inverting amplifier A, an adder 63 and a delay element 19, the output of the delay element

19 represents the output of the partial correlator and this is fed back to the second input of the adder 63, so that a digital integrator results.

If, for example, the error signal e consists only of a sign bit, as described in Tobias Noll's dissertation, each bit of the reference signal w can be combined with the signal e in an EXOR circuit instead of the multiplier M. The outputs of the partial correlators 80 ... 90 provide the coefficients C-5 or C-5/2, Ci or C-4/2, C4 or C-3/2, C2 or C-2 in sequence / 2, C-3 or C-1/2, C3 or Co, C-2 or C1 / 2, C4 or C2 / 2, C-1 or C3 / 2, C5 or C4 / 2 and Co or C5 / 2. This means that both in non-decimating and in decimating operation there are the same connections between partial correlators and coefficient multipliers and no further switches or changeover switches are required.

2 shows a further equalizer filter according to the invention, in which a switchable non-decimating / decimating filter NDF / DF is used instead of the switchable non-decimating / decimating filter NDF / DF, which has a partial filter TF1 'and a partial filter TF2 'each with a parallel-in / serial-out structure which is more favorable for the implementation in terms of circuit technology, and in which the wiring between the filter NDF / DF' and the coefficient adjustment circuit CORR with respect to the wiring between the filter NDF / DF and the coefficients Adjustment circuit CORR is mirrored, whereby the last partial correlator 90 shown by way of example in FIG. 2 with a first coefficient multiplier 42 for variable coefficients and the first partial correlator 80 shown by way of example in FIG. 2 having a last coefficient multiplier 47 of the first partial filter TF1 ' connected is. The input signal of the sub-filter TF1 'is fed to all coefficient multipliers 42 ... 47 for variable coefficients and the input signal of the sub-filter TF2' is simultaneously fed to all coefficient multipliers 48 ... 52 for variable coefficients. A chain of delay elements 20 ... 25 and adders 64 ... 68 is provided in the partial filter TF1 ', the chain starting with the delay element 20 and an adder with a delay element connected in series following each. The output of the first coefficient multiplier 42 is via the delay element 20 with a first input of the adder 64 and one of the outputs from the coefficient multipliers 43 ... 47 is with one of the second inputs of the adders 64 ... 68 of the series after connected. In the partial filter TF2 ', the delay elements 26 ... 30 and the adders 69 ... 72 are alternately provided in the same way as in the filter TF1', the input signal of the filter TF2 'being applied via the first coefficient multiplier 48 and the delay element 26 a first input of the adder 69 and an output signal of the coefficient multipliers 41 ... 52 is fed to a second input of the adders 69 ... 72. The coefficient multipliers 42 ... 47 of the sub-filter TF1 'are in turn the coefficients Co, C-1, ... C-5 and the coefficient multipliers 48 ... 52 of the sub-filter TF2' are in sequence Coefficients C5, C4, ... Ci in the non-decimating

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Operation can be fed in parallel. In decimating operation, the coefficient multipliers 42 ... 44 are the coefficients C5 / 2, C3 / 2, ... C-5/2 and the coefficient multipliers 48 ... 52 are the coefficients C4 / 2, C2 / 2, ... C ^ / 2 can be fed in parallel in sequence. The wiring between the filter NDF / DF 'and the coefficient adjustment circuit CORR is also invariant with regard to switching between non-decimating and decimating operation.

In addition to the filters with an odd number of coefficients that are generally used, filters with an even number of coefficients are also conceivable, and a filter according to the invention, for example N = 10, can be easily derived from FIGS. 1 and 2 by the fact that in FIG. 1 the coefficient multiplier 31 and the partial correlator 80 and in FIG. 2 the coefficient multiplier 47 and the partial correlator 80 are not present.

A non-decimating filter with N coefficients can be divided into two sub-filters which are additively linked on the output side, but the second sub-filter can be supplied via a pre-delay circuit, designated V1 in FIG. 1 and FIG. 2. The pre-delay circuit generally has a pre-delay time which results from the sum of all delay times of the first sub-filter and a further delay time T. The pre-delay time of the pre-delay circuit is Int (N / 2), Int (x) being the next larger integer of x, if the number of coefficients of the first sub-filter differs by at most one coefficient from the number of coefficients of the second sub-filter, So there is a symmetrical distribution between the two sub-filters. For the filter shown in Fig. 1 and Fig. 2 with N = 11 coefficients, there is therefore a pre-delay time for the pre-delay circuit V1 of 6 T. In decimating operation, the sub-filter TF1 and the sub-filter are alternated on the demultiplexer DMUX1 clocked with the symbol rate fs TF2 is supplied with the filter input signal x, which has twice the symbol rate 2fs, for the time of 1/2 * fs, with the partial filter TF1 directly and with the partial filter TF2 via a pre-delay circuit with the delay time T / 2. The pre-delay circuit V2 in FIGS. 1 and 2 therefore also has the delay time T / 2.

In the coefficient adjustment circuit CORR, the same pre-delay times result for the pre-delay of the reference signal w in the respective operating modes as for the pre-delay of the second partial filter. This means a pre-delay time of 6 T for the pre-delay circuit V5 of FIGS. 1 and 2 and a pre-delay time of T / 2 for the pre-delay circuit V6 of FIGS. 1 and 2.

The error signal e is freely selectable depending on the desired correlation between O and NT in non-decimating mode and between O and NT / 2 in decimating mode. Often, however, a pre-delay time for pre-delaying the error signal in the non-decimating mode of (N-Int (N / 2)) T and a pre-delay time for the error signal in the decimating mode of (N-Int (N / 2)) T / 2 are selected to take into account so-called pre-oscillators in the impulse response of a channel to be equalized before the main sample and so-called post-oscillators in the impulse response of the channel in the same way. If, for example, only post-echoes occur in the channel, it may be advisable to select shorter pre-delay times for the error signal e in order to include as many post-oscillators as possible in the equalization. For the pre-delay circuit V3 in FIG. 1 and FIG. 2, this results in a pre-delay time of 5T and for the pre-delay circuit V4 in a corresponding manner a pre-delay time of 5T / 2.

Claims (2)

Claims 1. Adaptive equalizer filter - With a first demultiplexer (DMUX1) to which a filter input signal (x) can be fed, which is bridged on the output side in non-decimating mode by a switch (S1) and which is not bridged on the output side in decimating mode and whose first output is via a first partial filter ( TFI), which has coefficient multipliers (31 ... 36) for variable coefficients, is connected to a first input of an adder (62), the output of which carries a filter output signal (y), - With a first changeover switch (S2) through either, in non-decimating mode, the second output of the first demultiplexer via a series circuit comprising a first pre-delay circuit (V1) and a second sub-filter (TF2), the coefficient multiplier (37 .. . 41) for changeable coefficients, or in decimating operation, can be switched to the second input of the adder (62) via a series circuit comprising a second pre-delay circuit (V2) and the second partial filter, - With a second switch (S3), through which an error signal (e) either in non-decimating operation, via a third pre-delay circuit (V3) or, in decimating operation, via a fourth pre-delay circuit (V4) each to a first Input of a large number of partial correlators (80 ... 90) of a coefficient adjustment circuit (CORR) can be switched, - With a second demultiplexer (DMUX2), which can be supplied with a reference signal (w) on the input side, bridged on the output side in non-decimating operation by a switch (S5) and not bridged on the output side in decimating operation, and its first output with an input one first chain of delay elements (10 ... 14) is connected, - With a third changeover switch (S4) through which the second output of the second demultiplexer either in non-decimating mode, via a fifth pre-delay circuit (V5) or, in decimating mode, via a sixth pre-delay circuit 5 10th 15 20th 25th 30th 35 40 45 50 55 60 65 4th 7 CH 686 328 A5 approximately circuit (V6) with an input of a second chain of delay elements (15 ... 18) can be connected, - With first partial correlators (80, 82 ... 90), the respective outputs of which are directly connected to one of the coefficient multipliers (31 ... 36) of the first partial filter in order to obtain the respective coefficients (C-5, C-4 ... Co or C-5/2, C-3/2, ... C5 / 2), and the second inputs of which are connected to delay elements of the first chain of delay elements, - With second partial correlators (81, 83 ... 89), the respective output of which is directly connected to one of the coefficient multipliers (37, ... 41) of the second partial filter in order to convert the respective coefficients (Ci, C2, .. C5 or C-4/2, C-2/2, - C4 / 2), and the second inputs of which are connected to delay elements of the second chain of delay elements, with a first and fifth pre-delay circuit which have a pre-delay time (6T) which results from the delay time (T) of the delay elements in the sub-filters multiplied by the next larger integer number of halved coefficient numbers (N), - And with a second and sixth pre-delay circuit, which has a pre-delay time (T / 2) which corresponds to half the delay time T of the delay elements in the sub-filters. 2. Adaptive equalizer filter according to claim 1, - in which the third pre-delay circuit (V3) has a pre-delay time (5T) which results from the delay time T multiplied by the number of coefficients minus the pre-delay time of the first pre-delay circuit (V1), - And in which the fourth pre-delay circuit (V4) has a pre-delay time (5T / 2) which corresponds to half the pre-delay time of the third pre-delay circuit (V3). 5 10th 15 20th 25th 30th 35 40 45 50 55 60 65 5