CH677712A5 - - Google Patents

Description

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GH 677 712 A5

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description

The invention relates to a clamping circuit according to the preamble of claim 1.

For certain circuit parts, for example in television receivers, it is necessary to control the video signal rectified after the intermediate frequency amplifier at certain times, regardless of the picture content, to a certain DC voltage value. This process is commonly referred to as clamping.

If the video signal is to be processed digitally, e.g. According to the CCIR 601 studio standard, the input signal must be converted from analog to digital, which requires a capacitive coupling at the input of the analog-digital converter at the beginning of each image line.

If the duration of the line scan of a video signal according to CCIR 601 is 64 ps, then in the blanking interval of 10.7 ns the video signal in front of and behind the image synchronization signal is controlled to the clamping level (front and back porch).

An analog-to-digital converter according to the preamble of patent claim 1 is known from a document by Intermetall, “DIGIT 2000 / VLSI Digital TV System”, p. 112, edition 1983,

The video codec IC VCU 2100 is equipped with two inputs for analog video signals, which are decoupled in a direct current manner via a capacitance and permanently connected to an upper reference DC voltage of +12 V via a respective resistor. Signals for line (horizontal) synchronization can be fed to an analog-digital converter via both inputs, where they are converted into digital signals.

In the deflection processor unit IC DPU 2500, these digital signals are first noise-filtered by a 1 MHz low-pass filter and then by a 0.2 MHz low-pass filter before they are passed to a minimum detector and (not explained in more detail in the publication) are fed to a second detector, the latter monitoring the back porch level. Then they arrive in a comparator, which compares them with a TARGET value (clamping level) and which controls a clamping pulse generator, with the pulses of which the DC voltage level at the analog video inputs of the VCU 2100 to the TARGET -Value is regulated.

For this purpose, the inputs are switched, if necessary, with a clamping pulse of fixed duration via a second resistance to ground.

This circuit has the disadvantage that the clamping level fluctuates around the setpoint. The clamping level is only maintained over time. This means that brightness fluctuations from line to line are possible on the screen.

The invention is therefore based on the object of allowing more precise clamping.

In this way, the clamping level at the beginning of each line can be quickly set to the target level and precisely maintained.

The object is achieved as in claim 1

specified. Further developments result from the dependent claims.

The invention will now be explained in two embodiments with reference to the drawings. Show it:

1 is a basic circuit diagram of the clamp circuit according to the invention with analog-digital converter,

2 shows a diagram of the time segments I and II according to a first embodiment,

3 shows a diagram of the time period Z according to a second embodiment.

1, an analog video signal with a voltage Ua (9) is present at the input of the circuit labeled "A" and is coupled from there via a capacitor C to the input E of the analog-digital converter ADC. The DC voltage level can can be lowered or increased by closing the switches Sup or Sdo.To do this, each switch is connected on the one side to the input of the converter ADC via a resistor Rup or Rdo and on the other side to a voltage source which has a constant reference voltage Uup or Udo creates.

The two voltage sources, together with the switches Sup, Sdo and the resistors Rup, Rdo, represent a special case of a current source with controllable current direction.

In general, there must be a current source that charges or discharges the capacitor depending on the control.

If there is a constant voltage value (UA (t) = const.) At input A during a correction process (closing a switch for the duration T), then the difference between Ug (t), the voltage at the input of the converter, increases at the time t = 0 and Uup or Udo exponential! with a time constant x. The following applies to Ri »Rup, Rdo:

t = C (Rllp / üo + Ron),

where Ron is the internal resistance of the switch when closed and Ri is the internal resistance of the converter ADC.

In the first embodiment, the digital control signals Kup and Kdo, which cause the switches Sup and Sdo to open and close, are obtained by averaging the video signal values Vi occurring in the output of the converter ADC over a timeout (I) (FIG. 2) . This period (I) lies in the front area of the back porch, i.e. in the period in which the signal is to be clamped. The average digital value (ACTUAL value) is the digital equivalent of the analog terminal level at the input of the ADC converter. The averaging is used for a position still to be explained. The averaging prevents disturbing fluctuations in the voltage value from affecting the setting process.

During the time period (I), a goal

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CH677 712 A5

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Circuit To opened so that n actual-part signal values are entered in a register Regi, from which they arrive at an adder Add. The respective subtotal is temporarily stored in a register Reg2 until n values have been added up. If n was chosen as the power of two (n = 2m), then by cutting off the last m digits, a division by n can be carried out, i.e. form the arithmetic mean value which is fed to a subtractor Sub before the register Reg2 is reset to zero by an erase signal. The subtractor forms the deviation Di between the actual clamping level (actual value) and the required clamping level (desired value).

1 n

DI = ì y V - TARGET = ACTUAL - TARGET n • *

1 = 1

The sign VZ of this difference determines, on the one hand, with the aid of the control of the switch St, which of the two switches, Sup or Sdo, is actuated for the subsequent correction. On the other hand, the amount B of the difference DI together with the sign addresses a memory in which data values DA are stored in the form of a table for each difference value DI which contain the switch-on time T corresponding to the difference and required for correction as the number of counting sections of a counter Za contain.

The data values DA are loaded into the counter Za, which e.g. can be a down counter. In it, the value DA is used as the initial value of the counting process and the counting process ends when the count reaches zero. As long as the count is not equal to zero, the "ZERO" status signal is inactive and the switch Sup or Sdo selected via the switch Si with the sign VZ is closed. By assigning the differences from the averaged actual values and the specified target value to the time periods T, any connection can be made

DA = f (DI)

be taken into account.

The switching function of the switch Si shown in FIG. 1 can be implemented by a simple gate logic.

The time period II, in which the clamping level is set to a corrected level, follows the time period I required to form the mean value from the video signals Vt.

A second embodiment offers the possibility of continuously forming mean values and regulating them immediately during a time period Z (FIG. 3), so that the video signals Vi which have already been corrected after a first mean value formation are also taken into account in the averaging for forming the actual value.

A filter with a limited impulse response can be used for averaging.

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At time intervals T, the filter receives various video signals Vt through its input E, each of which is multiplied by k constant factors c [corresponding to the length of time that they have already been in the filter, and then added, such that:

IS C- V-î

i = l 1 1

k u

C1 = 1

For a quick response of the control, however, it is advantageous to choose the q such that the last digital values are weighted more heavily. This procedure increases the usable time for black shoulder correction, because in comparison to the above-mentioned averaging with the addition of an adder and two registers, not only time period I but also time period II (cf. FIG. 2) can be used.

Claims (6)

Claims 1. Clamping circuit with an analog-digital converter (ADC) and a capacitor (C), via which an analog input voltage (Ue) is fed to the analog-digital converter, with a circuit part for changing the voltage applied to the capacitor (Uc ), with a filter that forms a value from the digital output values (Vi) of the analog-to-digital converter, with a comparator that compares this value with a target value and a circuit part that, depending on the comparison result, changes the am Controls the applied voltage, characterized in that the circuit part for changing the capacitor voltage (Uc) contains a current source with a controllable current direction, which charges or discharges the capacitor (C) depending on the controlled current direction, that the comparator is a subtractor ( Sub) is that the direction of the Stro-45 mes is determined by the sign of the difference formed by the subtractor and that the switch-on time of the current source u nd the magnitude of a change in charge caused thereby in the capacitor depends on the sign and the amount of the difference. 50 2. Clamping circuit according to claim 1, characterized in that the current source consists of two voltage sources, each with a resistor (Rup, Rdo) and a switch (Sup, Sdo), which provide reference voltages (Uup, Udo) and that when a 55 is closed the two switches the capacitor (C) is charged or discharged. 3. Clamping circuit according to claim 1 or 2, characterized in that the amount of the difference and its sign address a memory (Sp) 60, in which, in the form of a table corresponding to the difference, the switch-on times of the current source required for correction as a number of Counting steps of a counter (Za) are shown and that the counting time of the counter determines the 65 switch-on time. 3rd 5 CH677712 A5 4. Clamping circuit according to one of claims 1, 2 or 3, characterized in that the filter only works during a first period (I) and that during a second period (II) following this, the analog input signal is corrected. 5. Clamping circuit according to claim 4, characterized in that the filter during the first time period (I) forms the value to be compared with the target value by arithmetic averaging from the digital output values (Vi) of the analog-digital converter (ADC). 6. Clamping circuit according to one of claims 1, 2 or 3, characterized in that the filter continuously forms the value to be compared with the desired value from the last digital output values (Vi) by weighting during a period (Z) and that the analog input signal after the first averaging is corrected continuously until the end of the time period (Z). 5 10th 15 20th 25th 30th 35 40 45 50 55 60 65 4th