CH655819A5 - EVALUATOR FOR DETECTING A SIGNAL OF A SPECIFIC FREQUENCY. - Google Patents

Description

The present invention relates to an evaluator for the detection of a signal of a specific frequency. Such evaluators are preferably used for evaluating selective call signals either in radio systems with a ringing tone or with a signal underlying the calls (tone quich) or in call receivers.

Such an evaluator basically consists of a bandpass filter with a prescribed pass frequency and bandwidth and a subsequent rectification and screening of the passed signal. A threshold value detector is then used to determine whether the signal emitted by the detector exceeds or falls below a certain threshold and thus the presence or absence of the frequency to be evaluated at the input of the evaluator. For the sake of simplicity, the frequency to be evaluated is referred to as the “target frequency”.

For example, from the article by L.E. Franks and I.W. Sandberg: "An alternative approach to the realization of network transfer functions: The N-Path Filter", published in the "Bell System Technical Journal" September 1960, pages 1321 to 1350, band filters have become known, in which several paths with low-pass filters between two cyclic switches are arranged, these switches with a frequency corresponding to the desired center frequency of the bandpass filter go through a switching cycle and on the one hand the inputs of the paths in sequence with the input and other5

10th

15

20th

25th

SO

35

■ 40

45

50

55

fit)

65

3rd

655 819

connect the outputs of the paths in turn to the output of the band pass. Half the pass bandwidth then corresponds to the cutoff frequency of the low-pass filters. The supply of sampled values of the input signal to the different paths can be viewed as a mixture of the input signal with the frequency of the circuit cycle. If the two frequencies match, the frequency is zero in the paths.

However, such an “n-path filter” has the serious disadvantage that, in addition to the target frequency, it also passes the frequency zero and all integer multiples (harmonics) of the target frequency. It has already been proposed to sieve out the even harmonics (including the frequency zero) through a filter upstream of the bandpass filter, in which an inverted signal which is delayed by half a period of the desired frequency is added to the input signal. In order to filter out the odd-numbered harmonics, a further low-pass filter is also required, which, if the target frequencies are low and if conventional means are used, requires a relatively large amount of space.

For example, from the article by R.W. Broderson, P.R. Gray and D.A. Hodges: "MOS Switched-Capacitor Filters", published in the "Proceedings of the IEEE", January 1979, pages 61 ... 75, the so-called "SC technology" is known, in which a capacity alternately with an input and is connected to an output, the whole arrangement acting like a resistor between input and output. With a capacitance connected to the output of such an artificial resistor, a low-pass filter can thus be formed, which contains only switches and capacitances and can be produced as an integrated circuit. If necessary, several such filters can be connected in series in order to achieve a desired result. The cut-off frequency of such a low-pass filter results from the switching frequency and the ratio of the interacting capacitances.

N-path band filters have already been proposed, in which the low-pass filters contained in the paths are constructed using SC technology. With these filters, the frequency of the capacity switching corresponds to the frequency of the samples. If such a filter is to be constructed as an integrated circuit, the difficulty arises that the ratio of the capacitances can only be selected within very narrow limits, which also makes it impossible to bring the bandwidth to an often desired small value.

The present invention is based on the finding that

Simplifications are possible for arrangements serving as evaluators, which merely have to determine the presence or absence of a signal of a certain frequency, compared to filter circuits used for other purposes. It makes it possible to sieve out the even harmonics within the paths, to achieve a narrow bandwidth and insensitivity to harmonics of low order and to manufacture all the parts mentioned as an integrated circuit, which considerably reduces the space requirement and the outlay in comparison with known circuits with similar properties can.

The invention relates to an evaluator for the detection of a signal of a specific frequency and contains first circuit means which sample this input signal and apply the sampled voltage values to the inputs of at least two parallel paths, these paths each containing low-pass filters constructed with switched capacitances. The invention is characterized by the features set out in the characterizing part of patent claim 1. In particular embodiments of the invention, chains of low-pass filters are used in the paths, in which the switching frequency applied in a particular filter element is lower than in the previous one.

The invention will now be described using an exemplary embodiment.

1 shows the basic diagram of an evaluation device with a narrow bandwidth.

2 and 3 show in different lines an input signal of a frequency that is to be evaluated by the device according to FIG. 1 and the chronological course of the states of a part of the switches shown in FIG. 1. The lines are labeled with the corresponding switches. The time scale is chosen eight times larger in FIG. 2 than in FIG. 3.

Fig. 4 shows the representation of a voltage follower (uni-ty gain buffer) with all details.

5 shows a comparator with all details.

The evaluation device shown in FIG. 1 has four paths to which the input signal supplied at 1 is applied. The outputs 71 ... 74 of these paths are connected to voltage followers 60, 65, 66 and 67. A comparator 64 outputs an output signal at its output 69 if the frequency of the signal supplied deviates less than half the bandwidth from the target frequency. 2 shows in line 1 a signal of the frequency to be evaluated.

Field-effect transistors are preferably used for the switches shown, which can be designed as an integrated circuit together with the capacitors also shown. The resistors shown are only shown as resistors for the sake of simplicity of illustration; they could also be implemented as switched capacities. The switches operate according to the programs shown in FIGS. 2 and 3. Their control is not shown, since such controls belong to the generally known state of the art and are not directly related to the invention.

In the following, the description of the way the paths work is preceded by some basic explanations about the technology of the switched capacitors. As can be seen, for example, from the previously mentioned literature reference, a capacitance Ci, which is alternately connected to an input and an output, is equivalent to a resistor, the value of which is inversely proportional to the switched capacitance Ci and the switching frequency fc. A low-pass filter made up of a series resistor and a parallel capacitance thus consists of a switched capacitance and a capacitance permanently connected to the output, and the frequency for 3 dB attenuation is calculated

1 C, • fc

B 2n 'C2

where Ci means the switched and C2 the capacity at the output. The cutoff frequency is therefore lower, the smaller the ratio of the two capacitances and the lower the switching frequency. The switching frequency must be at least twice the limit frequency. Such a low-pass filter has the disadvantage that it is also permeable at the switching frequency and at multiples thereof.

The sequence of switching operations in the first path is described below. The input signal is fed to all paths together at point 1. An unbalanced square wave signal is used as the input signal, i.e. a signal that periodically assumes the value zero and a unit value. The conversion, not shown, of a symmetrical sinusoidal signal into a square wave signal is assumed to be known.

5

10th

15

20th

25th

30th

35

40

45

50

55

fiO

05

655 819

4th

The signal shown in FIG. 2 line 1 corresponds to an input signal with the nominal frequency.

The square wave signal supplied at 1 is now inverted in the inverter 23, so that the original or the inverse signal is supplied to the switches 4 and 6 by optionally operating the switches 2 or 3. Switches 2 ... 7 are now operated by a program whose duration corresponds to the period of the set frequency. According to this program shown in FIG. 2, switches 2 and 3 are each conductive for half a program duration, so that the original input signal is applied to switches 4 and 6 during half of the program and the inverse input signal during the other half. The same result could be achieved if switches 2 and 3 were actuated by the input signal or its inverse value and switches 4 and 6 were alternately connected to two fixed potentials.

Switches 4 and 5 each switch eight times during a program and are alternately conductive. The capacitance 14 (e.g. 0.5 pF) is ten times smaller than the capacitance 16 (e.g. 5 pF). Since, according to the previous explanations, the switches 4 and 5 together with the capacitance 14 correspond to a resistor - if one considers the switch 8 as blocked for the time being - the potential at the capacitance 16 is an average over time of the potential curve applied to the switches 4 and 6. The signal occurring at the capacitance 16 is a mixture of the supplied signal with the program frequency and its frequency thus corresponds to the difference between that of the supplied signal and that of the program. This frequency thus depends directly on the frequency of the signal to be evaluated. If the two frequencies to be mixed coincide with one another, the potential at the capacitance 16 assumes a constant value, the size of which depends on the mutual phase relationship of the supplied signal and the program. Half the bandwidth within which a signal deviating from the target frequency is still to be evaluated is determined by the highest frequency occurring at the capacitor 16, which still causes an evaluation. This bandwidth can be selected by setting a corresponding maximum value.

As already mentioned, bandpass filters with several periodically switched lowpass filters are also permeable to signals whose frequency is a multiple of the set frequency. The previously described mixing arrangement significantly reduces this undesirable effect. Thanks to the temporary inverting of the signals at the input, the circuit does not respond to even harmonics, including zero frequency. As the operating frequency of switches 4 and 5 increases, the non-response to odd harmonics is improved. It was found that the number of eight switching cycles per program period represents a good compromise between effort and result. A further improvement in this regard is achieved by changing the resistance effective between input 1 and capacitance 16 over the course of a half period defined by switches 2 and 3. The ideal case would be a change according to a sine curve. The arrangement shown has proven to be a good compromise, in which either the capacitor 14 alone or the two capacitors 14 and 15 are brought into effect by either only the switches 4 and 5 or additionally the switch 6 simultaneously with the switch 4 and the switch 7 are operated simultaneously with the switch 5. If the same capacitance is used for the two capacitors 14 and 15, e.g. 0.5 pF selected, the capacitance values behave as 2: 1 and thus the resistance values as 1: 2. In each half period determined by switches 2 and 3, the capacitance values 1 are now, as can be seen from FIG. 2, 2, 1 made effective. According to these requirements, the approximation to the ideal case is so great that a passage at the odd multiples of the target frequency only occurs from the seventh harmonic, which is not disturbing in most applications. Not responding to even harmonics has been mentioned before.

The switches 8 and 9 in connection with the capacitances 17 and 18, the switches 10 and 11 in connection with the capacitances 19 and 20 and the switches 12 and 13 in connection with the capacitances 21 and 22 each form, in accordance with the introductory statements Low pass filter. The capacitances 18, 20 and 22 each amount to a multiple of the capacitances 17, 19 and 21. The former have a value of 1.5 pF, for example, the latter each have a value of 0.5 pF. The switching frequency of the switches 8 and 9 corresponds, as can be seen from FIG. 2, to the target frequency 2 of the evaluator. As shown in FIG. 3, on the other hand, the switching frequency of the switches 10 and 11 corresponds to a quarter and that of the switches 12 and 13 to a sixteenth of the target frequency 2. Because of the selected capacitance ratio, it results that the cutoff frequency in the first low pass -Stage is approximately 1/19 of the switching frequency and thus the target frequency, while the cut-off frequency is also four times lower compared to the previous stage due to the four times smaller switching frequency. It follows that the cut-off frequency of the third stage is approx. 300 times smaller than the target frequency, which means that the bandwidth is approx. 6.6%. The upstream of these last stages, which only determine the bandwidth, are necessary

because, according to the previous statements, a low-pass filter with switched capacitance is permeable to the switching frequency and multiples thereof. The provision of stages with a higher switching frequency makes it possible to block those frequencies at which the subsequent stage has interfering passages.

The four paths are constructed exactly the same, and the switching frequencies are the same in all paths. The only difference is in the timing of the switching times, in that at the input of the different paths, i.e. in their mixer parts, these switching times are shifted against each other. This shift, based on the period of the desired frequency, is 90 ° between successive paths. With switches 2, 32, 42 and 52, the working points of two successive ones are therefore different by 90 °, and corresponding shifts also have the switches corresponding to switches 6, 7, 8 and 9 in the other paths. The switches corresponding to switches 4 and 5 have no mutual displacements in the paths because their frequency is eight times the nominal frequency and therefore two of their periods together correspond to a phase shift of 90 ° of the nominal frequency. With switches 9 ... 13, the phase position in the different paths is irrelevant.

At outputs 71 ... 74 of the four paths, as long as a signal with a frequency deviating at most by half the permissible bandwidth from the target frequency is applied to input 1, four phases of a signal shifted by 90 ° occur, the frequency of which is between zero and half the bandwidth. With the devices described below, these signals are now processed together and it is determined whether they differ significantly from their common mean. In the ideal case of such a signal test, it would have to be determined whether the sum of the squares of the voltages by which the potentials of the signals to be tested differ from the mean value exceeds a certain threshold value. If this is the case, this is the criterion for ensuring that the frequency of a signal applied to the input lies within the bandwidth set around the target frequency. This criterion therefore represents the result of the evaluation.

In the arrangement described below, instead of

5

10th

15

20th

25th

30th

35

40

45

5 «

55

60

65

5

655 819

le of squares uses only the linear values of the deviations. The simultaneous consideration of all paths is necessary because of the occurrence of extremely low frequencies. It has been shown that the arithmetic mean of twice the absolute amount of the highest deviation and once the absolute amount of the second highest deviation is approximately proportional to the sum of the squares of the deviations and can therefore be used as a measure of the deviation.

Since the circuit is asymmetrical with respect to potentials, i.e. that the extreme values of the potentials are zero and one (unit potential), the mean value, to which the deviations relate, is half of the unit potential.

The circuit arrangement shown in FIG. 1 comprises seven voltage followers 60, 65, 66 and 67. The voltage followers each have a different number of inputs and one output each. A voltage follower assumed to be known, for example with two inputs 81 and 82, is shown in detail in FIG. 4. The potential arising at the output 83, which has a relatively small internal resistance, corresponds to the higher of the potentials applied to the two high-ohmic inputs 81 and 82.

The four voltage followers 60 are each connected between one of the outputs 71 ... 74 of the paths and a resistor 61, which connects the relevant output to point 70. This point 70 is the end point of a voltage divider consisting of resistors 62 and 63. To the tension follower

65, the outputs 71 ... 74 of all four paths and to the voltage followers 66 and 67 two of the paths are connected. The programs of the two paths, which are connected to the same voltage follower, are shifted by 180 ° to each other. The outputs of the three voltage followers 65, 66 and 67 are each connected to point 91 via an identical resistor 68.

The tap 92 of the voltage divider mentioned above and the point 91 described are each now connected to the input of a comparator 64, the mode of operation of which is assumed to be known and the details of which are shown in FIG. This comparator generates a potential at its output 69, which depends on which of the potentials is higher at its inputs.

In the case of a signal of a frequency that does not correspond to the one to be evaluated that occurs at input 1 of the evaluation device, the mean value of the potentials occurs at all four outputs of the paths. If, on the other hand, the correct frequency is available at input 1, the potentials move above and below the mean value mentioned. Since the two potentials of two paths with a phase shifted by 180 ° are always symmetrical with respect to the mean value, the deviations are of the same size and only one value has to be taken into account for the summation. A potential of two paths always appears at the outputs of the two voltage followers 66 and 67, in which the potential exceeds the mean value and the phases of which are mutually shifted by 90 ° or 270 °. At the output of the voltage follower 65, the higher of the two also appears at the outputs of the voltage follower

66 and 67 potentials. The sum of the three potentials occurring at the outputs of the voltage followers 65, 66 and 67 now corresponds to the sum set out earlier, which is decisive for the evaluation. A value proportional to this sum is now obtained by connecting the outputs of the three voltage followers 65, 66 and 67 via the resistors 68. The voltage followers 66 and 67 then contribute the highest and the second highest and the voltage follower 65 the highest value of the potentials.

The threshold value, which the mentioned value must exceed, so that the frequency of the supplied signal is recognized as the target frequency, could in principle be set as a fixed potential. In the arrangement shown in FIG. 1, however, the threshold value is determined with the aid of the measured mean value of the potentials of all four paths in order to compensate for certain differences due to asymmetries. The mean value is determined by the four voltage followers 60. The potential of point 70 adjusts to the mean. The voltage divider formed from resistors 62 and 63 adds a fixed voltage serving as a response threshold to the latter potential. The potential resulting from this sum is applied to the input 92 of the comparator 64, while the potential connected to the input 91 is proportional to the sum of the potentials generated by the voltage followers 65, 66 and 67. The two potentials applied are compared in the comparator 64, and the output potential 69, which takes one of two fixed values, thus indicates whether the frequency of the signal supplied at 1 lies within or outside the bandwidth defined around the target frequency.

The further processing of the output signal 69 of the comparator 64 can be assumed to be generally known and is therefore not described.

The resistors 61, 62, 63 and 68 shown in FIG. 1 are preferably also formed as switched capacitors. They have only been shown as resistors for the sake of simplicity.

The invention is of course not tied to the exemplary embodiment. It would also be possible with more or less than four paths to achieve satisfactory results, and the frequency of the switching movements with which the input signal is sampled could be chosen to be less than or greater than eight per period of the target frequency. The arrangement, according to which alternately a single or double capacity is brought into effect, could be restricted to an arrangement with a single capacity value and thus simplified or expanded to an arrangement with more than two capacity values and thus refined. The number of low pass elements depends on the required bandwidth and could be chosen smaller or larger than in the example.

Some of the switches could carry out additional switching movements, not shown in FIG. 2, during certain program times without this leading to changes in the characteristics of the entire arrangement. The control of the switches could possibly be simplified if such switching cycles which were in themselves superfluous were permitted.

The signals at the outputs of the paths need not be evaluated in the manner shown. If the resistors at the output of the voltage followers were replaced by switched capacitors and the output of each voltage follower and thus the entire voltage follower were only used intermittently, it would be possible to combine two voltage followers and operate the voltage followers combined in this way alternately in one or the other function .

The principles of the invention are also applicable to the processing of symmetrical digital and analog signals. However, the effort would be greater than in the described devices, in particular in the case of an implementation as an integrated circuit.

5

10th

15

20th

25th

30th

35

4 (1

45

50

55

fit)

V

2 sheets of drawings

Claims (8)

655 819 2nd PATENT CLAIMS 1. Evaluation for the detection of a signal (Fig. 2: 1) of a certain frequency, with first circuit means (2, 4, 5; ... 53, 56, 57), which sample this signal and the sampled voltage values to the inputs (16) of at least two parallel paths, each containing switched capacitors (17, 19, 21) containing paths, characterized in that the first circuit means are divided into a number corresponding to the number of paths, each of which one Path is assigned that each of these parts generates the voltage values mentioned periodically according to a program corresponding to the length of a period of the frequency to be recognized (Fig. 2: 2, 3, 4, 5, 6, 7), the signal to at least scans two points of time distributed regularly over the program duration and inverts the generated voltage values during each half of the program (23, 3, 33, 43, 53) that the first circuit means the scanning programs their r match parts in a manner according to which each program is shifted in phase with respect to the other programs, and characterized by second circuit means (60 ... 68) which match the frequency of the supplied signal (1) with the one to be recognized Determine the value by processing all signals occurring at the outputs of the individual paths at the same time. 2. An evaluator according to claim 1, in which each scanning takes place with the aid of a first (14, 15) and a second (16) capacitance, in that the first capacitance (14, 15) alternately with the voltage to be sampled and with the second capacitance ( 16) is connected, whereby a switching cycle depending on the voltage and the first capacitance dependent charge is shifted from the first to the second capacitance, characterized by switching means which have a different sized first capacitance (14; 14 + 15) during a program bring to effect, whereby different amounts of charge are shifted at the same sampled voltage at different sampling times. 3. Evaluator according to claim 2, with a third capacitance arranged per path (17) and third circuit means (8, 9) which alternately connect the third capacitance (17) with the second (16) and with a fourth (18) capacitance and thus act as a low pass filter, characterized in that the switching frequency used for the third circuit means (8, 9) is lower than the sampling frequency of the first circuit means (4, 5, 6, 7). 4. Evaluator according to claim 3, characterized in that the switching frequency used for the third switching means (8, 9) corresponds to the frequency to be evaluated, so that the voltage across the second capacitance (16) is at an average value during the execution of a program generated samples. 5. Evaluator according to claim 2, in which the program comprises eight equally spaced samples (Fig. 2: 4, 5), characterized by such a selection of said first capacitance (14, 15) that two are like 2: 1 restrained values are brought into effect and are characterized by a program (FIGS. 2: 4, 5, 6, 7), according to which four successive samples with the relative values 1, 2, 2, 1 of the first capacitance (14, 15) , followed by four inverted (23, 3) samples with the relative values 1, 2, 2, 1 of the first capacitance (14, 15), which roughly corresponds to the mixing of the supplied signal with a sine signal of the frequency to be evaluated. 6. Evaluator according to claim 4, characterized in that within each path to the fourth capacitance (18) another low-pass filter (10, 11, 19) constructed in the same way as the filter consisting of third (17) and fourth (18) capacitance , 20) is connected, the switching frequency of which is an integer fraction of that of the preceding filter (8, 9, 17, 18) and that further low-pass filters, each with a lower switching frequency than the previous filter, are connected to this latter filter in the same manner as a chain circuit are connected. 7. Evaluator according to claim 1, with four paths, the associated programs in their phase are each offset by 90 °, characterized in that the second circuit means (65, 66, 67) one of the sum of twice the amount of the highest and compare (64) the simple amount of the second highest value proportional to the potentials occurring at the outputs of the four paths with a value that is above the mean (70) of the four potentials by a certain threshold value and compare the results with the result of the comparison (69) or indicate absence of the frequency to be evaluated. 8. Evaluator according to claim 7, characterized in that the second circuit means two voltage follower (66, 67) with two inputs each, a voltage follower (65) with four inputs, circuit means (60, 61, 62, 63) for detection of the mean potential value of four input potentials and a comparator (64), the voltage followers each generating at their output an output potential corresponding to the largest of the input potentials, so that the voltage followers (66, 67) with two inputs each are connected to the outputs of two paths are whose programs are offset from each other by 180 °, that the voltage follower (65) with four inputs is connected to the outputs of all four paths and that one of the inputs of the comparator (64) is generated via one each, possibly with the aid of a switched capacitance , Resistor (68) the three outputs of the voltage followers are applied and to its other input a said average by one a certain amount exceeding potential is applied, the comparator (64), provided that of the potentials applied to it exceeds that generated by the voltage followers (65, 66, 67) mentioned above, the matching of the frequency of the input signal (1) with that recognizing value.