CH653830A5 - Four-wire line section and digital telecommunications system with a four-wire line section of this type - Google Patents

Description

The invention relates to a four-wire line section with a digital signal receiving circuit and a time-shifted, but synchronously operating digital signal transmission circuit; According to the invention, this four-wire line section is characterized in that the transmit bit clock of the digital signal transmission circuit is phase-shifted by half a bit time period compared to the reception bit clock of the digital signal reception circuit.

The invention has the advantage that the decision times at which the amplitude decision about the respective status value of the relevant bit is made in the digital signal receiving circuit when the received signal pulses are regenerated coincide at least approximately with a zero crossing of the transmitted signal pulses that interference signals originating directly from the transmission signal pulses, at most with a correspondingly low amplitude, overlap the received signal pulses at the point in time that is decisive for them. The resulting decoupling of the receiving side from the transmitting side of the four-wire line section is not only given when the interfering signal is coupled directly from the transmitting side to the receiving side of the four-wire line section - for example via a bridge circuit connecting the four-wire line section to a two-wire line; it also has an effect in terms of echoes of the transmitted signal pulses, which are caused by reflection points on such a two-wire line, in any case insofar as the transit time to and from the reflection point is short compared to half the bit period.

It should be noted at this point that it is known (for example from DE-AS 11 24 097) for time-division multiplex systems with pulse modulation that the transmitting branch and the receiving branch of a four-wire time-division multiplex line are each connected to a two-wire time-division multiplex rail at different, non-overlapping times at different times switch on, to which a two-wire subscriber line can be connected at both times using its own time channel switch. Such a two-wire, four-wire circuit, which in practice requires a relatively precise, correspondingly complex control of the three time channel switches involved in such a connection, is linked to the fact that on the two-wire time division multiplex rail, transmission channels which are separated in time for the two transmission directions are provided; Problems of a near crosstalk attenuation of a four-wire line or the crosstalk attenuation of a hybrid circuit connecting a four-wire line section with a two-wire line operated in the equilibrium method or in the frequency separation method are, however, not touched upon.

It should also be noted that [e.g. is known from «Informations Telefon-Vermittlungsstechnik» 5 (1969) 1, 48, .. 59, 53], in a four-wire line connected to a PCM exchange at its end remote from the exchange, the phase angle between demodulator and modulator by means of a Adjust the phase shifter so that the time channels of the same number appear in the incoming and outgoing direction at the end of the four-wire line near the exchange; Problems of near crosstalk attenuation of a four-wire line or crosstalk attenuation of a hybrid circuit connecting a four-wire line section to a two-wire line are not touched upon.

In a further embodiment of the invention, the received bit clock derived from the received signal pulses arriving in the digital signal receiving circuit can be supplied with a phase shift of half a bit period as the sending bit clock of the digital signal transmitting circuit forming the transmitted signal pulses. This is particularly advantageous if, in a digital telecommunications system with such a four-wire line section, the digital reception circuit of the four-wire line section on the outgoing four-wire side and the digital signal transmission circuit of the four-wire line section on the incoming four-wire side of a hybrid circuit, which is in a digital subscriber terminal whose two-wire subscriber line terminates, since in an io digital subscriber terminal the send bit clock is generally derived from the receive bit clock anyway. However, it is also expedient that, according to a further embodiment of the invention, a reception clock pulse derived from the reception signal pulses arriving in a digital signal reception circuit and the phase discriminator generated by a transmission bit clock regulates the transit time of a delay element passing through at least the received signal pulses so that Receive bit clock and transmit bit clock are out of phase with one another by half a bit period; This is particularly advantageous if, in a telecommunications system with such a four-wire line section, the digital signal reception circuit of the four-wire line section on the outgoing four-wire side and the digital signal transmission circuit of the four-wire line section on the incoming four-wire side of a hybrid circuit, which is located in a digital switching center terminates a two-wire subscriber line, the two-wire subscriber line being connected to the two-wire side of the hybrid circuit via the delay element; in a digital switching center, the send bit clock is usually generated anyway by a central office clock generator.

The invention will be explained in more detail with reference to the drawings. It shows:

Fig. 1 shows an embodiment of a digital signal telecommunication system with two four-wire line sections according to the invention;

Fig. 2 illustrates the phase shift between receive and transmit signal pulses.

In the drawing Fig. 1, a digital telecommunications system with 40 two four-wire line sections D-Tln and D-VSt is shown, one of which may be inside a digital subscriber terminal, for example a digital telephone subscriber station, while the other is in a digital switching center may; Both four-wire line sections D-Tln, D-VSt are each connected to a two-wire line Z via a hybrid circuit Gt or Gv, which may form the subscriber line.

The four-wire line section D-Tln has in its transmission branch a digital signal transmission circuit DS for transmitting transmission signal pulses s of a predetermined form or with a predetermined focus of its frequency spectrum. In the drawing, it is indicated that the transmission circuit DSt pseudo-ternary half-step signal pulses, so-called helped bauded AMI (alternate mark inversion) signal pulses. For this purpose, the transmission circuit DSt can, without being shown in detail in FIG. 1, have a code converter which converts binary signals fed to it on the input side into AMI signals, which are then pulse-shaped in a subsequent transmission filter; However, the transmission circuit DSt can also have, as 60 is suggested elsewhere (P 29 16 576.2), a coded storage of the instantaneous values of the transmit signal pulses s and controlled according to the digital signals, which feeds the corresponding instantaneous values in their coded representation to a decoder, which 65 forms the corresponding transmission signal pulses s therefrom. The transmission signal pulses s may occur with a transmission bit clock, which is supplied to the transmission circuit DSt via a transmission bit clock line tsT.

653 830

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Furthermore, the four-wire line section D-Tln has a digital signal receiving circuit DEt for receiving received signal pulses e. In Fig. 1 it is indicated that the receiving circuit DEt contains a regenerator R; In such a regenerator, as it is known in principle (for example from the Siemens publication "PCM - The Pulse Code Modulation and its Application in Telecommunications", page 15, Figure 21), the received bit pulse is derived from the received signal pulses with the aid of a clock extractor, on the basis of which the decision points in time are defined at which the amplitude decision about the respective status value of the relevant bit is made in the digital signal receiving circuit DEt. Furthermore, the receiving circuit DE can contain a received signal converter which converts the regenerated signals into corresponding binary signals, the basis of the signal forms indicated in FIG. 1 such a received signal converter being able to be formed in principle by a rectifier circuit.

The transmission signal pulses s pass from the transmission branch (DSt) of the four-wire line section D-Tnl via the hybrid circuit Gt to the two-wire line Z, via which they are transmitted to the remote station D-VSt of the digital telecommunications system shown in FIG. 1; in the opposite direction, signal pulses originating from the remote station D-VSt and transmitted via the two-wire line Z pass through the hybrid circuit Gt as received signal pulses e to the receive branch (DEt) of the four-wire line section D-Tln. With limited fork lock damping, however, portions of the transmission signal pulses s can also reach the reception branch directly, so that a reception signal mixture of the actual reception signal pulses and crosstalk signals occurs here.

Here, these crosstalk signals are largely rendered ineffective in that the transmission bit clock of the digital signal transmission circuit DSt is phase-shifted by half a bit period t / 2 compared to the reception bit clock of the digital signal reception circuit DEt. In the digital telecommunication system shown in FIG. 1, this is done in that the receive bit clock, which is derived in the regenerator R from the received signal pulses e arriving in the digital signal receiving circuit DEt, with a phase shift of half a bit time period as the transmit bit clock of the transmit signal pulses s forming digital signal transmission circuit DSt is supplied. 1 indicates that the receive bit clock derived from the regenerator R is fed via a receive bit clock line tET to a delay element t / 2 of the length of half a bit time period, to the output of which the transmit bit clock line tsT is connected.

If the receive bit clock extractor contains on the output side a bistable flip-flop switched in the pulse-pause ratio 1: 1, in deviation from the conditions indicated in FIG. 1, it is also possible for the transmit bit clock to be taken directly from a complementary output of the receive bit clock extractor.

The effect of the phase shift provided according to the invention between the transmission bit clock and the reception bit clock by half a bit period t / 2 is illustrated in FIG. 2, in which a transmission signal pulse and line e receive signal pulses are indicated in line s. As can be seen from the illustration in FIG. 2, the maxima of the received signal pulses and thus the decision times at which the amplitude decision about the respective status value of the relevant bit is made in the digital signal receiving circuit when the received signal pulses are regenerated, are at least approximated a zero crossing of the transmission signal pulses together; an interference signal originating directly from a transmission signal pulse therefore superimposes, at best with a correspondingly small amplitude, the reception signal pulse at the point in time for which this decision is decisive, so that the decoupling of the reception side from the transmission side of the four-wire line section D-Tln is correspondingly high.

Correspondingly, this decoupling is also effective with regard to echoes of the transmitted signal pulses, which may be caused by reflection points on the two-wire line Z, insofar as the transit time to or from the reflection point is short compared to half the bit period t / 2.

In the manner explained above, the received bit pulse derived from the received signal pulses e arriving in the digital signal receiving circuit DEt with a phase shift t / 2 of half a bit time period as the sending bit clock of the digital signal transmitting circuit DSt is particularly expedient when the digital signal receiving circuit and the digital signal transmitting circuit are located in a digital terminal in which the transmit bit clock is derived from the receive bit clock anyway. If, on the other hand, the digital signal reception circuit and the digital signal transmission circuit are located in a digital switching center in which the transmission bit clock is usually generated by a central clock generator, the phase shift of half a bit period between the transmission bit clock and the reception bit clock can be brought about in another way. How this can be done is shown in FIG. 1 for the four-wire line section D-VSt, which, as mentioned above, may be in a digital switching center:

The four-wire line section D-VSt has in its receiving branch a digital signal receiving circuit DEv, which is located on the outgoing four-wire side of a two-wire subscriber line Z terminating the two-wire subscriber line Z in the digital switching center D-VSt, and in its transmitting branch one on the incoming four-wire side of the hybrid circuit Gv lying digital signal transmission circuit DSv. 1 indicates that the digital signal receiving circuit DEV in turn contains a regenerator R, which derives the received bit clock from the received signal pulses arriving in the digital signal receiving circuit DEv, which then in turn appears on a receive bit clock line îev; it is also indicated that a central clock generator O generates the transmission bit clock appearing on a transmission clock line tsv. The receive bit clock line tsv and the send bit clock line tsv lead to the two inputs of a phase discriminator PD, which compares the received bit clock and the transmit bit clock. This phase discriminator PD now regulates the transit time of a delay element L, at least traversed by the received signal pulses, in such a way that the received bit clock and transmit bit clock are out of phase with one another by half a bit period. In the digital telecommunications system according to FIG. 1, the delay element L is inserted between the two-wire subscriber line Z and the hybrid circuit Gv. The runtime element L is therefore run through both by the transmit signal pulses coming from the digital switching center D-VSt and by the receive signal pulses arriving there, so that the runtime effect of the runtime element L doubles under the conditions shown in FIG. 1; the maximum settable delay time therefore only needs to be half a bit time t / 2.

The phase shift in the digital switching center D-VSt of half a bit period between the transmission bit clock and the reception bit clock in turn results in a correspondingly increased decoupling between the transmission branch and the reception branch, as has already been explained above for the digital subscriber terminal D-Tln with reference to FIG. 2. so that this need not be explained in detail here again.

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Claims (6)

653 830 2nd PATENT CLAIMS 1. Four-wire line section with a digital signal reception circuit and a time-shifted, but synchronously operating digital signal transmission circuit, characterized in that the transmission bit clock of the digital signal transmission circuit (DS) compared to the reception bit clock of the digital signal reception circuit (DE) by half a bit period (t / 2) is out of phase. 2. Four-wire line section according to claim 1, characterized in that the received bit pulse derived from the received signal pulses (et) in the digital signal receiving circuit (DEt) with a phase shift (x / 2) of half a bit time period as the transmit bit clock of the transmit signal pulses (s) forming digital signal transmission circuit (DS-r) is supplied. 3. Four-wire line section according to claim 2, characterized in that the transmit bit clock is taken from a complementary output of a receive bit clock extractor. 4. Four-wire line section according to one of claims 1 to 3, characterized in that a derived from the received in a digital signal receiving circuit (DEv) received signal pulses received bit clock and the generated by a clock generator (O) transmit bit clock comparing phase discriminator (PD) the duration of an at least of the transit time element (L) passing through the received signal pulses so that the received bit clock and the transmitted bit clock are out of phase with each other by half a bit period. 5. Digital telecommunications system with a four-wire line section according to claim 2, characterized in that the digital signal receiving circuit (DEj) of the four-wire line section on the outgoing four-wire side and the digital signal transmission circuit (DSt) of the four-wire line section on the incoming four-wire side of a hybrid circuit ( Gr), which terminates in a digital terminal (D-Tln) whose two-wire subscriber line (Z). 6. Digital telecommunications system with a four-wire line section according to claim 4, characterized in that the digital signal receiving circuit (DEv) of the four-wire line section on the outgoing four-wire side and the digital signal transmission circuit (DSv) of the four-wire line section on the incoming four-wire side of a hybrid circuit (Gv) is located, which closes a two-wire subscriber line (Z) in a digital switching center (D-VSt), the two-wire subscriber line (Z) being connected to the two-wire side of the hybrid circuit (Gv) via the delay element (L). In order to enable communication between two telecommunication points in a telecommunication system, transmission devices are required between the telecommunication points which enable a sufficiently interference-free signal transmission in both directions of transmission. For this purpose, a separate transmission line can be provided for each transmission direction, possibly in multiplex mode also for a plurality of simultaneously existing connections of two telecommunications stations; Such a four-wire operation, in which near-end crosstalk problems can occur if the received signal pulses coming from the remote transmitter and attenuated by the line are disturbed by crosstalk from their own transmitter, will preferably be provided in higher telecommunications network levels. In lower telecommunications network levels, in particular in the area of the subscriber lines, signal transmission is generally carried out over two-wire lines. In the case of transmission of analog voice signals, the separation of the transmission signals of the two transmission directions can be effected with the aid of a hybrid circuit (bridge circuit) which closes the two-wire line and which, for example, transfers the two-wire line to the four-wire part of a subscriber terminal (and vice versa). In order to achieve a complete decoupling of the receiving branch of the four-wire line leading away from the hybrid circuit to the transmitting branch of the four-wire line leading to the hybrid circuit, the hybrid circuit would have to contain an exact replica of the input impedance of the two-wire line; With a so-called compromise simulation, which is often provided in practice and with which one tries to take into account different line impedances, the hybrid circuit, which then has a finite blocking attenuation dependent on the respective line impedance, can only decouple the transmit and receive signals from one another to a limited extent , so that when connecting analog telephone subscribers there remains an (acceptable) listening in of their own language, when connecting digital telephony or data subscribers, however, due to the overlay of the received digital signals by the transmit digital signals, and thus bit errors unacceptable interference in the received signal can arise from the own transmitted signal. To counteract this, you can improve fork lock damping by using e.g. [e.g. according to Electrical Communication 53 (1978) 2, 118 ... 121] carries out an automatic adjustment of the line simulation or [e.g. according to frequency 28 (1974) 5, 118 ... 122, 121 and 155 ... 161] provides for compensation of the interference signals in the receiving branch, such compensation by adding or subtracting analog or digitally generated compensation signals in the receiving branch not eliminating them enables only the interference signals originating directly from the transmission branch, but also interference signals caused by echoes of the transmission signals in the two-wire path. In this context, it has been proposed, for example (in DE-P 29 20 575.2), to provide a read-only memory which stores coded instantaneous values of compensation signals and is controlled in accordance with the transmission signal pulses and which supplies the corresponding instantaneous values in their coded representation to a decoder (demodulator), which uses them as the basis forms a corresponding compensation signal which is subtracted from the disturbed received signal pulses. Instead of a message transmission using the same method, a decoupling of transmit and receive signals on the two-wire line can also be provided by a message using the separate method by providing separate transmission channels for the two transmission directions (e.g. according to DE-OS 27 13 854). In this context, it has already been proposed (in DE-P 28 07 785.2-32) to combine a conventional hybrid circuit with a simplified frequency division multiplexing method by separating the center of gravity of the frequency spectrum of the transmitted signals from that of the received signals by means of a frequency or code converter A frequency filter suppressing the signals of the own transmitter is inserted in the receiving branch, the blocking attenuation of which is added to that of the hybrid circuit. For this purpose, it was further proposed (in German patent application P 29 16 576.2) that for converting the frequency of the digital signals generated in a digital terminal into the transmission signal pulses to be transmitted in the transmission part of the digital terminal, instantaneous values of the transmission signal pulses are coded, stored and controlled according to the digital signals is provided, which feeds the corresponding instantaneous values in their coded representation to a decoder (demodulator), which forms the corresponding transmission signal pulses therefrom. The decoupling of transmit and receive signals 5 10th 15 20th 25th 30th 35 40 45 50 55 60 65 3rd 653 830 can be brought about according to the principles mentioned above, however, and for this purpose the invention now shows a way to increase for certain applications: